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Header cleanup, rename macros for more consistency.

This commit is contained in:
Michael Lotz 2012-12-03 22:24:32 +01:00
parent 3d4175bfe1
commit 50c463f4f1
3 changed files with 58 additions and 47 deletions
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44
headers/private/kernel/arch/arm/arm_mmu.h
View File

@ -18,21 +18,21 @@
/*
* L1 defines for the page directory (page table walk methods)
*/
#define MMU_L1_TYPE_FAULT 0x0
#define ARM_MMU_L1_TYPE_FAULT 0x0
// MMU Fault
// 31 2 10
// | |00|
#define MMU_L1_TYPE_SECTION 0x2
#define ARM_MMU_L1_TYPE_SECTION 0x2
// Single step table walk, 4096 entries
// 1024K pages, 16K consumed
// 31 20 19 12 11 10 9 8 5 432 10
// | page table address | 0? | AP |0| domain |1CB|10|
#define MMU_L1_TYPE_FINE 0x3
#define ARM_MMU_L1_TYPE_FINE 0x3
// Three(?) step table walk, 1024 entries
// 1K, 4K, 64K pages, 4K consumed
// 31 12 11 9 8 5 432 10
// | page table address | 0? | domain |100|11|
#define MMU_L1_TYPE_COARSE 0x1
#define ARM_MMU_L1_TYPE_COARSE 0x1
// Two step table walk, 256 entries
// 4K(Haiku), 64K pages, 1K consumed
// 31 10 9 8 5 432 10
@ -52,37 +52,47 @@
* I will use the old format...
*/
#define MMU_L2_TYPE_SMALLEXT 0x3
#define ARM_MMU_L2_TYPE_SMALLEXT 0x3
/* for new format entries (cortex-a8) */
#define MMU_L2_TYPE_SMALLNEW 0x2
#define ARM_MMU_L2_TYPE_SMALLNEW 0x2
// for B C and TEX see ARM arm B4-11
#define MMU_L2_FLAG_B 0x4
#define MMU_L2_FLAG_C 0x8
#define MMU_L2_FLAG_TEX 0 // use 0b000 as TEX
#define MMU_L2_FLAG_AP_RW 0x30 // allow read and write for user and system
// #define MMU_L2_FLAG_AP_
#define ARM_MMU_L2_FLAG_B 0x4
#define ARM_MMU_L2_FLAG_C 0x8
#define ARM_MMU_L2_FLAG_TEX 0 // use 0b000 as TEX
#define ARM_MMU_L2_FLAG_AP_RW 0x30
// allow read and write for user and system
#define ARM_MMU_L1_TABLE_ENTRY_COUNT 4096
#define ARM_MMU_L1_TABLE_SIZE (ARM_MMU_L1_TABLE_ENTRY_COUNT \
* sizeof(uint32))
#define MMU_L1_TABLE_SIZE (4096 * 4)
//4096 entries (one entry per MB) -> 16KB
#define MMU_L2_COARSE_TABLE_SIZE (256 * 4)
//256 entries (one entry per 4KB) -> 1KB
#define ARM_MMU_L2_COARSE_ENTRY_COUNT 256
#define ARM_MMU_L2_COARSE_TABLE_SIZE (ARM_MMU_L2_COARSE_ENTRY_COUNT \
* sizeof(uint32))
#define ARM_MMU_L2_FINE_ENTRY_COUNT 1024
#define ARM_MMU_L2_FINE_TABLE_SIZE (ARM_MMU_L2_FINE_ENTRY_COUNT \
* sizeof(uint32))
/*
* definitions for CP15 r1
*/
#define CR_R1_MMU 0x1 // enable MMU
#define CP_R1_XP 0x800000 // if XP=0 then use backwards comaptible
// translation tables
#define CP_R1_XP 0x800000
// if XP=0 then use backwards comaptible translation tables
#define VADDR_TO_PDENT(va) ((va) >> 20)
#define VADDR_TO_PTENT(va) (((va) & 0xff000) >> 12)
#define VADDR_TO_PGOFF(va) ((va) & 0x0fff)
#define ARM_PDE_ADDRESS_MASK 0xfffffc00
#define ARM_PDE_TYPE_MASK 0x00000003
#define ARM_PTE_ADDRESS_MASK 0xfffff000
#define ARM_PTE_TYPE_MASK 0x00000003
#endif /* _ARCH_ARM_ARM_MMU_H */

44
src/system/boot/arch/arm/arch_mmu.cpp
View File

@ -78,37 +78,37 @@ static struct memblock LOADER_MEMORYMAP[] = {
"devices",
DEVICE_BASE,
DEVICE_BASE + DEVICE_SIZE - 1,
MMU_L2_FLAG_B,
ARM_MMU_L2_FLAG_B,
},
{
"RAM_loader", // 1MB loader
SDRAM_BASE + 0,
SDRAM_BASE + 0x0fffff,
MMU_L2_FLAG_C,
ARM_MMU_L2_FLAG_C,
},
{
"RAM_pt", // Page Table 1MB
SDRAM_BASE + 0x100000,
SDRAM_BASE + 0x1FFFFF,
MMU_L2_FLAG_C,
ARM_MMU_L2_FLAG_C,
},
{
"RAM_free", // 16MB free RAM (more but we don't map it automaticaly)
SDRAM_BASE + 0x0200000,
SDRAM_BASE + 0x11FFFFF,
MMU_L2_FLAG_C,
ARM_MMU_L2_FLAG_C,
},
{
"RAM_stack", // stack
SDRAM_BASE + 0x1200000,
SDRAM_BASE + 0x2000000,
MMU_L2_FLAG_C,
ARM_MMU_L2_FLAG_C,
},
{
"RAM_initrd", // stack
SDRAM_BASE + 0x2000000,
SDRAM_BASE + 0x2500000,
MMU_L2_FLAG_C,
ARM_MMU_L2_FLAG_C,
},
#ifdef FB_BASE
@ -116,7 +116,7 @@ static struct memblock LOADER_MEMORYMAP[] = {
"framebuffer", // 2MB framebuffer ram
FB_BASE,
FB_BASE + FB_SIZE - 1,
MMU_L2_FLAG_AP_RW | MMU_L2_FLAG_C,
ARM_MMU_L2_FLAG_AP_RW | ARM_MMU_L2_FLAG_C,
},
#endif
};
@ -254,14 +254,14 @@ get_next_page_table(uint32 type)
size_t size = 0;
switch (type) {
case MMU_L1_TYPE_COARSE:
case ARM_MMU_L1_TYPE_COARSE:
default:
size = 1024;
size = ARM_MMU_L2_COARSE_TABLE_SIZE;
break;
case MMU_L1_TYPE_FINE:
size = 4096;
case ARM_MMU_L1_TYPE_FINE:
size = ARM_MMU_L2_FINE_TABLE_SIZE;
break;
case MMU_L1_TYPE_SECTION:
case ARM_MMU_L1_TYPE_SECTION:
size = 16384;
break;
}
@ -285,20 +285,20 @@ init_page_directory()
// see if subpages are disabled
if (mmu_read_C1() & (1 << 23))
smallType = MMU_L2_TYPE_SMALLNEW;
smallType = ARM_MMU_L2_TYPE_SMALLNEW;
else
smallType = MMU_L2_TYPE_SMALLEXT;
smallType = ARM_MMU_L2_TYPE_SMALLEXT;
gKernelArgs.arch_args.phys_pgdir = (uint32)sPageDirectory;
// clear out the page directory
for (uint32 i = 0; i < 4096; i++)
for (uint32 i = 0; i < ARM_MMU_L1_TABLE_ENTRY_COUNT; i++)
sPageDirectory[i] = 0;
uint32 *pageTable = NULL;
for (uint32 i = 0; i < ARRAY_SIZE(LOADER_MEMORYMAP); i++) {
pageTable = get_next_page_table(MMU_L1_TYPE_COARSE);
pageTable = get_next_page_table(ARM_MMU_L1_TYPE_COARSE);
TRACE(("BLOCK: %s START: %lx END %lx\n", LOADER_MEMORYMAP[i].name,
LOADER_MEMORYMAP[i].start, LOADER_MEMORYMAP[i].end));
addr_t pos = LOADER_MEMORYMAP[i].start;
@ -311,8 +311,8 @@ init_page_directory()
if (c > 255) { // we filled a pagetable => we need a new one
// there is 1MB per pagetable so:
sPageDirectory[VADDR_TO_PDENT(pos)]
= (uint32)pageTable | MMU_L1_TYPE_COARSE;
pageTable = get_next_page_table(MMU_L1_TYPE_COARSE);
= (uint32)pageTable | ARM_MMU_L1_TYPE_COARSE;
pageTable = get_next_page_table(ARM_MMU_L1_TYPE_COARSE);
c = 0;
}
@ -321,7 +321,7 @@ init_page_directory()
if (c > 0) {
sPageDirectory[VADDR_TO_PDENT(pos)]
= (uint32)pageTable | MMU_L1_TYPE_COARSE;
= (uint32)pageTable | ARM_MMU_L1_TYPE_COARSE;
}
}
@ -355,7 +355,7 @@ add_page_table(addr_t base)
TRACE(("add_page_table(base = %p)\n", (void *)base));
// Get new page table and clear it out
uint32 *pageTable = get_next_page_table(MMU_L1_TYPE_COARSE);
uint32 *pageTable = get_next_page_table(ARM_MMU_L1_TYPE_COARSE);
/*
if (pageTable > (uint32 *)(8 * 1024 * 1024)) {
panic("tried to add page table beyond the indentity mapped 8 MB "
@ -367,7 +367,7 @@ add_page_table(addr_t base)
// put the new page table into the page directory
sPageDirectory[VADDR_TO_PDENT(base)]
= (uint32)pageTable | MMU_L1_TYPE_COARSE;
= (uint32)pageTable | ARM_MMU_L1_TYPE_COARSE;
}
@ -615,7 +615,7 @@ mmu_init(void)
if (strcmp("RAM_pt", LOADER_MEMORYMAP[i].name) == 0) {
sNextPageTableAddress = LOADER_MEMORYMAP[i].start
+ MMU_L1_TABLE_SIZE;
+ ARM_MMU_L1_TABLE_SIZE;
kPageTableRegionEnd = LOADER_MEMORYMAP[i].end;
sPageDirectory = (uint32 *)LOADER_MEMORYMAP[i].start;
}

5
src/system/kernel/arch/arm/paging/32bit/ARMPagingMethod32Bit.cpp
View File

@ -314,8 +314,9 @@ ARMPagingMethod32Bit::InitPostArea(kernel_args* args)
area_id area;
temp = (void*)fKernelVirtualPageDirectory;
area = create_area("kernel_pgdir", &temp, B_EXACT_ADDRESS, MMU_L1_TABLE_SIZE,
B_ALREADY_WIRED, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA);
area = create_area("kernel_pgdir", &temp, B_EXACT_ADDRESS,
ARM_MMU_L1_TABLE_SIZE, B_ALREADY_WIRED, B_KERNEL_READ_AREA
| B_KERNEL_WRITE_AREA);
if (area < B_OK)
return area;