Header cleanup, rename macros for more consistency.
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3d4175bfe1
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50c463f4f1
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@ -18,21 +18,21 @@
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/*
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/*
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* L1 defines for the page directory (page table walk methods)
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* L1 defines for the page directory (page table walk methods)
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*/
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*/
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#define MMU_L1_TYPE_FAULT 0x0
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#define ARM_MMU_L1_TYPE_FAULT 0x0
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// MMU Fault
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// MMU Fault
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// 31 2 10
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// 31 2 10
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// | |00|
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// | |00|
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#define MMU_L1_TYPE_SECTION 0x2
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#define ARM_MMU_L1_TYPE_SECTION 0x2
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// Single step table walk, 4096 entries
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// Single step table walk, 4096 entries
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// 1024K pages, 16K consumed
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// 1024K pages, 16K consumed
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// 31 20 19 12 11 10 9 8 5 432 10
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// 31 20 19 12 11 10 9 8 5 432 10
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// | page table address | 0? | AP |0| domain |1CB|10|
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// | page table address | 0? | AP |0| domain |1CB|10|
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#define MMU_L1_TYPE_FINE 0x3
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#define ARM_MMU_L1_TYPE_FINE 0x3
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// Three(?) step table walk, 1024 entries
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// Three(?) step table walk, 1024 entries
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// 1K, 4K, 64K pages, 4K consumed
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// 1K, 4K, 64K pages, 4K consumed
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// 31 12 11 9 8 5 432 10
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// 31 12 11 9 8 5 432 10
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// | page table address | 0? | domain |100|11|
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// | page table address | 0? | domain |100|11|
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#define MMU_L1_TYPE_COARSE 0x1
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#define ARM_MMU_L1_TYPE_COARSE 0x1
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// Two step table walk, 256 entries
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// Two step table walk, 256 entries
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// 4K(Haiku), 64K pages, 1K consumed
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// 4K(Haiku), 64K pages, 1K consumed
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// 31 10 9 8 5 432 10
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// 31 10 9 8 5 432 10
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@ -52,37 +52,47 @@
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* I will use the old format...
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* I will use the old format...
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*/
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*/
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#define MMU_L2_TYPE_SMALLEXT 0x3
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#define ARM_MMU_L2_TYPE_SMALLEXT 0x3
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/* for new format entries (cortex-a8) */
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/* for new format entries (cortex-a8) */
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#define MMU_L2_TYPE_SMALLNEW 0x2
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#define ARM_MMU_L2_TYPE_SMALLNEW 0x2
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// for B C and TEX see ARM arm B4-11
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// for B C and TEX see ARM arm B4-11
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#define MMU_L2_FLAG_B 0x4
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#define ARM_MMU_L2_FLAG_B 0x4
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#define MMU_L2_FLAG_C 0x8
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#define ARM_MMU_L2_FLAG_C 0x8
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#define MMU_L2_FLAG_TEX 0 // use 0b000 as TEX
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#define ARM_MMU_L2_FLAG_TEX 0 // use 0b000 as TEX
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#define MMU_L2_FLAG_AP_RW 0x30 // allow read and write for user and system
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#define ARM_MMU_L2_FLAG_AP_RW 0x30
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// #define MMU_L2_FLAG_AP_
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// allow read and write for user and system
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#define ARM_MMU_L1_TABLE_ENTRY_COUNT 4096
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#define ARM_MMU_L1_TABLE_SIZE (ARM_MMU_L1_TABLE_ENTRY_COUNT \
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* sizeof(uint32))
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#define MMU_L1_TABLE_SIZE (4096 * 4)
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#define ARM_MMU_L2_COARSE_ENTRY_COUNT 256
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//4096 entries (one entry per MB) -> 16KB
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#define ARM_MMU_L2_COARSE_TABLE_SIZE (ARM_MMU_L2_COARSE_ENTRY_COUNT \
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#define MMU_L2_COARSE_TABLE_SIZE (256 * 4)
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* sizeof(uint32))
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//256 entries (one entry per 4KB) -> 1KB
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#define ARM_MMU_L2_FINE_ENTRY_COUNT 1024
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#define ARM_MMU_L2_FINE_TABLE_SIZE (ARM_MMU_L2_FINE_ENTRY_COUNT \
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* sizeof(uint32))
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/*
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/*
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* definitions for CP15 r1
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* definitions for CP15 r1
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*/
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*/
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#define CR_R1_MMU 0x1 // enable MMU
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#define CR_R1_MMU 0x1 // enable MMU
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#define CP_R1_XP 0x800000 // if XP=0 then use backwards comaptible
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#define CP_R1_XP 0x800000
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// translation tables
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// if XP=0 then use backwards comaptible translation tables
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#define VADDR_TO_PDENT(va) ((va) >> 20)
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#define VADDR_TO_PDENT(va) ((va) >> 20)
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#define VADDR_TO_PTENT(va) (((va) & 0xff000) >> 12)
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#define VADDR_TO_PTENT(va) (((va) & 0xff000) >> 12)
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#define VADDR_TO_PGOFF(va) ((va) & 0x0fff)
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#define VADDR_TO_PGOFF(va) ((va) & 0x0fff)
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#define ARM_PDE_ADDRESS_MASK 0xfffffc00
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#define ARM_PDE_ADDRESS_MASK 0xfffffc00
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#define ARM_PDE_TYPE_MASK 0x00000003
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#define ARM_PTE_ADDRESS_MASK 0xfffff000
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#define ARM_PTE_ADDRESS_MASK 0xfffff000
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#define ARM_PTE_TYPE_MASK 0x00000003
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#endif /* _ARCH_ARM_ARM_MMU_H */
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#endif /* _ARCH_ARM_ARM_MMU_H */
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@ -78,37 +78,37 @@ static struct memblock LOADER_MEMORYMAP[] = {
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"devices",
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"devices",
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DEVICE_BASE,
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DEVICE_BASE,
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DEVICE_BASE + DEVICE_SIZE - 1,
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DEVICE_BASE + DEVICE_SIZE - 1,
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MMU_L2_FLAG_B,
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ARM_MMU_L2_FLAG_B,
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},
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},
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{
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{
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"RAM_loader", // 1MB loader
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"RAM_loader", // 1MB loader
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SDRAM_BASE + 0,
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SDRAM_BASE + 0,
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SDRAM_BASE + 0x0fffff,
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SDRAM_BASE + 0x0fffff,
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MMU_L2_FLAG_C,
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ARM_MMU_L2_FLAG_C,
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},
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},
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{
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{
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"RAM_pt", // Page Table 1MB
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"RAM_pt", // Page Table 1MB
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SDRAM_BASE + 0x100000,
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SDRAM_BASE + 0x100000,
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SDRAM_BASE + 0x1FFFFF,
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SDRAM_BASE + 0x1FFFFF,
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MMU_L2_FLAG_C,
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ARM_MMU_L2_FLAG_C,
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},
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},
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{
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{
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"RAM_free", // 16MB free RAM (more but we don't map it automaticaly)
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"RAM_free", // 16MB free RAM (more but we don't map it automaticaly)
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SDRAM_BASE + 0x0200000,
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SDRAM_BASE + 0x0200000,
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SDRAM_BASE + 0x11FFFFF,
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SDRAM_BASE + 0x11FFFFF,
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MMU_L2_FLAG_C,
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ARM_MMU_L2_FLAG_C,
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},
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},
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{
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{
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"RAM_stack", // stack
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"RAM_stack", // stack
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SDRAM_BASE + 0x1200000,
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SDRAM_BASE + 0x1200000,
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SDRAM_BASE + 0x2000000,
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SDRAM_BASE + 0x2000000,
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MMU_L2_FLAG_C,
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ARM_MMU_L2_FLAG_C,
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},
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},
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{
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{
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"RAM_initrd", // stack
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"RAM_initrd", // stack
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SDRAM_BASE + 0x2000000,
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SDRAM_BASE + 0x2000000,
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SDRAM_BASE + 0x2500000,
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SDRAM_BASE + 0x2500000,
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MMU_L2_FLAG_C,
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ARM_MMU_L2_FLAG_C,
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},
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},
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#ifdef FB_BASE
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#ifdef FB_BASE
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@ -116,7 +116,7 @@ static struct memblock LOADER_MEMORYMAP[] = {
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"framebuffer", // 2MB framebuffer ram
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"framebuffer", // 2MB framebuffer ram
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FB_BASE,
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FB_BASE,
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FB_BASE + FB_SIZE - 1,
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FB_BASE + FB_SIZE - 1,
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MMU_L2_FLAG_AP_RW | MMU_L2_FLAG_C,
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ARM_MMU_L2_FLAG_AP_RW | ARM_MMU_L2_FLAG_C,
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},
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},
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#endif
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#endif
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};
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};
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@ -254,14 +254,14 @@ get_next_page_table(uint32 type)
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size_t size = 0;
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size_t size = 0;
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switch (type) {
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switch (type) {
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case MMU_L1_TYPE_COARSE:
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case ARM_MMU_L1_TYPE_COARSE:
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default:
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default:
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size = 1024;
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size = ARM_MMU_L2_COARSE_TABLE_SIZE;
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break;
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break;
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case MMU_L1_TYPE_FINE:
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case ARM_MMU_L1_TYPE_FINE:
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size = 4096;
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size = ARM_MMU_L2_FINE_TABLE_SIZE;
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break;
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break;
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case MMU_L1_TYPE_SECTION:
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case ARM_MMU_L1_TYPE_SECTION:
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size = 16384;
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size = 16384;
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break;
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break;
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}
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}
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@ -285,20 +285,20 @@ init_page_directory()
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// see if subpages are disabled
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// see if subpages are disabled
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if (mmu_read_C1() & (1 << 23))
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if (mmu_read_C1() & (1 << 23))
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smallType = MMU_L2_TYPE_SMALLNEW;
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smallType = ARM_MMU_L2_TYPE_SMALLNEW;
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else
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else
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smallType = MMU_L2_TYPE_SMALLEXT;
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smallType = ARM_MMU_L2_TYPE_SMALLEXT;
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gKernelArgs.arch_args.phys_pgdir = (uint32)sPageDirectory;
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gKernelArgs.arch_args.phys_pgdir = (uint32)sPageDirectory;
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// clear out the page directory
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// clear out the page directory
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for (uint32 i = 0; i < 4096; i++)
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for (uint32 i = 0; i < ARM_MMU_L1_TABLE_ENTRY_COUNT; i++)
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sPageDirectory[i] = 0;
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sPageDirectory[i] = 0;
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uint32 *pageTable = NULL;
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uint32 *pageTable = NULL;
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for (uint32 i = 0; i < ARRAY_SIZE(LOADER_MEMORYMAP); i++) {
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for (uint32 i = 0; i < ARRAY_SIZE(LOADER_MEMORYMAP); i++) {
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pageTable = get_next_page_table(MMU_L1_TYPE_COARSE);
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pageTable = get_next_page_table(ARM_MMU_L1_TYPE_COARSE);
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TRACE(("BLOCK: %s START: %lx END %lx\n", LOADER_MEMORYMAP[i].name,
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TRACE(("BLOCK: %s START: %lx END %lx\n", LOADER_MEMORYMAP[i].name,
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LOADER_MEMORYMAP[i].start, LOADER_MEMORYMAP[i].end));
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LOADER_MEMORYMAP[i].start, LOADER_MEMORYMAP[i].end));
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addr_t pos = LOADER_MEMORYMAP[i].start;
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addr_t pos = LOADER_MEMORYMAP[i].start;
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@ -311,8 +311,8 @@ init_page_directory()
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if (c > 255) { // we filled a pagetable => we need a new one
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if (c > 255) { // we filled a pagetable => we need a new one
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// there is 1MB per pagetable so:
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// there is 1MB per pagetable so:
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sPageDirectory[VADDR_TO_PDENT(pos)]
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sPageDirectory[VADDR_TO_PDENT(pos)]
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= (uint32)pageTable | MMU_L1_TYPE_COARSE;
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= (uint32)pageTable | ARM_MMU_L1_TYPE_COARSE;
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pageTable = get_next_page_table(MMU_L1_TYPE_COARSE);
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pageTable = get_next_page_table(ARM_MMU_L1_TYPE_COARSE);
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c = 0;
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c = 0;
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}
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}
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@ -321,7 +321,7 @@ init_page_directory()
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if (c > 0) {
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if (c > 0) {
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sPageDirectory[VADDR_TO_PDENT(pos)]
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sPageDirectory[VADDR_TO_PDENT(pos)]
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= (uint32)pageTable | MMU_L1_TYPE_COARSE;
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= (uint32)pageTable | ARM_MMU_L1_TYPE_COARSE;
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}
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}
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}
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}
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@ -355,7 +355,7 @@ add_page_table(addr_t base)
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TRACE(("add_page_table(base = %p)\n", (void *)base));
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TRACE(("add_page_table(base = %p)\n", (void *)base));
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// Get new page table and clear it out
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// Get new page table and clear it out
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uint32 *pageTable = get_next_page_table(MMU_L1_TYPE_COARSE);
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uint32 *pageTable = get_next_page_table(ARM_MMU_L1_TYPE_COARSE);
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/*
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/*
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if (pageTable > (uint32 *)(8 * 1024 * 1024)) {
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if (pageTable > (uint32 *)(8 * 1024 * 1024)) {
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panic("tried to add page table beyond the indentity mapped 8 MB "
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panic("tried to add page table beyond the indentity mapped 8 MB "
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@ -367,7 +367,7 @@ add_page_table(addr_t base)
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// put the new page table into the page directory
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// put the new page table into the page directory
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sPageDirectory[VADDR_TO_PDENT(base)]
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sPageDirectory[VADDR_TO_PDENT(base)]
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= (uint32)pageTable | MMU_L1_TYPE_COARSE;
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= (uint32)pageTable | ARM_MMU_L1_TYPE_COARSE;
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}
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}
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@ -615,7 +615,7 @@ mmu_init(void)
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if (strcmp("RAM_pt", LOADER_MEMORYMAP[i].name) == 0) {
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if (strcmp("RAM_pt", LOADER_MEMORYMAP[i].name) == 0) {
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sNextPageTableAddress = LOADER_MEMORYMAP[i].start
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sNextPageTableAddress = LOADER_MEMORYMAP[i].start
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+ MMU_L1_TABLE_SIZE;
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+ ARM_MMU_L1_TABLE_SIZE;
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kPageTableRegionEnd = LOADER_MEMORYMAP[i].end;
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kPageTableRegionEnd = LOADER_MEMORYMAP[i].end;
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sPageDirectory = (uint32 *)LOADER_MEMORYMAP[i].start;
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sPageDirectory = (uint32 *)LOADER_MEMORYMAP[i].start;
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}
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}
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@ -314,8 +314,9 @@ ARMPagingMethod32Bit::InitPostArea(kernel_args* args)
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area_id area;
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area_id area;
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temp = (void*)fKernelVirtualPageDirectory;
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temp = (void*)fKernelVirtualPageDirectory;
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area = create_area("kernel_pgdir", &temp, B_EXACT_ADDRESS, MMU_L1_TABLE_SIZE,
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area = create_area("kernel_pgdir", &temp, B_EXACT_ADDRESS,
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B_ALREADY_WIRED, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA);
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ARM_MMU_L1_TABLE_SIZE, B_ALREADY_WIRED, B_KERNEL_READ_AREA
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if (area < B_OK)
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if (area < B_OK)
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return area;
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return area;
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