added TLB/Cache information
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@1592 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Daniel Reinhold
parent
7ab95d9da9
commit
4fea1c8ff7
105
src/kernel/apps/cpuinfo/cpuinfo.h
Normal file
105
src/kernel/apps/cpuinfo/cpuinfo.h
Normal file
@ -0,0 +1,105 @@
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// cache-type codes
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enum cache_types {
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Unused,
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Inst_TLB,
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Data_TLB,
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L1_Inst_Cache,
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L1_Data_Cache,
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L2_Cache,
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L3_Cache,
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No_L2_Or_L3,
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Trace_Cache
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};
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// an entry in the TLB/Cache table
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typedef struct {
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uint8 descriptor;
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uint8 cache_type;
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char text[70];
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} tlbc_info;
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//
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// the global TLB/Cache table
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// technical reference:
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// "Intel Processor Identification and the CPUID instruction"
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// (ftp://ftp.intel.com/docs/24161821.pdf)
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// Page 18
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static tlbc_info
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Intel_TLB_Cache_Table[] = {
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{0x0, 0, ""},
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{0x1, Inst_TLB, "4KB pages, 4-way set associative, 32 entries"},
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{0x2, Inst_TLB, "4MB pages, fully associative, 2 entries"},
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{0x50, Inst_TLB, "4KB, 2MB or 4MB pages, fully associative, 64 entries"},
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{0x51, Inst_TLB, "4KB, 2MB or 4MB pages, fully associative, 128 entries"},
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{0x52, Inst_TLB, "4KB, 2MB or 4MB pages, fully associative, 256 entries"},
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{0x3, Data_TLB, "4KB pages, 4-way set associative, 64 entries"},
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{0x4, Data_TLB, "4MB pages, 4-way set associative, 8 entries"},
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{0x5b, Data_TLB, "4KB or 4MB pages, fully associative, 64 entries"},
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{0x5c, Data_TLB, "4KB or 4MB pages, fully associative, 128 entries"},
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{0x5d, Data_TLB, "4KB or 4MB pages, fully associative, 256 entries"},
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{0x6, L1_Inst_Cache, "8KB pages, 4-way set associative, 32 byte line size"},
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{0x8, L1_Inst_Cache, "16KB pages, 4-way set associative, 32 byte line size"},
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{0xa, L1_Data_Cache, "8KB pages, 2-way set associative, 32 byte line size"},
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{0xc, L1_Data_Cache, "16KB pages, 4-way set associative, 32 byte line size"},
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{0x66, L1_Data_Cache, "8KB pages, 4-way set associative, 64 byte line size"},
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{0x67, L1_Data_Cache, "16KB pages, 4-way set associative, 64 byte line size"},
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{0x68, L1_Data_Cache, "32KB pages, 4-way set associative, 64 byte line size"},
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{0x39, L2_Cache, "128KB pages, 4-way set associative, sectored, 64 byte line size"},
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{0x3c, L2_Cache, "256KB pages, 4-way set associative, sectored, 64 byte line size"},
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{0x41, L2_Cache, "128KB pages, 4-way set associative, 32 byte line size"},
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{0x42, L2_Cache, "256KB pages, 4-way set associative, 32 byte line size"},
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{0x43, L2_Cache, "512KB pages, 4-way set associative, 32 byte line size"},
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{0x44, L2_Cache, "1MB pages, 4-way set associative, 32 byte line size"},
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{0x45, L2_Cache, "2MB pages, 4-way set associative, 32 byte line size"},
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{0x79, L2_Cache, "128KB pages, 8-way set associative, sectored, 64 byte line size"},
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{0x7a, L2_Cache, "256KB pages, 8-way set associative, sectored, 64 byte line size"},
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{0x7b, L2_Cache, "512KB pages, 8-way set associative, sectored, 64 byte line size"},
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{0x7c, L2_Cache, "1MB pages, 8-way set associative, sectored, 64 byte line size"},
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{0x82, L2_Cache, "256KB pages, 8-way set associative, 32 byte line size"},
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{0x83, L2_Cache, "512KB pages, 8-way set associative, 32 byte line size"},
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{0x84, L2_Cache, "1MB pages, 8-way set associative, 32 byte line size"},
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{0x85, L2_Cache, "2MB pages, 8-way set associative, 32 byte line size"},
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{0x40, No_L2_Or_L3, "No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache\n"},
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{0x22, L3_Cache, "512KB pages, 4-way set associative, sectored, 64 byte line size"},
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{0x23, L3_Cache, "1MB pages, 8-way set associative, sectored, 64 byte line size"},
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{0x25, L3_Cache, "2MB pages, 8-way set associative, sectored, 64 byte line size"},
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{0x29, L3_Cache, "4MB pages, 8-way set associative, sectored, 64 byte line size"},
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{0x70, Trace_Cache, "Trace cache: 12K-uops, 8-way set associative\n"},
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{0x71, Trace_Cache, "Trace cache: 16K-uops, 8-way set associative\n"},
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{0x72, Trace_Cache, "Trace cache: 32K-uops, 8-way set associative\n"},
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};
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void AMD_identify (cpuid_info *);
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void AMD_features (cpuid_info *);
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void AMD_TLB_cache (cpuid_info *);
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void Cyrix_identify (cpuid_info *);
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void Cyrix_features (cpuid_info *);
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void Cyrix_TLB_cache (cpuid_info *);
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void Intel_identify (cpuid_info *);
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void Intel_features (cpuid_info *);
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void Intel_TLB_cache (cpuid_info *);
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const char *Intel_brand_string (int, int);
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void dump_regs (cpuid_info *, const char *, uint32, uint32);
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char getoption (char *);
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void insert (int *, int, int);
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void opt_identify (cpuid_info *, int);
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void opt_features (cpuid_info *, int);
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void opt_TLB_cache (cpuid_info *, int);
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void opt_dump_calls (cpuid_info *, uint32);
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void print_regs (cpuid_info *);
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void usage (void);
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@ -3,29 +3,10 @@
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//#include <stdlib.h> -- when exit() is implemented
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#include <string.h>
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#include "cpuinfo.h"
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#include "flag_arrays.c"
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void AMD_identify (cpuid_info *);
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void AMD_features (cpuid_info *);
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void AMD_TLB_cache (cpuid_info *);
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void Cyrix_identify (cpuid_info *);
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void Cyrix_features (cpuid_info *);
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void Cyrix_TLB_cache (cpuid_info *);
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void Intel_identify (cpuid_info *);
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void Intel_features (cpuid_info *);
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void Intel_TLB_cache (cpuid_info *);
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const char *Intel_brand_string (int, int);
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void dump_regs (cpuid_info *, const char *, uint32, uint32);
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char getoption (char *optstr);
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void opt_identify (cpuid_info *, int);
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void opt_features (cpuid_info *, int);
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void opt_TLB_cache (cpuid_info *, int);
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void opt_dump_calls (cpuid_info *, uint32);
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void print_regs (cpuid_info *);
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void usage (void);
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static cpuid_info CPU_Data;
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@ -60,9 +41,14 @@ getoption(char *optstr)
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int
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main(int argc, char *argv[])
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{
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// this program prints out everything you would ever want to know about
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// your computer's processor, or your money back, in full (30 days, no hassle)
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//
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// technical reference:
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// "Intel Processor Identification and the CPUID Instruction"
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// (ftp://download.intel.com/design/Xeon/applnots/24161821.pdf)
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// "Intel Processor Identification and the CPUID Instruction"
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// (ftp://download.intel.com/design/Xeon/applnots/24161821.pdf)
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const char *no_support = "Sorry, your processor does not support this feature\n";
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char option = 0;
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int vendor_tag;
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@ -79,24 +65,36 @@ main(int argc, char *argv[])
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// get initial info (max_level and vendor_tag)
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get_cpuid(info, 0, 0);
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max_level = info->eax_0.max_eax;
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if (max_level < 1) {
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printf("\nSorry, your computer does not seem to support the CPUID instruction\n");
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return 1;
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}
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max_level = info->eax_0.max_eax;
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vendor_tag = info->regs.ebx;
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switch (option) {
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case 'i':
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opt_identify(info, vendor_tag);
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printf("CPU identification:\n\n");
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if (max_level < 1)
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printf(no_support);
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else
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opt_identify(info, vendor_tag);
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break;
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case 'f':
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opt_features(info, vendor_tag);
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printf("Supported processor features:\n\n");
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if (max_level < 1)
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printf(no_support);
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else
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opt_features(info, vendor_tag);
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break;
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case 't':
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opt_TLB_cache(info, vendor_tag);
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printf("TLB and cache information:\n\n");
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if (max_level < 2)
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printf(no_support);
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else
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opt_TLB_cache(info, vendor_tag);
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break;
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case 'd':
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printf("CPUID instruction call dump:\n\n");
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opt_dump_calls(info, max_level);
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break;
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}
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@ -108,13 +106,15 @@ main(int argc, char *argv[])
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void
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opt_identify(cpuid_info *info, int vendor_tag)
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{
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// gosh, these CPU manufacturers have really outdone
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// themselves on creating cutesy vendorID strings, no?
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// (that was sarcasm, btw...)
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char vendorID[12+1] = {0};
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// the 'vendorid' field of the info struct is not null terminated,
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// so it is copied into a properly terminated local string buffer
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memcpy(vendorID, info->eax_0.vendorid, 12);
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printf("\nCPU identification:\n");
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printf("%12s '%s'\n", "Vendor ID:", vendorID);
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switch (vendor_tag) {
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@ -154,7 +154,7 @@ opt_features(cpuid_info *info, int vendor_tag)
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void
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opt_TLB_cache(cpuid_info *info, int vendor_tag)
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{
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{
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switch (vendor_tag) {
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case 'uneG': // "GenuineIntel"
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Intel_TLB_cache(info);
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@ -179,6 +179,10 @@ opt_TLB_cache(cpuid_info *info, int vendor_tag)
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void
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Intel_identify(cpuid_info *info)
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{
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// the code for this function looks very boring and tedious
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// (that's because it's very boring and tedious)
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// but I think it's correct anyway (there's always that possibility!)
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int type, family, model, sig;
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get_cpuid(info, 1, 0);
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@ -203,6 +207,11 @@ Intel_identify(cpuid_info *info)
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else if (family == 6) printf("Pentium Pro");
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else if (family == 15) printf("Pentium 4");
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printf("'\n");
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if (family == 15) {
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int efamily = (info->regs.eax >> 20) & 0xff;
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printf("Extended family: %d\n", efamily);
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}
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printf("%12s %2d '", "Model:", model);
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switch (family) {
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@ -300,7 +309,8 @@ Intel_brand_string(int id, int processor_signature)
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void
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Intel_features(cpuid_info *info)
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{
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//
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// for each bit set in the features flag, print out the
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// corresponding index in the flags array (too easy!)
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int i;
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int fflags;
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@ -308,7 +318,6 @@ Intel_features(cpuid_info *info)
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get_cpuid(info, 1, 0);
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fflags = info->eax_1.features;
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printf("\nSupported processor features:\n");
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for (i = 0; i < 32; ++i)
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if (fflags & (1<<i))
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printf(" %s\n", Intel_feature_flags[i]);
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@ -317,11 +326,150 @@ Intel_features(cpuid_info *info)
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}
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void
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insert (int *a, int elem, int max_index)
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{
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// inserts a new element into an ordered integer array
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// using (what else) the trusty old binary search algorithm...
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// assumes the array has sufficient space to do this
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// (i.e. it's the caller's problem to check for bounds overflow)
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int i;
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int lo = 0;
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int hi = max_index;
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int mid;
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// find insert index (will end up in lo)
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while (lo < hi) {
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mid = (lo + hi) / 2;
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if (elem < a[mid])
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hi = mid;
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else
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lo = mid + 1;
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}
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// bump up the max index (to make room for the new element)
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hi = max_index + 1;
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// move up all the items after the insert point by one
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for (i = hi; i > lo; --i)
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a[i] = a[i-1];
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// insert the new guy
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a[lo] = elem;
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}
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void
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Intel_TLB_cache(cpuid_info *info)
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{
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//get_cpuid(info, 2, 0);
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printf("\nnot just yet...\n");
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// displays technical info for the CPU's various instruction and data pipeline caches
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// and the TLBs (Translation Lookaside Buffers).
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//
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// The method for extracting and displaying this info might be less than obvious,
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// so here's an explanation:
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//
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// The TLB/Cache info is stored in a global table. Each entry is uniquely identified
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// by a descriptor byte. Additionally, each entry is catagorized according to the
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// cache type. A textual string contains the information to display.
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//
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// To retrieve the CPUs capabilities, the pass loop repeatedly (maybe) calls
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// get_cpuid() which fills the registers. Each register is a 4-byte datum,
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// capable of holding up to 4 descriptor bytes. The descriptor bytes are extracted
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// (thru shifting and masking) and then inserted into a slot array. The slot array
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// stores indexes into the table. Since descriptor bytes are not indexes themselves,
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// an index array is created and used to convert them. The slot array is filled so
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// as to keep the indexes in sorted order -- this guarantees than all entries for
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// a particular cache type will display together.
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//
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// After the pass loop is finished, the slot array contains the indexes of all the
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// table entries that apply to the host processor. Displaying the info merely a matter
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// of spinning thru the slot array and printing the text. The output is organized by
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// the cache types -- this technique *only* works because the TLB/Cache table has been
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// carefully arranged in that order.
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#define BIT_31_MASK (1 << 31)
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int pass, matches; // counters
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uint32 reg; // value of an individual register (eax, ebx, ecx, edx)
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uint8 db; // descriptor byte
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int indexOf[256] = {0}; // converts descriptor bytes to table indexes
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int slot[256] = {0}; // indexes into the TLB/Cache table (for entries found)
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tlbc_info *tab = Intel_TLB_Cache_Table;
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int tabsize = sizeof Intel_TLB_Cache_Table / sizeof(Intel_TLB_Cache_Table[0]);
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// fill the index conversion array
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int i = 0;
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int n = 0;
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while (n < tabsize)
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indexOf[tab[n++].descriptor] = i++;
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// pass loop: insert relevant table indexes into the slots array
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i = 0;
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for (pass = 0; ; ++pass) {
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get_cpuid(info, 2, 0);
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// low byte of eax register holds maximum iterations
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reg = info->regs.eax;
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if (pass >= (reg & 0xff))
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break;
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reg >>= 8; // skip low byte
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while ((db = (reg & 0xff)))
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insert(slot, indexOf[db], i++),
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reg >>= 8;
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reg = info->regs.ebx; // ebx
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if ((reg & BIT_31_MASK) == 0)
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while ((db = (reg & 0xff)))
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insert(slot, indexOf[db], i++),
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reg >>= 8;
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reg = info->regs.ecx; // ecx
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if ((reg & BIT_31_MASK) == 0)
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while ((db = (reg & 0xff)))
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insert(slot, indexOf[db], i++),
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reg >>= 8;
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reg = info->regs.edx; // edx
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if ((reg & BIT_31_MASK) == 0)
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while ((db = (reg & 0xff)))
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insert(slot, indexOf[db], i++),
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reg >>= 8;
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}
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// reset slot index for output loop
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i = 0;
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// eeiuw! an icky macro (but it really does prevent much repetitive code)
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#define display_matching_entries(type_name,type_code) \
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printf(type_name ":\n"); \
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matches = 0; \
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while (tab[n = slot[i]].cache_type == type_code) { \
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printf(" %s\n", tab[n].text); \
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++matches; \
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++i; \
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} \
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if (matches == 0) \
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printf(" None\n")
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// at long last... output the data
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display_matching_entries("Instruction TLB", Inst_TLB);
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display_matching_entries("Data TLB", Data_TLB);
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display_matching_entries("L1 Instruction Cache", L1_Inst_Cache);
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display_matching_entries("L1 Data Cache", L1_Data_Cache);
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display_matching_entries("L2 Cache", L2_Cache);
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if (tab[slot[i]].cache_type == No_L2_Or_L3)
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// no need to print the text on this one, just skip it
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++i;
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display_matching_entries("L3 Cache", L3_Cache);
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display_matching_entries("Trace Cache", Trace_Cache);
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}
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@ -388,9 +536,10 @@ Cyrix_TLB_cache(cpuid_info *info)
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void
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opt_dump_calls(cpuid_info *info, uint32 max_level)
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{
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// dumps the registers for standard (and if supported) extended
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// calls to the CPUID instruction
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uint32 max_extended;
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printf("CPUID instruction call dump:\n");
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dump_regs(info, "Standard Calls", 0, max_level);
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||||
@ -407,9 +556,11 @@ opt_dump_calls(cpuid_info *info, uint32 max_level)
|
||||
void
|
||||
dump_regs(cpuid_info *info, const char *heading, uint32 min_level, uint32 max_level)
|
||||
{
|
||||
// gosh, it's so perty (in a text-based output kind of way)
|
||||
|
||||
uint32 i;
|
||||
|
||||
printf("\n%s (max eax level = %lx)\n", heading, max_level);
|
||||
printf("%s (max eax level = %lx)\n", heading, max_level);
|
||||
printf("----------------------------------------------\n");
|
||||
printf(" Input | Output\n");
|
||||
printf("----------------------------------------------\n");
|
||||
@ -424,12 +575,17 @@ dump_regs(cpuid_info *info, const char *heading, uint32 min_level, uint32 max_le
|
||||
info->regs.ecx,
|
||||
info->regs.edx);
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
print_regs(cpuid_info *info)
|
||||
{
|
||||
// this function either prints the contents of all the
|
||||
// registers as a single character string, or it does
|
||||
// something else entirely (you decide)
|
||||
|
||||
int i;
|
||||
char s[17] = {0};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user