fix a few missed style corrections in BeceemCPU; style cleanup in BeceemDDR; no functional change
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@40850 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
parent
1687edd0fd
commit
4b7b79d52f
@ -43,11 +43,10 @@ BeceemCPU::CPURun()
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}
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// Adjust clock register contents to start cpu
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if (fWmxDevice->CPUFlashBoot) {
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clockRegister &= (~(1<<30));
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} else {
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clockRegister |= (1<<30);
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}
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if (fWmxDevice->CPUFlashBoot)
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clockRegister &= ~(1 << 30);
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else
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clockRegister |= (1 << 30);
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// Write new clock register contents
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if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
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@ -66,14 +65,13 @@ BeceemCPU::CPUReset()
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unsigned int value = 0;
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unsigned int uiResetValue = 0;
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if (fWmxDevice->deviceChipID >= T3LPB)
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{
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if (fWmxDevice->deviceChipID >= T3LPB) {
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BizarroReadRegister(SYS_CFG, sizeof(value), &value);
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BizarroReadRegister(SYS_CFG, sizeof(value), &value);
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// SYS_CFG register is write protected hence for modifying
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// this reg value, it should be read twice before writing.
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value = value | (fWmxDevice->syscfgBefFw & 0x00000060) ;
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value = value | (fWmxDevice->syscfgBefFw & 0x00000060);
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// making bit[6...5] same as was before f/w download. this
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// setting forces the h/w to re-populated the SP RAM area
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// with the string descriptor .
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@ -85,23 +83,20 @@ BeceemCPU::CPUReset()
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}
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/* Reset the UMA-B Device */
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if (fWmxDevice->deviceChipID >= T3LPB)
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{
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if (fWmxDevice->deviceChipID >= T3LPB) {
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// Reset UMA-B
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// TODO : USB reset needs implimented
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/*
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if (usb_reset_device(psIntfAdapter->udev) != B_OK)
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{
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if (usb_reset_device(psIntfAdapter->udev) != B_OK) {
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TRACE_ALWAYS("Error: USB Reset failed\n");
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retrun B_ERROR;
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}
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*/
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if (fWmxDevice->deviceChipID == BCS220_2 ||
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fWmxDevice->deviceChipID == BCS220_2BC ||
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fWmxDevice->deviceChipID == BCS250_BC ||
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fWmxDevice->deviceChipID == BCS220_3)
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{
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if (fWmxDevice->deviceChipID == BCS220_2
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|| fWmxDevice->deviceChipID == BCS220_2BC
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|| fWmxDevice->deviceChipID == BCS250_BC
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|| fWmxDevice->deviceChipID == BCS220_3) {
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if (BizarroReadRegister(HPM_CONFIG_LDO145,
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sizeof(value), &value) != B_OK) {
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TRACE_ALWAYS("Error: USB read failed during reset\n");
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@ -120,8 +115,7 @@ BeceemCPU::CPUReset()
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}
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// TODO : ELSE OLDER CHIP ID's < T3LP see Misc.c:1048
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if (fWmxDevice->CPUFlashBoot)
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{
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if (fWmxDevice->CPUFlashBoot) {
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// In flash boot mode MIPS state register has reverse polarity.
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// So just or with setting bit 30.
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// Make the MIPS in Reset state.
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@ -131,7 +125,7 @@ BeceemCPU::CPUReset()
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return B_ERROR;
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}
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// set 30th bit
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uiResetValue |=(1<<30);
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uiResetValue |= (1 << 30);
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if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
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sizeof(uiResetValue), &uiResetValue) != B_OK) {
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@ -140,17 +134,15 @@ BeceemCPU::CPUReset()
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}
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}
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if (fWmxDevice->deviceChipID >= T3LPB)
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{
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if (fWmxDevice->deviceChipID >= T3LPB) {
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uiResetValue = 0;
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// WA for SYSConfig Issue.
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BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue);
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if (uiResetValue & (1<<4))
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{
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if (uiResetValue & (1 << 4)) {
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uiResetValue = 0;
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BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue);
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// Read SYSCFG Twice to make it writable.
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uiResetValue &= (~(1<<4));
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uiResetValue &= ~(1 << 4);
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if (BizarroWriteRegister(SYS_CFG,
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sizeof(uiResetValue), &uiResetValue) != B_OK) {
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@ -16,9 +16,7 @@
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#define CLOCK_RESET_CNTRL_REG_1 0x0F00000C
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class BeceemCPU
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{
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class BeceemCPU {
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public:
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BeceemCPU();
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status_t CPUInit(WIMAX_DEVICE* swmxdevice);
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@ -9,93 +9,83 @@
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*/
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#include "Settings.h"
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#include "BeceemDDR.h"
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#include "Settings.h"
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BeceemDDR::BeceemDDR()
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{
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TRACE("Debug: Load DDR handler\n");
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TRACE("Debug: Load DDR handler\n");
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}
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status_t
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BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
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{
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pwmxdevice = swmxdevice;
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PDDR_SETTING psDDRSetting=NULL;
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fWmxDevice = swmxdevice;
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PDDR_SETTING psDDRSetting = NULL;
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unsigned int HostDrvrConfig6 = pwmxdevice->vendorcfg.HostDrvrConfig6;
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unsigned int uiHostDrvrCfg6 = 0;
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unsigned int ChipID = pwmxdevice->deviceChipID;
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unsigned int chipID = fWmxDevice->deviceChipID;
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unsigned long RegCount=0;
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unsigned long registerCount = 0;
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unsigned long value = 0;
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unsigned int uiResetValue = 0;
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unsigned int uiClockSetting = 0;
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int retval = B_OK;
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unsigned int DDRSetting = 0;
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bool PmuMode = 0;
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bool MipsConfig = 0;
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bool PLLConfig = 0;
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// Grab the Config6 metric from the vendor config and convert endianness
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unsigned int vendorConfig6raw = fWmxDevice->vendorcfg.HostDrvrConfig6;
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vendorConfig6raw &= ~(htonl(1 << 15));
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unsigned int vendorConfig6 = ntohl(vendorConfig6raw);
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HostDrvrConfig6 &= ~(htonl(1 << 15));
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uiHostDrvrCfg6 = ntohl(HostDrvrConfig6);
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// Read our vendor provided Config6 metric and populate memory settings
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unsigned int vendorDDRSetting = (ntohl(vendorConfig6raw) >> 8) & 0x0F;
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bool vendorPmuMode = (vendorConfig6 >> 24) & 0x03;
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bool vendorMipsConfig = (vendorConfig6 >> 20) & 0x01;
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bool vendorPLLConfig = (vendorConfig6 >> 19) & 0x01;
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DDRSetting = (ntohl(HostDrvrConfig6) >>8)&0x0F ;
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PmuMode = (uiHostDrvrCfg6>>24)&0x03;
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MipsConfig = (uiHostDrvrCfg6>>20)&0x01;
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PLLConfig = (uiHostDrvrCfg6>>19)&0x01;
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switch (chipID) {
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case 0xbece3200:
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switch (vendorDDRSetting) {
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case DDR_80_MHZ:
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psDDRSetting = asT3LP_DDRSetting80MHz;
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registerCount = sizeof(asT3LP_DDRSetting80MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_100_MHZ:
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psDDRSetting = asT3LP_DDRSetting100MHz;
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registerCount = sizeof(asT3LP_DDRSetting100MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_133_MHZ:
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psDDRSetting = asT3LP_DDRSetting133MHz;
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registerCount = sizeof(asT3LP_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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switch (ChipID)
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{
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case 0xbece3200:
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switch (DDRSetting)
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{
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case DDR_80_MHZ:
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psDDRSetting=asT3LP_DDRSetting80MHz;
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RegCount=(sizeof(asT3LP_DDRSetting80MHz)/
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sizeof(DDR_SETTING));
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break;
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case DDR_100_MHZ:
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psDDRSetting=asT3LP_DDRSetting100MHz;
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RegCount=(sizeof(asT3LP_DDRSetting100MHz)/
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sizeof(DDR_SETTING));
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break;
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case DDR_133_MHZ:
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psDDRSetting=asT3LP_DDRSetting133MHz;
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RegCount=(sizeof(asT3LP_DDRSetting133MHz)/
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sizeof(DDR_SETTING));
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if(MipsConfig == MIPS_200_MHZ)
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{
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uiClockSetting = 0x03F13652;
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}
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else
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{
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uiClockSetting = 0x03F1365B;
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}
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break;
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default:
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return -EINVAL;
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}
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if (vendorMipsConfig == MIPS_200_MHZ)
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uiClockSetting = 0x03F13652;
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else
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uiClockSetting = 0x03F1365B;
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break;
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default:
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return -EINVAL;
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}
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break;
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break;
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case T3LPB:
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case BCS220_2:
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case BCS220_2BC:
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case BCS250_BC:
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case BCS220_3 :
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// We need to check current value and additionally set bit 2 and
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// bit 6 to 1 for BBIC 2mA drive
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if( (ChipID != BCS220_2) &&
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(ChipID != BCS220_2BC) &&
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(ChipID != BCS220_3) )
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{
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retval= BizarroReadRegister((unsigned int)0x0f000830,
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case T3LPB:
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case BCS220_2:
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case BCS220_2BC:
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case BCS250_BC:
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case BCS220_3 :
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// We need to check current value and additionally set bit 2 and
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// bit 6 to 1 for BBIC 2mA drive
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if ((chipID != BCS220_2)
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&& (chipID != BCS220_2BC)
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&& (chipID != BCS220_3)) {
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retval = BizarroReadRegister((unsigned int)0x0f000830,
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sizeof(uiResetValue), &uiResetValue);
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if(retval < 0) {
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if (retval < 0) {
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TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
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__FUNCTION__, __LINE__);
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return retval;
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@ -103,172 +93,155 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
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uiResetValue |= 0x44;
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retval = BizarroWriteRegister((unsigned int)0x0f000830,
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sizeof(uiResetValue), &uiResetValue);
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if(retval < 0) {
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if (retval < 0) {
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TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
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__FUNCTION__, __LINE__);
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return retval;
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}
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}
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switch(DDRSetting)
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{
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case DDR_80_MHZ:
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TRACE("Debug: DDR 80MHz\n");
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psDDRSetting = asT3LPB_DDRSetting80MHz;
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RegCount=(sizeof(asT3B_DDRSetting80MHz)/
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sizeof(DDR_SETTING));
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break;
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case DDR_100_MHZ:
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TRACE("Debug: DDR 100MHz\n");
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psDDRSetting=asT3LPB_DDRSetting100MHz;
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RegCount=(sizeof(asT3B_DDRSetting100MHz)/
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sizeof(DDR_SETTING));
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break;
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case DDR_133_MHZ:
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TRACE("Debug: DDR 133MHz\n");
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psDDRSetting = asT3LPB_DDRSetting133MHz;
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RegCount=(sizeof(asT3B_DDRSetting133MHz)/
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sizeof(DDR_SETTING));
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}
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if(MipsConfig == MIPS_200_MHZ)
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{
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uiClockSetting = 0x03F13652;
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}
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else
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{
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uiClockSetting = 0x03F1365B;
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}
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break;
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switch(vendorDDRSetting) {
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case DDR_80_MHZ:
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TRACE("Debug: DDR 80MHz\n");
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psDDRSetting = asT3LPB_DDRSetting80MHz;
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registerCount = sizeof(asT3B_DDRSetting80MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_100_MHZ:
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TRACE("Debug: DDR 100MHz\n");
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psDDRSetting = asT3LPB_DDRSetting100MHz;
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registerCount = sizeof(asT3B_DDRSetting100MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_133_MHZ:
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TRACE("Debug: DDR 133MHz\n");
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psDDRSetting = asT3LPB_DDRSetting133MHz;
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registerCount = sizeof(asT3B_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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case DDR_160_MHZ:
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TRACE("Debug: DDR 160MHz\n");
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psDDRSetting = asT3LPB_DDRSetting160MHz;
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RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SETTING);
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if (vendorMipsConfig == MIPS_200_MHZ)
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uiClockSetting = 0x03F13652;
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else
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uiClockSetting = 0x03F1365B;
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break;
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if(MipsConfig == MIPS_200_MHZ)
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{
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TRACE("Debug: MIPS 200Mhz\n");
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uiClockSetting = 0x03F137D2;
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}
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else
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{
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uiClockSetting = 0x03F137DB;
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}
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case DDR_160_MHZ:
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TRACE("Debug: DDR 160MHz\n");
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psDDRSetting = asT3LPB_DDRSetting160MHz;
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registerCount = sizeof(asT3LPB_DDRSetting160MHz)
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/ sizeof(DDR_SETTING);
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if (vendorMipsConfig == MIPS_200_MHZ) {
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TRACE("Debug: MIPS 200Mhz\n");
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uiClockSetting = 0x03F137D2;
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} else {
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uiClockSetting = 0x03F137DB;
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}
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}
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break;
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case 0xbece0110:
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case 0xbece0120:
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case 0xbece0121:
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case 0xbece0130:
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case 0xbece0300:
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switch (DDRSetting)
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{
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case DDR_80_MHZ:
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psDDRSetting = asT3_DDRSetting80MHz;
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RegCount = (sizeof(asT3_DDRSetting80MHz)/
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sizeof(DDR_SETTING));
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break;
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case DDR_100_MHZ:
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psDDRSetting = asT3_DDRSetting100MHz;
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RegCount = (sizeof(asT3_DDRSetting100MHz)/
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sizeof(DDR_SETTING));
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break;
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case DDR_133_MHZ:
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psDDRSetting = asT3_DDRSetting133MHz;
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RegCount = (sizeof(asT3_DDRSetting133MHz)/
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sizeof(DDR_SETTING));
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break;
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default:
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return -EINVAL;
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}
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case 0xbece0310:
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{
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switch (DDRSetting)
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{
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case DDR_80_MHZ:
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psDDRSetting = asT3B_DDRSetting80MHz;
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RegCount=(sizeof(asT3B_DDRSetting80MHz)/
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sizeof(DDR_SETTING));
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break;
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case DDR_100_MHZ:
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psDDRSetting=asT3B_DDRSetting100MHz;
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RegCount=(sizeof(asT3B_DDRSetting100MHz)/
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sizeof(DDR_SETTING));
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case 0xbece0110:
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case 0xbece0120:
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case 0xbece0121:
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case 0xbece0130:
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case 0xbece0300:
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switch (vendorDDRSetting) {
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case DDR_80_MHZ:
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psDDRSetting = asT3_DDRSetting80MHz;
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registerCount = sizeof(asT3_DDRSetting80MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_100_MHZ:
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psDDRSetting = asT3_DDRSetting100MHz;
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registerCount = sizeof(asT3_DDRSetting100MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_133_MHZ:
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psDDRSetting = asT3_DDRSetting133MHz;
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registerCount = sizeof(asT3_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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break;
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default:
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return -EINVAL;
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}
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case 0xbece0310:
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{
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switch (vendorDDRSetting) {
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case DDR_80_MHZ:
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psDDRSetting = asT3B_DDRSetting80MHz;
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registerCount = sizeof(asT3B_DDRSetting80MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_100_MHZ:
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psDDRSetting = asT3B_DDRSetting100MHz;
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registerCount = sizeof(asT3B_DDRSetting100MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_133_MHZ:
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if (vendorPLLConfig == PLL_266_MHZ) {
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// 266Mhz PLL selected.
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memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
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sizeof(asDPLL_266MHZ));
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psDDRSetting = asT3B_DDRSetting133MHz;
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registerCount = sizeof(asT3B_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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} else {
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psDDRSetting = asT3B_DDRSetting133MHz;
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registerCount = sizeof(asT3B_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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if (vendorMipsConfig == MIPS_200_MHZ)
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uiClockSetting = 0x07F13652;
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else
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uiClockSetting = 0x07F1365B;
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}
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break;
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default:
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return -EINVAL;
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}
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break;
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case DDR_133_MHZ:
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if(PLLConfig == PLL_266_MHZ)//266Mhz PLL selected.
|
||||
{
|
||||
memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
|
||||
sizeof(asDPLL_266MHZ));
|
||||
psDDRSetting = asT3B_DDRSetting133MHz;
|
||||
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
|
||||
sizeof(DDR_SETTING));
|
||||
}
|
||||
else
|
||||
{
|
||||
psDDRSetting = asT3B_DDRSetting133MHz;
|
||||
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
|
||||
sizeof(DDR_SETTING));
|
||||
if(MipsConfig == MIPS_200_MHZ)
|
||||
{
|
||||
uiClockSetting = 0x07F13652;
|
||||
}
|
||||
else
|
||||
{
|
||||
uiClockSetting = 0x07F1365B;
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
|
||||
}
|
||||
default:
|
||||
return -EINVAL;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
value=0;
|
||||
TRACE("Debug: Register count is %lu\n", RegCount);
|
||||
while(RegCount && !retval)
|
||||
{
|
||||
if(uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
|
||||
{
|
||||
value = 0;
|
||||
TRACE("Debug: Register count is %lu\n", registerCount);
|
||||
while (registerCount && !retval) {
|
||||
if (uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
|
||||
value = uiClockSetting;
|
||||
}
|
||||
else
|
||||
{
|
||||
value = psDDRSetting->ulRegValue;
|
||||
}
|
||||
|
||||
retval = BizarroWriteRegister(psDDRSetting->ulRegAddress,
|
||||
sizeof(value), (unsigned int*)&value);
|
||||
|
||||
if(B_OK != retval) {
|
||||
if (B_OK != retval) {
|
||||
TRACE_ALWAYS(
|
||||
"%s:%d BizarroWriteRegister failed at 0x%x on Register #%d.\n",
|
||||
__FUNCTION__, __LINE__, psDDRSetting->ulRegAddress, RegCount);
|
||||
__FUNCTION__, __LINE__, psDDRSetting->ulRegAddress,
|
||||
registerCount);
|
||||
break;
|
||||
}
|
||||
|
||||
RegCount--;
|
||||
registerCount--;
|
||||
psDDRSetting++;
|
||||
}
|
||||
|
||||
if(ChipID >= 0xbece3300 )
|
||||
{
|
||||
if (chipID >= 0xbece3300) {
|
||||
snooze(3);
|
||||
if( (ChipID != BCS220_2)&&
|
||||
(ChipID != BCS220_2BC)&&
|
||||
(ChipID != BCS220_3))
|
||||
{
|
||||
if ((chipID != BCS220_2)
|
||||
&& (chipID != BCS220_2BC)
|
||||
&& (chipID != BCS220_3)) {
|
||||
/* drive MDDR to half in case of UMA-B: */
|
||||
uiResetValue = 0x01010001;
|
||||
retval = BizarroWriteRegister((unsigned int)0x0F007018,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
@ -277,7 +250,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
|
||||
retval = BizarroWriteRegister((unsigned int)0x0F007094,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
@ -286,7 +259,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
|
||||
retval = BizarroWriteRegister((unsigned int)0x0F00701c,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
@ -295,7 +268,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
|
||||
retval = BizarroWriteRegister((unsigned int)0x0F007018,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
@ -310,20 +283,19 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
|
||||
* UMA-B chip id. we will change this when we will have an
|
||||
* internal PMU.
|
||||
*/
|
||||
if(PmuMode == HYBRID_MODE_7C)
|
||||
{
|
||||
if (vendorPmuMode == HYBRID_MODE_7C) {
|
||||
TRACE("Debug: Hybrid Power Mode 7C\n");
|
||||
retval = BizarroReadRegister((unsigned int)0x0f000c00,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
}
|
||||
retval = BizarroReadRegister((unsigned int)0x0f000c00,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
@ -331,21 +303,21 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
|
||||
uiResetValue = 0x1322a8;
|
||||
retval = BizarroWriteRegister((unsigned int)0x0f000d1c,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
}
|
||||
retval = BizarroReadRegister((unsigned int)0x0f000c00,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
}
|
||||
retval = BizarroReadRegister((unsigned int)0x0f000c00,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
@ -353,25 +325,24 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
|
||||
uiResetValue = 0x132296;
|
||||
retval = BizarroWriteRegister((unsigned int)0x0f000d14,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
}
|
||||
}
|
||||
else if(PmuMode == HYBRID_MODE_6 )
|
||||
{
|
||||
} else if (vendorPmuMode == HYBRID_MODE_6) {
|
||||
|
||||
TRACE("Debug: Hybrid Power Mode 6\n");
|
||||
retval = BizarroReadRegister((unsigned int)0x0f000c00,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
}
|
||||
retval = BizarroReadRegister((unsigned int)0x0f000c00,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
@ -379,21 +350,21 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
|
||||
uiResetValue = 0x6003229a;
|
||||
retval = BizarroWriteRegister((unsigned int)0x0f000d14,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
}
|
||||
retval = BizarroReadRegister((unsigned int)0x0f000c00,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
}
|
||||
retval = BizarroReadRegister((unsigned int)0x0f000c00,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
@ -401,7 +372,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
|
||||
uiResetValue = 0x1322a8;
|
||||
retval = BizarroWriteRegister((unsigned int)0x0f000d1c,
|
||||
sizeof(uiResetValue), &uiResetValue);
|
||||
if(retval < 0) {
|
||||
if (retval < 0) {
|
||||
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return retval;
|
||||
|
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user