fix a few missed style corrections in BeceemCPU; style cleanup in BeceemDDR; no functional change
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@40850 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
parent
1687edd0fd
commit
4b7b79d52f
@ -43,11 +43,10 @@ BeceemCPU::CPURun()
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}
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// Adjust clock register contents to start cpu
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if (fWmxDevice->CPUFlashBoot) {
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clockRegister &= (~(1<<30));
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} else {
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if (fWmxDevice->CPUFlashBoot)
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clockRegister &= ~(1 << 30);
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else
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clockRegister |= (1 << 30);
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}
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// Write new clock register contents
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if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
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@ -66,8 +65,7 @@ BeceemCPU::CPUReset()
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unsigned int value = 0;
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unsigned int uiResetValue = 0;
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if (fWmxDevice->deviceChipID >= T3LPB)
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{
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if (fWmxDevice->deviceChipID >= T3LPB) {
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BizarroReadRegister(SYS_CFG, sizeof(value), &value);
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BizarroReadRegister(SYS_CFG, sizeof(value), &value);
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// SYS_CFG register is write protected hence for modifying
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@ -85,23 +83,20 @@ BeceemCPU::CPUReset()
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}
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/* Reset the UMA-B Device */
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if (fWmxDevice->deviceChipID >= T3LPB)
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{
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if (fWmxDevice->deviceChipID >= T3LPB) {
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// Reset UMA-B
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// TODO : USB reset needs implimented
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/*
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if (usb_reset_device(psIntfAdapter->udev) != B_OK)
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{
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if (usb_reset_device(psIntfAdapter->udev) != B_OK) {
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TRACE_ALWAYS("Error: USB Reset failed\n");
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retrun B_ERROR;
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}
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*/
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if (fWmxDevice->deviceChipID == BCS220_2 ||
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fWmxDevice->deviceChipID == BCS220_2BC ||
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fWmxDevice->deviceChipID == BCS250_BC ||
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fWmxDevice->deviceChipID == BCS220_3)
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{
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if (fWmxDevice->deviceChipID == BCS220_2
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|| fWmxDevice->deviceChipID == BCS220_2BC
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|| fWmxDevice->deviceChipID == BCS250_BC
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|| fWmxDevice->deviceChipID == BCS220_3) {
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if (BizarroReadRegister(HPM_CONFIG_LDO145,
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sizeof(value), &value) != B_OK) {
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TRACE_ALWAYS("Error: USB read failed during reset\n");
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@ -120,8 +115,7 @@ BeceemCPU::CPUReset()
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}
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// TODO : ELSE OLDER CHIP ID's < T3LP see Misc.c:1048
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if (fWmxDevice->CPUFlashBoot)
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{
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if (fWmxDevice->CPUFlashBoot) {
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// In flash boot mode MIPS state register has reverse polarity.
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// So just or with setting bit 30.
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// Make the MIPS in Reset state.
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@ -140,17 +134,15 @@ BeceemCPU::CPUReset()
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}
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}
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if (fWmxDevice->deviceChipID >= T3LPB)
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{
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if (fWmxDevice->deviceChipID >= T3LPB) {
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uiResetValue = 0;
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// WA for SYSConfig Issue.
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BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue);
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if (uiResetValue & (1<<4))
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{
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if (uiResetValue & (1 << 4)) {
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uiResetValue = 0;
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BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue);
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// Read SYSCFG Twice to make it writable.
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uiResetValue &= (~(1<<4));
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uiResetValue &= ~(1 << 4);
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if (BizarroWriteRegister(SYS_CFG,
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sizeof(uiResetValue), &uiResetValue) != B_OK) {
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@ -16,9 +16,7 @@
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#define CLOCK_RESET_CNTRL_REG_1 0x0F00000C
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class BeceemCPU
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{
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class BeceemCPU {
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public:
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BeceemCPU();
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status_t CPUInit(WIMAX_DEVICE* swmxdevice);
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@ -9,8 +9,8 @@
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*/
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#include "Settings.h"
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#include "BeceemDDR.h"
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#include "Settings.h"
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BeceemDDR::BeceemDDR()
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@ -22,65 +22,56 @@ BeceemDDR::BeceemDDR()
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status_t
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BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
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{
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pwmxdevice = swmxdevice;
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fWmxDevice = swmxdevice;
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PDDR_SETTING psDDRSetting = NULL;
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unsigned int HostDrvrConfig6 = pwmxdevice->vendorcfg.HostDrvrConfig6;
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unsigned int uiHostDrvrCfg6 = 0;
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unsigned int ChipID = pwmxdevice->deviceChipID;
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unsigned int chipID = fWmxDevice->deviceChipID;
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unsigned long RegCount=0;
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unsigned long registerCount = 0;
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unsigned long value = 0;
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unsigned int uiResetValue = 0;
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unsigned int uiClockSetting = 0;
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int retval = B_OK;
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unsigned int DDRSetting = 0;
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bool PmuMode = 0;
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bool MipsConfig = 0;
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bool PLLConfig = 0;
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// Grab the Config6 metric from the vendor config and convert endianness
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unsigned int vendorConfig6raw = fWmxDevice->vendorcfg.HostDrvrConfig6;
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vendorConfig6raw &= ~(htonl(1 << 15));
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unsigned int vendorConfig6 = ntohl(vendorConfig6raw);
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HostDrvrConfig6 &= ~(htonl(1 << 15));
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uiHostDrvrCfg6 = ntohl(HostDrvrConfig6);
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// Read our vendor provided Config6 metric and populate memory settings
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unsigned int vendorDDRSetting = (ntohl(vendorConfig6raw) >> 8) & 0x0F;
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bool vendorPmuMode = (vendorConfig6 >> 24) & 0x03;
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bool vendorMipsConfig = (vendorConfig6 >> 20) & 0x01;
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bool vendorPLLConfig = (vendorConfig6 >> 19) & 0x01;
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DDRSetting = (ntohl(HostDrvrConfig6) >>8)&0x0F ;
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PmuMode = (uiHostDrvrCfg6>>24)&0x03;
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MipsConfig = (uiHostDrvrCfg6>>20)&0x01;
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PLLConfig = (uiHostDrvrCfg6>>19)&0x01;
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switch (ChipID)
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{
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switch (chipID) {
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case 0xbece3200:
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switch (DDRSetting)
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{
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switch (vendorDDRSetting) {
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case DDR_80_MHZ:
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psDDRSetting = asT3LP_DDRSetting80MHz;
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RegCount=(sizeof(asT3LP_DDRSetting80MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3LP_DDRSetting80MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_100_MHZ:
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psDDRSetting = asT3LP_DDRSetting100MHz;
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RegCount=(sizeof(asT3LP_DDRSetting100MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3LP_DDRSetting100MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_133_MHZ:
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psDDRSetting = asT3LP_DDRSetting133MHz;
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RegCount=(sizeof(asT3LP_DDRSetting133MHz)/
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sizeof(DDR_SETTING));
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if(MipsConfig == MIPS_200_MHZ)
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{
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registerCount = sizeof(asT3LP_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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if (vendorMipsConfig == MIPS_200_MHZ)
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uiClockSetting = 0x03F13652;
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}
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else
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{
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uiClockSetting = 0x03F1365B;
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}
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break;
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default:
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return -EINVAL;
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}
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break;
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case T3LPB:
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case BCS220_2:
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case BCS220_2BC:
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@ -88,10 +79,9 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
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case BCS220_3 :
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// We need to check current value and additionally set bit 2 and
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// bit 6 to 1 for BBIC 2mA drive
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if( (ChipID != BCS220_2) &&
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(ChipID != BCS220_2BC) &&
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(ChipID != BCS220_3) )
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{
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if ((chipID != BCS220_2)
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&& (chipID != BCS220_2BC)
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&& (chipID != BCS220_3)) {
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retval = BizarroReadRegister((unsigned int)0x0f000830,
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sizeof(uiResetValue), &uiResetValue);
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@ -109,48 +99,42 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
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return retval;
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}
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}
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switch(DDRSetting)
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{
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switch(vendorDDRSetting) {
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case DDR_80_MHZ:
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TRACE("Debug: DDR 80MHz\n");
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psDDRSetting = asT3LPB_DDRSetting80MHz;
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RegCount=(sizeof(asT3B_DDRSetting80MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3B_DDRSetting80MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_100_MHZ:
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TRACE("Debug: DDR 100MHz\n");
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psDDRSetting = asT3LPB_DDRSetting100MHz;
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RegCount=(sizeof(asT3B_DDRSetting100MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3B_DDRSetting100MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_133_MHZ:
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TRACE("Debug: DDR 133MHz\n");
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psDDRSetting = asT3LPB_DDRSetting133MHz;
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RegCount=(sizeof(asT3B_DDRSetting133MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3B_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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if(MipsConfig == MIPS_200_MHZ)
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{
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if (vendorMipsConfig == MIPS_200_MHZ)
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uiClockSetting = 0x03F13652;
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}
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else
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{
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uiClockSetting = 0x03F1365B;
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}
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break;
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case DDR_160_MHZ:
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TRACE("Debug: DDR 160MHz\n");
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psDDRSetting = asT3LPB_DDRSetting160MHz;
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RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SETTING);
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registerCount = sizeof(asT3LPB_DDRSetting160MHz)
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/ sizeof(DDR_SETTING);
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if(MipsConfig == MIPS_200_MHZ)
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{
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if (vendorMipsConfig == MIPS_200_MHZ) {
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TRACE("Debug: MIPS 200Mhz\n");
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uiClockSetting = 0x03F137D2;
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}
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else
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{
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} else {
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uiClockSetting = 0x03F137DB;
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}
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}
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@ -161,108 +145,97 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
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case 0xbece0121:
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case 0xbece0130:
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case 0xbece0300:
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switch (DDRSetting)
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{
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switch (vendorDDRSetting) {
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case DDR_80_MHZ:
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psDDRSetting = asT3_DDRSetting80MHz;
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RegCount = (sizeof(asT3_DDRSetting80MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3_DDRSetting80MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_100_MHZ:
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psDDRSetting = asT3_DDRSetting100MHz;
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RegCount = (sizeof(asT3_DDRSetting100MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3_DDRSetting100MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_133_MHZ:
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psDDRSetting = asT3_DDRSetting133MHz;
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RegCount = (sizeof(asT3_DDRSetting133MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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break;
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default:
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return -EINVAL;
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}
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case 0xbece0310:
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{
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switch (DDRSetting)
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{
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switch (vendorDDRSetting) {
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case DDR_80_MHZ:
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psDDRSetting = asT3B_DDRSetting80MHz;
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RegCount=(sizeof(asT3B_DDRSetting80MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3B_DDRSetting80MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_100_MHZ:
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psDDRSetting = asT3B_DDRSetting100MHz;
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RegCount=(sizeof(asT3B_DDRSetting100MHz)/
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sizeof(DDR_SETTING));
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registerCount = sizeof(asT3B_DDRSetting100MHz)
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/ sizeof(DDR_SETTING);
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break;
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case DDR_133_MHZ:
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if(PLLConfig == PLL_266_MHZ)//266Mhz PLL selected.
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{
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if (vendorPLLConfig == PLL_266_MHZ) {
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// 266Mhz PLL selected.
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memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
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sizeof(asDPLL_266MHZ));
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psDDRSetting = asT3B_DDRSetting133MHz;
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RegCount=(sizeof(asT3B_DDRSetting133MHz)/
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sizeof(DDR_SETTING));
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}
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else
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{
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registerCount = sizeof(asT3B_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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} else {
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psDDRSetting = asT3B_DDRSetting133MHz;
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RegCount=(sizeof(asT3B_DDRSetting133MHz)/
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sizeof(DDR_SETTING));
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if(MipsConfig == MIPS_200_MHZ)
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{
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registerCount = sizeof(asT3B_DDRSetting133MHz)
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/ sizeof(DDR_SETTING);
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if (vendorMipsConfig == MIPS_200_MHZ)
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uiClockSetting = 0x07F13652;
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}
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else
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{
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uiClockSetting = 0x07F1365B;
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}
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}
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break;
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default:
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return -EINVAL;
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}
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break;
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}
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default:
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return -EINVAL;
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}
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value = 0;
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TRACE("Debug: Register count is %lu\n", RegCount);
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while(RegCount && !retval)
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{
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TRACE("Debug: Register count is %lu\n", registerCount);
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while (registerCount && !retval) {
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if (uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
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{
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value = uiClockSetting;
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}
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else
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{
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value = psDDRSetting->ulRegValue;
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}
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retval = BizarroWriteRegister(psDDRSetting->ulRegAddress,
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sizeof(value), (unsigned int*)&value);
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if (B_OK != retval) {
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TRACE_ALWAYS(
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"%s:%d BizarroWriteRegister failed at 0x%x on Register #%d.\n",
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__FUNCTION__, __LINE__, psDDRSetting->ulRegAddress, RegCount);
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__FUNCTION__, __LINE__, psDDRSetting->ulRegAddress,
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registerCount);
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break;
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}
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RegCount--;
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registerCount--;
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psDDRSetting++;
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}
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if(ChipID >= 0xbece3300 )
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{
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if (chipID >= 0xbece3300) {
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snooze(3);
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if( (ChipID != BCS220_2)&&
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(ChipID != BCS220_2BC)&&
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(ChipID != BCS220_3))
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{
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if ((chipID != BCS220_2)
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&& (chipID != BCS220_2BC)
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&& (chipID != BCS220_3)) {
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/* drive MDDR to half in case of UMA-B: */
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uiResetValue = 0x01010001;
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retval = BizarroWriteRegister((unsigned int)0x0F007018,
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@ -310,8 +283,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
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* UMA-B chip id. we will change this when we will have an
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* internal PMU.
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*/
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if(PmuMode == HYBRID_MODE_7C)
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{
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if (vendorPmuMode == HYBRID_MODE_7C) {
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TRACE("Debug: Hybrid Power Mode 7C\n");
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retval = BizarroReadRegister((unsigned int)0x0f000c00,
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sizeof(uiResetValue), &uiResetValue);
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@ -358,9 +330,8 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
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__FUNCTION__, __LINE__);
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return retval;
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}
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}
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else if(PmuMode == HYBRID_MODE_6 )
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{
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} else if (vendorPmuMode == HYBRID_MODE_6) {
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TRACE("Debug: Hybrid Power Mode 6\n");
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retval = BizarroReadRegister((unsigned int)0x0f000c00,
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sizeof(uiResetValue), &uiResetValue);
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@ -7,14 +7,14 @@
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*
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* Description: Wrangle Beceem volatile DDR memory.
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*/
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#ifndef _USB_BECEEM_DDR_H_
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#define _USB_BECEEM_DDR_H_
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#include <ByteOrder.h>
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#include <ByteOrder.h>
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#include "DeviceStruct.h"
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#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
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#define MIPS_CLOCK_REG 0x0f000820
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@ -32,20 +32,25 @@
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#define DDR_180_MHZ 6 // Not Used (Reserved for future)
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#define DDR_200_MHZ 7 // Not Used (Reserved for future)
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class BeceemDDR
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{
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class BeceemDDR {
|
||||
public:
|
||||
WIMAX_DEVICE* pwmxdevice;
|
||||
|
||||
BeceemDDR();
|
||||
status_t DDRInit(WIMAX_DEVICE* swmxdevice);
|
||||
|
||||
WIMAX_DEVICE* fWmxDevice;
|
||||
|
||||
// yuck. These are in a child class class
|
||||
virtual status_t ReadRegister(unsigned int reg, size_t size, uint32_t* buffer){ return NULL; };
|
||||
virtual status_t WriteRegister(unsigned int reg, size_t size, uint32_t* buffer){ return NULL; };
|
||||
virtual status_t BizarroReadRegister(unsigned int reg, size_t size, uint32_t* buffer){ return NULL; };
|
||||
virtual status_t BizarroWriteRegister(unsigned int reg, size_t size, uint32_t* buffer){ return NULL; };
|
||||
virtual status_t ReadRegister(unsigned int reg, size_t size,
|
||||
uint32_t* buffer) { return NULL; };
|
||||
virtual status_t WriteRegister(unsigned int reg, size_t size,
|
||||
uint32_t* buffer) { return NULL; };
|
||||
virtual status_t BizarroReadRegister(unsigned int reg,
|
||||
size_t size, uint32_t* buffer)
|
||||
{ return NULL; };
|
||||
virtual status_t BizarroWriteRegister(unsigned int reg,
|
||||
size_t size, uint32_t* buffer)
|
||||
{ return NULL; };
|
||||
|
||||
};
|
||||
|
||||
@ -60,26 +65,29 @@ typedef enum ePMU_MODES
|
||||
HYBRID_MODE_6 = 2
|
||||
}PMU_MODE;
|
||||
|
||||
|
||||
/*
|
||||
* DDR Init maps, taken from Beceem GPL Linux Driver
|
||||
*/
|
||||
|
||||
typedef struct _DDR_SETTING
|
||||
{
|
||||
unsigned long ulRegAddress;
|
||||
unsigned long ulRegValue;
|
||||
} DDR_SETTING, *PDDR_SETTING;
|
||||
|
||||
|
||||
typedef DDR_SETTING DDR_SET_NODE, *PDDR_SET_NODE;
|
||||
|
||||
//DDR INIT-133Mhz
|
||||
|
||||
// DDR INIT 133Mhz
|
||||
#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// # DPLL Clock Setting
|
||||
static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// DPLL Clock Setting
|
||||
{0x0F000800, 0x00007212},
|
||||
{0x0f000820, 0x07F13FFF},
|
||||
{0x0f000810, 0x00000F95},
|
||||
{0x0f000860, 0x00000000},
|
||||
{0x0f000880, 0x000003DD},
|
||||
// Changed source for X-bar and MIPS clock to APLL
|
||||
// Changed source for Xbar and MIPS clock to APLL
|
||||
{0x0f000840, 0x0FFF1B00},
|
||||
{0x0f000870, 0x00000002},
|
||||
{0x0F00a044, 0x1fffffff},
|
||||
@ -99,13 +107,13 @@ static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
|
||||
{0x0F007024, 0x02000007},
|
||||
{0x0F007028, 0x02020202},
|
||||
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
|
||||
{0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
|
||||
{0x0F007030, 0x05000000},
|
||||
{0x0F007034, 0x00000003},
|
||||
{0x0F007038,0x110a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
|
||||
{0x0F00703C,0x02101010},//ROB - 0x02101010,//0x02101018},
|
||||
{0x0F007040,0x45751200},//ROB - 0x45751200,//0x450f1200},
|
||||
{0x0F007044,0x110a0d00},//ROB - 0x110a0d00//0x111f0d00
|
||||
{0x0F007038, 0x110a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
|
||||
{0x0F00703C, 0x02101010}, // ROB - 0x02101010, 0x02101018},
|
||||
{0x0F007040, 0x45751200}, // ROB - 0x45751200, 0x450f1200},
|
||||
{0x0F007044, 0x110a0d00}, // ROB - 0x110a0d00, 0x111f0d00
|
||||
{0x0F007048, 0x081b0306},
|
||||
{0x0F00704c, 0x00000000},
|
||||
{0x0F007050, 0x0000001c},
|
||||
@ -124,14 +132,16 @@ static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007084, 0x00000000},
|
||||
// # Enable BW improvement within memory controller
|
||||
{0x0F007094, 0x00000104},
|
||||
//# Enable 2 ports within X-bar
|
||||
// # Enable 2 ports within Xbar
|
||||
{0x0F00A000, 0x00000016},
|
||||
// # Enable start bit within memory controller
|
||||
{0x0F007018, 0x01010000}
|
||||
};
|
||||
|
||||
|
||||
// 80Mhz
|
||||
#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// # DPLL Clock Setting
|
||||
static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// DPLL Clock Setting
|
||||
{0x0f000810, 0x00000F95},
|
||||
{0x0f000820, 0x07f1ffff},
|
||||
{0x0f000860, 0x00000000},
|
||||
@ -178,18 +188,20 @@ static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007080, 0x00000000},
|
||||
{0x0F007084, 0x00000000},
|
||||
{0x0F007094, 0x00000104},
|
||||
//# Enable start bit within memory controller
|
||||
// Enable start bit within memory controller
|
||||
{0x0F007018, 0x01010000}
|
||||
};
|
||||
|
||||
|
||||
// 100Mhz
|
||||
#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// DPLL Clock Setting
|
||||
{0x0F000800, 0x00007008},
|
||||
{0x0f000810, 0x00000F95},
|
||||
{0x0f000820, 0x07F13E3F},
|
||||
{0x0f000860, 0x00000000},
|
||||
{0x0f000880, 0x000003DD},
|
||||
// Changed source for X-bar and MIPS clock to APLL
|
||||
// Changed source for Xbar and MIPS clock to APLL
|
||||
// 0x0f000840, 0x0FFF1800,
|
||||
{0x0f000840, 0x0FFF1B00},
|
||||
{0x0f000870, 0x00000002},
|
||||
@ -198,7 +210,7 @@ static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F00a084, 0x1Cffffff},
|
||||
{0x0F00a080, 0x1C000000},
|
||||
{0x0F00a04C, 0x0000000C},
|
||||
//# Enable 2 ports within X-bar
|
||||
// Enable 2 ports within Xbar
|
||||
{0x0F00A000, 0x00000016},
|
||||
// Memcontroller Default values
|
||||
{0x0F007000, 0x00010001},
|
||||
@ -235,14 +247,15 @@ static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F00707C, 0x00000000},
|
||||
{0x0F007080, 0x00000000},
|
||||
{0x0F007084, 0x00000000},
|
||||
//# Enable BW improvement within memory controller
|
||||
// Enable BW improvement within memory controller
|
||||
{0x0F007094, 0x00000104},
|
||||
//# Enable start bit within memory controller
|
||||
// Enable start bit within memory controller
|
||||
{0x0F007018, 0x01010000}
|
||||
};
|
||||
|
||||
|
||||
// Net T3B DDR Settings
|
||||
//DDR INIT-133Mhz
|
||||
// DDR INIT 133Mhz
|
||||
static DDR_SET_NODE asDPLL_266MHZ[] = {
|
||||
{0x0F000800, 0x00007212},
|
||||
{0x0f000820, 0x07F13FFF},
|
||||
@ -253,6 +266,8 @@ static DDR_SET_NODE asDPLL_266MHZ[] = {
|
||||
{0x0f000840, 0x0FFF1B00},
|
||||
{0x0f000870, 0x00000002}
|
||||
};
|
||||
|
||||
|
||||
#if 0
|
||||
static DDR_SET_NODE asDPLL_800MHZ[] = {
|
||||
{0x0f000810, 0x00000F95},
|
||||
@ -265,22 +280,23 @@ static DDR_SET_NODE asDPLL_800MHZ[] = {
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting
|
||||
static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// DPLL Clock Setting
|
||||
{0x0f000810, 0x00000F95},
|
||||
{0x0f000810, 0x00000F95},
|
||||
{0x0f000810, 0x00000F95},
|
||||
{0x0f000820, 0x07F13652},
|
||||
{0x0f000840, 0x0FFF0800},
|
||||
// Changed source for X-bar and MIPS clock to APLL
|
||||
// Changed source for Xbar and MIPS clock to APLL
|
||||
{0x0f000880, 0x000003DD},
|
||||
{0x0f000860, 0x00000000},
|
||||
// Changed source for X-bar and MIPS clock to APLL
|
||||
// Changed source for Xbar and MIPS clock to APLL
|
||||
{0x0F00a044, 0x1fffffff},
|
||||
{0x0F00a040, 0x1f000000},
|
||||
{0x0F00a084, 0x1Cffffff},
|
||||
{0x0F00a080, 0x1C000000},
|
||||
//# Enable 2 ports within X-bar
|
||||
// Enable 2 ports within Xbar
|
||||
{0x0F00A000, 0x00000016},
|
||||
// Memcontroller Default values
|
||||
{0x0F007000, 0x00010001},
|
||||
@ -294,13 +310,13 @@ static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting
|
||||
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
|
||||
{0x0F007024, 0x02000007},
|
||||
{0x0F007028, 0x02020202},
|
||||
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
|
||||
{0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
|
||||
{0x0F007030, 0x05000000},
|
||||
{0x0F007034, 0x00000003},
|
||||
{0x0F007038,0x130a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
|
||||
{0x0F00703C,0x02101012},//ROB - 0x02101010,//0x02101018},
|
||||
{0x0F007040,0x457D1200},//ROB - 0x45751200,//0x450f1200},
|
||||
{0x0F007044,0x11130d00},//ROB - 0x110a0d00//0x111f0d00
|
||||
{0x0F007038, 0x130a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
|
||||
{0x0F00703C, 0x02101012}, // ROB - 0x02101010, 0x02101018},
|
||||
{0x0F007040, 0x457D1200}, // ROB - 0x45751200, 0x450f1200},
|
||||
{0x0F007044, 0x11130d00}, // ROB - 0x110a0d00, 0x111f0d00
|
||||
{0x0F007048, 0x040D0306},
|
||||
{0x0F00704c, 0x00000000},
|
||||
{0x0F007050, 0x0000001c},
|
||||
@ -323,8 +339,9 @@ static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting
|
||||
{0x0F007018, 0x01010000},
|
||||
};
|
||||
|
||||
|
||||
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// # DPLL Clock Setting
|
||||
static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// DPLL Clock Setting
|
||||
{0x0f000810, 0x00000F95},
|
||||
{0x0f000820, 0x07F13FFF},
|
||||
{0x0f000840, 0x0FFF1F00},
|
||||
@ -372,13 +389,14 @@ static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// # DPLL Clock Setting
|
||||
{0x0F007080, 0x00000000},
|
||||
{0x0F007084, 0x00000000},
|
||||
{0x0F007094, 0x00000104},
|
||||
//# Enable start bit within memory controller
|
||||
// Enable start bit within memory controller
|
||||
{0x0F007018, 0x01010000}
|
||||
};
|
||||
|
||||
|
||||
// 100Mhz
|
||||
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting
|
||||
static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// DPLL Clock Setting
|
||||
{0x0f000810, 0x00000F95},
|
||||
{0x0f000820, 0x07F1369B},
|
||||
{0x0f000840, 0x0FFF0800},
|
||||
@ -388,7 +406,7 @@ static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting
|
||||
{0x0F00a040, 0x1f000000},
|
||||
{0x0F00a084, 0x1Cffffff},
|
||||
{0x0F00a080, 0x1C000000},
|
||||
//# Enable 2 ports within X-bar
|
||||
// Enable 2 ports within Xbar
|
||||
{0x0F00A000, 0x00000016},
|
||||
// Memcontroller Default values
|
||||
{0x0F007000, 0x00010001},
|
||||
@ -433,11 +451,11 @@ static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting
|
||||
|
||||
|
||||
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3LP_DDRSetting133MHz[]= {// # DPLL Clock Setting
|
||||
static DDR_SET_NODE asT3LP_DDRSetting133MHz[] = {// DPLL Clock Setting
|
||||
{0x0f000820, 0x03F1365B},
|
||||
{0x0f000810, 0x00002F95},
|
||||
{0x0f000880, 0x000003DD},
|
||||
// Changed source for X-bar and MIPS clock to APLL
|
||||
// Changed source for Xbar and MIPS clock to APLL
|
||||
{0x0f000840, 0x0FFF0000},
|
||||
{0x0f000860, 0x00000000},
|
||||
{0x0F00a044, 0x1fffffff},
|
||||
@ -457,13 +475,13 @@ static DDR_SET_NODE asT3LP_DDRSetting133MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
|
||||
{0x0F007024, 0x02000007},
|
||||
{0x0F007028, 0x02020200},
|
||||
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
|
||||
{0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
|
||||
{0x0F007030, 0x05000000},
|
||||
{0x0F007034, 0x00000003},
|
||||
{0x0F007038,0x200a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
|
||||
{0x0F00703C,0x02101020},//ROB - 0x02101010,//0x02101018,
|
||||
{0x0F007040,0x45711200},//ROB - 0x45751200,//0x450f1200,
|
||||
{0x0F007044,0x110D0D00},//ROB - 0x110a0d00//0x111f0d00
|
||||
{0x0F007038, 0x200a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
|
||||
{0x0F00703C, 0x02101020}, // ROB - 0x02101010, 0x02101018,
|
||||
{0x0F007040, 0x45711200}, // ROB - 0x45751200, 0x450f1200,
|
||||
{0x0F007044, 0x110D0D00}, // ROB - 0x110a0d00, 0x111f0d00
|
||||
{0x0F007048, 0x04080306},
|
||||
{0x0F00704c, 0x00000000},
|
||||
{0x0F007050, 0x0100001c},
|
||||
@ -483,15 +501,16 @@ static DDR_SET_NODE asT3LP_DDRSetting133MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007088, 0x01000001},
|
||||
{0x0F00708c, 0x00000101},
|
||||
{0x0F007090, 0x00000000},
|
||||
//# Enable BW improvement within memory controller
|
||||
// Enable BW improvement within memory controller
|
||||
{0x0F007094, 0x00040000},
|
||||
{0x0F007098, 0x00000000},
|
||||
{0x0F0070c8, 0x00000104},
|
||||
//# Enable 2 ports within X-bar
|
||||
//# Enable start bit within memory controller
|
||||
// Enable 2 ports within Xbar
|
||||
// Enable start bit within memory controller
|
||||
{0x0F007018, 0x01010000}
|
||||
};
|
||||
|
||||
|
||||
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0f000810, 0x00002F95},
|
||||
@ -499,7 +518,7 @@ static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0f000840, 0x0fff0000},
|
||||
{0x0f000860, 0x00000000},
|
||||
{0x0f000880, 0x000003DD},
|
||||
// Changed source for X-bar and MIPS clock to APLL
|
||||
// Changed source for Xbar and MIPS clock to APLL
|
||||
{0x0f000840, 0x0FFF0000},
|
||||
{0x0F00a044, 0x1fffffff},
|
||||
{0x0F00a040, 0x1f000000},
|
||||
@ -517,13 +536,13 @@ static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
|
||||
{0x0F007024, 0x00000007},
|
||||
{0x0F007028, 0x01020200},
|
||||
{0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
|
||||
{0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
|
||||
{0x0F007030, 0x06000000},
|
||||
{0x0F007034, 0x00000004},
|
||||
{0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
|
||||
{0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
|
||||
{0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
|
||||
{0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
|
||||
{0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
|
||||
{0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
|
||||
{0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
|
||||
{0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
|
||||
{0x0F007048, 0x03000305},
|
||||
{0x0F00704c, 0x00000000},
|
||||
{0x0F007050, 0x0100001c},
|
||||
@ -546,12 +565,13 @@ static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007094, 0x00010000},
|
||||
{0x0F007098, 0x00000000},
|
||||
{0x0F0070C8, 0x00000104},
|
||||
//# Enable 2 ports within X-bar
|
||||
// Enable 2 ports within Xbar
|
||||
{0x0F00A000, 0x00000016},
|
||||
//# Enable start bit within memory controller
|
||||
// Enable start bit within memory controller
|
||||
{0x0F007018, 0x01010000}
|
||||
};
|
||||
|
||||
|
||||
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
|
||||
{0x0f000820, 0x07F13FFF},
|
||||
@ -608,13 +628,9 @@ static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
///T3 LP-B (UMA-B)
|
||||
|
||||
// T3 LP-B (UMA-B)
|
||||
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
|
||||
|
||||
{0x0f000820, 0x03F137DB},
|
||||
{0x0f000810, 0x01842795},
|
||||
{0x0f000860, 0x00000000},
|
||||
@ -622,7 +638,7 @@ static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
|
||||
{0x0f000840, 0x0FFF0400},
|
||||
{0x0F00a044, 0x1fffffff},
|
||||
{0x0F00a040, 0x1f000000},
|
||||
{0x0f003050,0x00000021},//this is flash/eeprom clock divisor which set the flash clock to 20 MHz
|
||||
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
|
||||
{0x0F00a084, 0x1Cffffff}, // Now dump from her in internal memory
|
||||
{0x0F00a080, 0x1C000000},
|
||||
{0x0F00A000, 0x00000016},
|
||||
@ -675,12 +691,12 @@ static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
|
||||
{0x0f000820, 0x03F1365B},
|
||||
{0x0f000810, 0x00002F95},
|
||||
{0x0f000880, 0x000003DD},
|
||||
// Changed source for X-bar and MIPS clock to APLL
|
||||
// Changed source for Xbar and MIPS clock to APLL
|
||||
{0x0f000840, 0x0FFF0000},
|
||||
{0x0f000860, 0x00000000},
|
||||
{0x0F00a044, 0x1fffffff},
|
||||
{0x0F00a040, 0x1f000000},
|
||||
{0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
|
||||
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
|
||||
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
|
||||
{0x0F00a080, 0x1C000000},
|
||||
{0x0F00A000, 0x00000016},
|
||||
@ -696,13 +712,13 @@ static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
|
||||
{0x0F007024, 0x02000007},
|
||||
{0x0F007028, 0x02020200},
|
||||
{0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
|
||||
{0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
|
||||
{0x0F007030, 0x05000000},
|
||||
{0x0F007034, 0x00000003},
|
||||
{0x0F007038,0x190a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
|
||||
{0x0F00703C,0x02101017},//ROB - 0x02101010,//0x02101018,
|
||||
{0x0F007040,0x45171200},//ROB - 0x45751200,//0x450f1200,
|
||||
{0x0F007044,0x11290D00},//ROB - 0x110a0d00//0x111f0d00
|
||||
{0x0F007038, 0x190a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
|
||||
{0x0F00703C, 0x02101017}, // ROB - 0x02101010, 0x02101018,
|
||||
{0x0F007040, 0x45171200}, // ROB - 0x45751200, 0x450f1200,
|
||||
{0x0F007044, 0x11290D00}, // ROB - 0x110a0d00, 0x111f0d00
|
||||
{0x0F007048, 0x04080306},
|
||||
{0x0F00704c, 0x00000000},
|
||||
{0x0F007050, 0x0100001c},
|
||||
@ -722,15 +738,16 @@ static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007088, 0x01000001},
|
||||
{0x0F00708c, 0x00000101},
|
||||
{0x0F007090, 0x00000000},
|
||||
//# Enable BW improvement within memory controller
|
||||
// Enable BW improvement within memory controller
|
||||
{0x0F007094, 0x00040000},
|
||||
{0x0F007098, 0x00000000},
|
||||
{0x0F0070c8, 0x00000104},
|
||||
//# Enable 2 ports within X-bar
|
||||
//# Enable start bit within memory controller
|
||||
// Enable 2 ports within Xbar
|
||||
// Enable start bit within memory controller
|
||||
{0x0F007018, 0x01010000}
|
||||
};
|
||||
|
||||
|
||||
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0f000810, 0x00002F95},
|
||||
@ -738,11 +755,11 @@ static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0f000840, 0x0fff0000},
|
||||
{0x0f000860, 0x00000000},
|
||||
{0x0f000880, 0x000003DD},
|
||||
// Changed source for X-bar and MIPS clock to APLL
|
||||
// Changed source for Xbar and MIPS clock to APLL
|
||||
{0x0f000840, 0x0FFF0000},
|
||||
{0x0F00a044, 0x1fffffff},
|
||||
{0x0F00a040, 0x1f000000},
|
||||
{0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
|
||||
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
|
||||
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
|
||||
{0x0F00a080, 0x1C000000},
|
||||
// Memcontroller Default values
|
||||
@ -757,13 +774,13 @@ static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
|
||||
{0x0F007024, 0x00000007},
|
||||
{0x0F007028, 0x01020200},
|
||||
{0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
|
||||
{0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
|
||||
{0x0F007030, 0x06000000},
|
||||
{0x0F007034, 0x00000004},
|
||||
{0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
|
||||
{0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
|
||||
{0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
|
||||
{0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
|
||||
{0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
|
||||
{0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
|
||||
{0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
|
||||
{0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
|
||||
{0x0F007048, 0x03000305},
|
||||
{0x0F00704c, 0x00000000},
|
||||
{0x0F007050, 0x0100001c},
|
||||
@ -786,14 +803,15 @@ static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007094, 0x00010000},
|
||||
{0x0F007098, 0x00000000},
|
||||
{0x0F0070C8, 0x00000104},
|
||||
//# Enable 2 ports within X-bar
|
||||
// # Enable 2 ports within Xbar
|
||||
{0x0F00A000, 0x00000016},
|
||||
// # Enable start bit within memory controller
|
||||
{0x0F007018, 0x01010000}
|
||||
};
|
||||
|
||||
|
||||
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 // index for 0x0F007000
|
||||
static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// # DPLL Clock Setting
|
||||
static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// DPLL Clock Setting
|
||||
{0x0f000820, 0x07F13FFF},
|
||||
{0x0f000810, 0x00002F95},
|
||||
{0x0f000860, 0x00000000},
|
||||
@ -801,7 +819,7 @@ static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// # DPLL Clock Setting
|
||||
{0x0f000840, 0x0FFF1F00},
|
||||
{0x0F00a044, 0x1fffffff},
|
||||
{0x0F00a040, 0x1f000000},
|
||||
{0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
|
||||
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
|
||||
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
|
||||
{0x0F00a080, 0x1C000000},
|
||||
{0x0F00A000, 0x00000016},
|
||||
@ -848,5 +866,6 @@ static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// # DPLL Clock Setting
|
||||
{0x0F007018, 0x01010000}
|
||||
};
|
||||
|
||||
|
||||
#endif // _USB_BECEEM_DDR_H_
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user