Aren/haiku
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix a few missed style corrections in BeceemCPU; style cleanup in BeceemDDR; no functional change

Browse Source 
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@40850 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV 2011-03-06 18:26:19 +00:00
parent 1687edd0fd
commit 4b7b79d52f
4 changed files with 1008 additions and 1028 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.cpp
View File

@ -43,11 +43,10 @@ BeceemCPU::CPURun()
}
// Adjust clock register contents to start cpu
if (fWmxDevice->CPUFlashBoot) {
clockRegister &= (~(1<<30));
} else {
clockRegister |= (1<<30);
}
if (fWmxDevice->CPUFlashBoot)
clockRegister &= ~(1 << 30);
else
clockRegister |= (1 << 30);
// Write new clock register contents
if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
@ -66,14 +65,13 @@ BeceemCPU::CPUReset()
unsigned int value = 0;
unsigned int uiResetValue = 0;
if (fWmxDevice->deviceChipID >= T3LPB)
{
if (fWmxDevice->deviceChipID >= T3LPB) {
BizarroReadRegister(SYS_CFG, sizeof(value), &value);
BizarroReadRegister(SYS_CFG, sizeof(value), &value);
// SYS_CFG register is write protected hence for modifying
// this reg value, it should be read twice before writing.
value = value | (fWmxDevice->syscfgBefFw & 0x00000060) ;
value = value | (fWmxDevice->syscfgBefFw & 0x00000060);
// making bit[6...5] same as was before f/w download. this
// setting forces the h/w to re-populated the SP RAM area
// with the string descriptor .
@ -85,23 +83,20 @@ BeceemCPU::CPUReset()
}
/* Reset the UMA-B Device */
if (fWmxDevice->deviceChipID >= T3LPB)
{
if (fWmxDevice->deviceChipID >= T3LPB) {
// Reset UMA-B
// TODO : USB reset needs implimented
/*
if (usb_reset_device(psIntfAdapter->udev) != B_OK)
{
if (usb_reset_device(psIntfAdapter->udev) != B_OK) {
TRACE_ALWAYS("Error: USB Reset failed\n");
retrun B_ERROR;
}
*/
if (fWmxDevice->deviceChipID == BCS220_2 ||
fWmxDevice->deviceChipID == BCS220_2BC ||
fWmxDevice->deviceChipID == BCS250_BC ||
fWmxDevice->deviceChipID == BCS220_3)
{
if (fWmxDevice->deviceChipID == BCS220_2
|| fWmxDevice->deviceChipID == BCS220_2BC
|| fWmxDevice->deviceChipID == BCS250_BC
|| fWmxDevice->deviceChipID == BCS220_3) {
if (BizarroReadRegister(HPM_CONFIG_LDO145,
sizeof(value), &value) != B_OK) {
TRACE_ALWAYS("Error: USB read failed during reset\n");
@ -120,8 +115,7 @@ BeceemCPU::CPUReset()
}
// TODO : ELSE OLDER CHIP ID's < T3LP see Misc.c:1048
if (fWmxDevice->CPUFlashBoot)
{
if (fWmxDevice->CPUFlashBoot) {
// In flash boot mode MIPS state register has reverse polarity.
// So just or with setting bit 30.
// Make the MIPS in Reset state.
@ -131,7 +125,7 @@ BeceemCPU::CPUReset()
return B_ERROR;
}
// set 30th bit
uiResetValue |=(1<<30);
uiResetValue |= (1 << 30);
if (BizarroWriteRegister(CLOCK_RESET_CNTRL_REG_1,
sizeof(uiResetValue), &uiResetValue) != B_OK) {
@ -140,17 +134,15 @@ BeceemCPU::CPUReset()
}
}
if (fWmxDevice->deviceChipID >= T3LPB)
{
if (fWmxDevice->deviceChipID >= T3LPB) {
uiResetValue = 0;
// WA for SYSConfig Issue.
BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue);
if (uiResetValue & (1<<4))
{
if (uiResetValue & (1 << 4)) {
uiResetValue = 0;
BizarroReadRegister(SYS_CFG, sizeof(uiResetValue), &uiResetValue);
// Read SYSCFG Twice to make it writable.
uiResetValue &= (~(1<<4));
uiResetValue &= ~(1 << 4);
if (BizarroWriteRegister(SYS_CFG,
sizeof(uiResetValue), &uiResetValue) != B_OK) {

4
src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemCPU.h
View File

@ -16,9 +16,7 @@
#define CLOCK_RESET_CNTRL_REG_1 0x0F00000C
class BeceemCPU
{
class BeceemCPU {
public:
BeceemCPU();
status_t CPUInit(WIMAX_DEVICE* swmxdevice);

403
src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.cpp
View File

@ -2,100 +2,90 @@
* Beceem WiMax USB Driver.
* Copyright (c) 2010 Alexander von Gluck <kallisti5@unixzen.com>
* Distributed under the terms of the GNU General Public License.
*
*
* Based on GPL code developed by: Beceem Communications Pvt. Ltd
*
*
* Description: Wrangle Beceem volatile DDR memory.
*/
#include "Settings.h"
#include "BeceemDDR.h"
#include "Settings.h"
BeceemDDR::BeceemDDR()
{
TRACE("Debug: Load DDR handler\n");
TRACE("Debug: Load DDR handler\n");
}
status_t
BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
{
pwmxdevice = swmxdevice;
PDDR_SETTING psDDRSetting=NULL;
fWmxDevice = swmxdevice;
PDDR_SETTING psDDRSetting = NULL;
unsigned int HostDrvrConfig6 = pwmxdevice->vendorcfg.HostDrvrConfig6;
unsigned int uiHostDrvrCfg6 = 0;
unsigned int ChipID = pwmxdevice->deviceChipID;
unsigned int chipID = fWmxDevice->deviceChipID;
unsigned long RegCount=0;
unsigned long registerCount = 0;
unsigned long value = 0;
unsigned int uiResetValue = 0;
unsigned int uiClockSetting = 0;
int retval = B_OK;
unsigned int DDRSetting = 0;
bool PmuMode = 0;
bool MipsConfig = 0;
bool PLLConfig = 0;
// Grab the Config6 metric from the vendor config and convert endianness
unsigned int vendorConfig6raw = fWmxDevice->vendorcfg.HostDrvrConfig6;
vendorConfig6raw &= ~(htonl(1 << 15));
unsigned int vendorConfig6 = ntohl(vendorConfig6raw);
HostDrvrConfig6 &= ~(htonl(1 << 15));
uiHostDrvrCfg6 = ntohl(HostDrvrConfig6);
// Read our vendor provided Config6 metric and populate memory settings
unsigned int vendorDDRSetting = (ntohl(vendorConfig6raw) >> 8) & 0x0F;
bool vendorPmuMode = (vendorConfig6 >> 24) & 0x03;
bool vendorMipsConfig = (vendorConfig6 >> 20) & 0x01;
bool vendorPLLConfig = (vendorConfig6 >> 19) & 0x01;
DDRSetting = (ntohl(HostDrvrConfig6) >>8)&0x0F ;
PmuMode = (uiHostDrvrCfg6>>24)&0x03;
MipsConfig = (uiHostDrvrCfg6>>20)&0x01;
PLLConfig = (uiHostDrvrCfg6>>19)&0x01;
switch (chipID) {
case 0xbece3200:
switch (vendorDDRSetting) {
case DDR_80_MHZ:
psDDRSetting = asT3LP_DDRSetting80MHz;
registerCount = sizeof(asT3LP_DDRSetting80MHz)
/ sizeof(DDR_SETTING);
break;
case DDR_100_MHZ:
psDDRSetting = asT3LP_DDRSetting100MHz;
registerCount = sizeof(asT3LP_DDRSetting100MHz)
/ sizeof(DDR_SETTING);
break;
case DDR_133_MHZ:
psDDRSetting = asT3LP_DDRSetting133MHz;
registerCount = sizeof(asT3LP_DDRSetting133MHz)
/ sizeof(DDR_SETTING);
switch (ChipID)
{
case 0xbece3200:
switch (DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting=asT3LP_DDRSetting80MHz;
RegCount=(sizeof(asT3LP_DDRSetting80MHz)/
sizeof(DDR_SETTING));
break;
case DDR_100_MHZ:
psDDRSetting=asT3LP_DDRSetting100MHz;
RegCount=(sizeof(asT3LP_DDRSetting100MHz)/
sizeof(DDR_SETTING));
break;
case DDR_133_MHZ:
psDDRSetting=asT3LP_DDRSetting133MHz;
RegCount=(sizeof(asT3LP_DDRSetting133MHz)/
sizeof(DDR_SETTING));
if(MipsConfig == MIPS_200_MHZ)
{
uiClockSetting = 0x03F13652;
}
else
{
uiClockSetting = 0x03F1365B;
}
break;
default:
return -EINVAL;
}
if (vendorMipsConfig == MIPS_200_MHZ)
uiClockSetting = 0x03F13652;
else
uiClockSetting = 0x03F1365B;
break;
default:
return -EINVAL;
}
break;
break;
case T3LPB:
case BCS220_2:
case BCS220_2BC:
case BCS250_BC:
case BCS220_3 :
// We need to check current value and additionally set bit 2 and
// bit 6 to 1 for BBIC 2mA drive
if( (ChipID != BCS220_2) &&
(ChipID != BCS220_2BC) &&
(ChipID != BCS220_3) )
{
retval= BizarroReadRegister((unsigned int)0x0f000830,
case T3LPB:
case BCS220_2:
case BCS220_2BC:
case BCS250_BC:
case BCS220_3 :
// We need to check current value and additionally set bit 2 and
// bit 6 to 1 for BBIC 2mA drive
if ((chipID != BCS220_2)
&& (chipID != BCS220_2BC)
&& (chipID != BCS220_3)) {
retval = BizarroReadRegister((unsigned int)0x0f000830,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
@ -103,172 +93,155 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
uiResetValue |= 0x44;
retval = BizarroWriteRegister((unsigned int)0x0f000830,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
}
switch(DDRSetting)
{
case DDR_80_MHZ:
TRACE("Debug: DDR 80MHz\n");
psDDRSetting = asT3LPB_DDRSetting80MHz;
RegCount=(sizeof(asT3B_DDRSetting80MHz)/
sizeof(DDR_SETTING));
break;
case DDR_100_MHZ:
TRACE("Debug: DDR 100MHz\n");
psDDRSetting=asT3LPB_DDRSetting100MHz;
RegCount=(sizeof(asT3B_DDRSetting100MHz)/
sizeof(DDR_SETTING));
break;
case DDR_133_MHZ:
TRACE("Debug: DDR 133MHz\n");
psDDRSetting = asT3LPB_DDRSetting133MHz;
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
sizeof(DDR_SETTING));
}
if(MipsConfig == MIPS_200_MHZ)
{
uiClockSetting = 0x03F13652;
}
else
{
uiClockSetting = 0x03F1365B;
}
break;
switch(vendorDDRSetting) {
case DDR_80_MHZ:
TRACE("Debug: DDR 80MHz\n");
psDDRSetting = asT3LPB_DDRSetting80MHz;
registerCount = sizeof(asT3B_DDRSetting80MHz)
/ sizeof(DDR_SETTING);
break;
case DDR_100_MHZ:
TRACE("Debug: DDR 100MHz\n");
psDDRSetting = asT3LPB_DDRSetting100MHz;
registerCount = sizeof(asT3B_DDRSetting100MHz)
/ sizeof(DDR_SETTING);
break;
case DDR_133_MHZ:
TRACE("Debug: DDR 133MHz\n");
psDDRSetting = asT3LPB_DDRSetting133MHz;
registerCount = sizeof(asT3B_DDRSetting133MHz)
/ sizeof(DDR_SETTING);
case DDR_160_MHZ:
TRACE("Debug: DDR 160MHz\n");
psDDRSetting = asT3LPB_DDRSetting160MHz;
RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SETTING);
if (vendorMipsConfig == MIPS_200_MHZ)
uiClockSetting = 0x03F13652;
else
uiClockSetting = 0x03F1365B;
break;
if(MipsConfig == MIPS_200_MHZ)
{
TRACE("Debug: MIPS 200Mhz\n");
uiClockSetting = 0x03F137D2;
}
else
{
uiClockSetting = 0x03F137DB;
}
case DDR_160_MHZ:
TRACE("Debug: DDR 160MHz\n");
psDDRSetting = asT3LPB_DDRSetting160MHz;
registerCount = sizeof(asT3LPB_DDRSetting160MHz)
/ sizeof(DDR_SETTING);
if (vendorMipsConfig == MIPS_200_MHZ) {
TRACE("Debug: MIPS 200Mhz\n");
uiClockSetting = 0x03F137D2;
} else {
uiClockSetting = 0x03F137DB;
}
}
break;
case 0xbece0110:
case 0xbece0120:
case 0xbece0121:
case 0xbece0130:
case 0xbece0300:
switch (DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting = asT3_DDRSetting80MHz;
RegCount = (sizeof(asT3_DDRSetting80MHz)/
sizeof(DDR_SETTING));
break;
case DDR_100_MHZ:
psDDRSetting = asT3_DDRSetting100MHz;
RegCount = (sizeof(asT3_DDRSetting100MHz)/
sizeof(DDR_SETTING));
break;
case DDR_133_MHZ:
psDDRSetting = asT3_DDRSetting133MHz;
RegCount = (sizeof(asT3_DDRSetting133MHz)/
sizeof(DDR_SETTING));
break;
default:
return -EINVAL;
}
case 0xbece0310:
{
switch (DDRSetting)
{
case DDR_80_MHZ:
psDDRSetting = asT3B_DDRSetting80MHz;
RegCount=(sizeof(asT3B_DDRSetting80MHz)/
sizeof(DDR_SETTING));
break;
case DDR_100_MHZ:
psDDRSetting=asT3B_DDRSetting100MHz;
RegCount=(sizeof(asT3B_DDRSetting100MHz)/
sizeof(DDR_SETTING));
case 0xbece0110:
case 0xbece0120:
case 0xbece0121:
case 0xbece0130:
case 0xbece0300:
switch (vendorDDRSetting) {
case DDR_80_MHZ:
psDDRSetting = asT3_DDRSetting80MHz;
registerCount = sizeof(asT3_DDRSetting80MHz)
/ sizeof(DDR_SETTING);
break;
case DDR_100_MHZ:
psDDRSetting = asT3_DDRSetting100MHz;
registerCount = sizeof(asT3_DDRSetting100MHz)
/ sizeof(DDR_SETTING);
break;
case DDR_133_MHZ:
psDDRSetting = asT3_DDRSetting133MHz;
registerCount = sizeof(asT3_DDRSetting133MHz)
/ sizeof(DDR_SETTING);
break;
default:
return -EINVAL;
}
case 0xbece0310:
{
switch (vendorDDRSetting) {
case DDR_80_MHZ:
psDDRSetting = asT3B_DDRSetting80MHz;
registerCount = sizeof(asT3B_DDRSetting80MHz)
/ sizeof(DDR_SETTING);
break;
case DDR_100_MHZ:
psDDRSetting = asT3B_DDRSetting100MHz;
registerCount = sizeof(asT3B_DDRSetting100MHz)
/ sizeof(DDR_SETTING);
break;
case DDR_133_MHZ:
if (vendorPLLConfig == PLL_266_MHZ) {
// 266Mhz PLL selected.
memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
sizeof(asDPLL_266MHZ));
psDDRSetting = asT3B_DDRSetting133MHz;
registerCount = sizeof(asT3B_DDRSetting133MHz)
/ sizeof(DDR_SETTING);
} else {
psDDRSetting = asT3B_DDRSetting133MHz;
registerCount = sizeof(asT3B_DDRSetting133MHz)
/ sizeof(DDR_SETTING);
if (vendorMipsConfig == MIPS_200_MHZ)
uiClockSetting = 0x07F13652;
else
uiClockSetting = 0x07F1365B;
}
break;
default:
return -EINVAL;
}
break;
case DDR_133_MHZ:
if(PLLConfig == PLL_266_MHZ)//266Mhz PLL selected.
{
memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
sizeof(asDPLL_266MHZ));
psDDRSetting = asT3B_DDRSetting133MHz;
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
sizeof(DDR_SETTING));
}
else
{
psDDRSetting = asT3B_DDRSetting133MHz;
RegCount=(sizeof(asT3B_DDRSetting133MHz)/
sizeof(DDR_SETTING));
if(MipsConfig == MIPS_200_MHZ)
{
uiClockSetting = 0x07F13652;
}
else
{
uiClockSetting = 0x07F1365B;
}
}
break;
default:
return -EINVAL;
}
break;
}
default:
return -EINVAL;
default:
return -EINVAL;
}
value=0;
TRACE("Debug: Register count is %lu\n", RegCount);
while(RegCount && !retval)
{
if(uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
{
value = 0;
TRACE("Debug: Register count is %lu\n", registerCount);
while (registerCount && !retval) {
if (uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
value = uiClockSetting;
}
else
{
value = psDDRSetting->ulRegValue;
}
retval = BizarroWriteRegister(psDDRSetting->ulRegAddress,
sizeof(value), (unsigned int*)&value);
if(B_OK != retval) {
if (B_OK != retval) {
TRACE_ALWAYS(
"%s:%d BizarroWriteRegister failed at 0x%x on Register #%d.\n",
__FUNCTION__, __LINE__, psDDRSetting->ulRegAddress, RegCount);
__FUNCTION__, __LINE__, psDDRSetting->ulRegAddress,
registerCount);
break;
}
RegCount--;
registerCount--;
psDDRSetting++;
}
if(ChipID >= 0xbece3300 )
{
if (chipID >= 0xbece3300) {
snooze(3);
if( (ChipID != BCS220_2)&&
(ChipID != BCS220_2BC)&&
(ChipID != BCS220_3))
{
if ((chipID != BCS220_2)
&& (chipID != BCS220_2BC)
&& (chipID != BCS220_3)) {
/* drive MDDR to half in case of UMA-B: */
uiResetValue = 0x01010001;
retval = BizarroWriteRegister((unsigned int)0x0F007018,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
@ -277,7 +250,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
retval = BizarroWriteRegister((unsigned int)0x0F007094,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
@ -286,7 +259,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
retval = BizarroWriteRegister((unsigned int)0x0F00701c,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
@ -295,7 +268,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
retval = BizarroWriteRegister((unsigned int)0x0F007018,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
@ -310,20 +283,19 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
* UMA-B chip id. we will change this when we will have an
* internal PMU.
*/
if(PmuMode == HYBRID_MODE_7C)
{
if (vendorPmuMode == HYBRID_MODE_7C) {
TRACE("Debug: Hybrid Power Mode 7C\n");
retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
@ -331,21 +303,21 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
uiResetValue = 0x1322a8;
retval = BizarroWriteRegister((unsigned int)0x0f000d1c,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
@ -353,25 +325,24 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
uiResetValue = 0x132296;
retval = BizarroWriteRegister((unsigned int)0x0f000d14,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
}
else if(PmuMode == HYBRID_MODE_6 )
{
} else if (vendorPmuMode == HYBRID_MODE_6) {
TRACE("Debug: Hybrid Power Mode 6\n");
retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
@ -379,21 +350,21 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
uiResetValue = 0x6003229a;
retval = BizarroWriteRegister((unsigned int)0x0f000d14,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
@ -401,7 +372,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
uiResetValue = 0x1322a8;
retval = BizarroWriteRegister((unsigned int)0x0f000d1c,
sizeof(uiResetValue), &uiResetValue);
if(retval < 0) {
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;

1587
src/add-ons/kernel/drivers/network/wimax/usb_beceemwmx/BeceemDDR.h
View File

File diff suppressed because it is too large Load Diff