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fixed secondary head specs (nview)

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@7348 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-05-02 12:12:55 +00:00
parent 14787e6d3a
commit 49e02c1862
2 changed files with 91 additions and 46 deletions
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72
src/add-ons/accelerants/nvidia/GetModeInfo.c
View File

@ -4,7 +4,7 @@
Other authors:
Mark Watson
Rudolf Cornelissen 9-11/2002
Rudolf Cornelissen 9/2002-5/2003
*/
#define MODULE_BIT 0x02000000
@ -35,10 +35,9 @@ status_t GET_FRAME_BUFFER_CONFIG(frame_buffer_config *afb)
}
/* Return the maximum and minium pixelclock limits for the specified mode. */
/* Rewritten / fixed by Rudolf */
/* NOTE:
* Due to BeOS constraints output for all heads will be limited to the head with
* the least capabilities. (BeOS should ask for seperate constraints for all heads.) */
* the least capabilities. */
status_t GET_PIXEL_CLOCK_LIMITS(display_mode *dm, uint32 *low, uint32 *high)
{
uint32 max_pclk = 0;
@ -58,7 +57,8 @@ status_t GET_PIXEL_CLOCK_LIMITS(display_mode *dm, uint32 *low, uint32 *high)
*low = ((si->ps.min_video_vco * 1000) / 16);
break;
}
/* find max. value */
/* find max. value:
* using decondary DAC specs because they could be narrower (twinview) */
switch (dm->space)
{
case B_CMAP8:
@ -93,26 +93,52 @@ status_t GET_PIXEL_CLOCK_LIMITS(display_mode *dm, uint32 *low, uint32 *high)
*low = ((si->ps.min_pixel_vco * 1000) / 16);
break;
}
/* find max. value */
switch (dm->space)
/* find max. value: depends on which head is used as primary head */
if (!si->ps.crtc2_prim)
{
case B_CMAP8:
max_pclk = si->ps.max_dac1_clock_8;
break;
case B_RGB15_LITTLE:
case B_RGB16_LITTLE:
max_pclk = si->ps.max_dac1_clock_16;
break;
case B_RGB24_LITTLE:
max_pclk = si->ps.max_dac1_clock_24;
break;
case B_RGB32_LITTLE:
max_pclk = si->ps.max_dac1_clock_32;
break;
default:
/* use fail-safe value */
max_pclk = si->ps.max_dac1_clock_32;
break;
switch (dm->space)
{
case B_CMAP8:
max_pclk = si->ps.max_dac1_clock_8;
break;
case B_RGB15_LITTLE:
case B_RGB16_LITTLE:
max_pclk = si->ps.max_dac1_clock_16;
break;
case B_RGB24_LITTLE:
max_pclk = si->ps.max_dac1_clock_24;
break;
case B_RGB32_LITTLE:
max_pclk = si->ps.max_dac1_clock_32;
break;
default:
/* use fail-safe value */
max_pclk = si->ps.max_dac1_clock_32;
break;
}
}
else
{
switch (dm->space)
{
case B_CMAP8:
max_pclk = si->ps.max_dac2_clock_8;
break;
case B_RGB15_LITTLE:
case B_RGB16_LITTLE:
max_pclk = si->ps.max_dac2_clock_16;
break;
case B_RGB24_LITTLE:
max_pclk = si->ps.max_dac2_clock_24;
break;
case B_RGB32_LITTLE:
max_pclk = si->ps.max_dac2_clock_32;
break;
default:
/* use fail-safe value */
max_pclk = si->ps.max_dac2_clock_32;
break;
}
}
/* return values in kHz */
*high = max_pclk * 1000;

65
src/add-ons/accelerants/nvidia/engine/nv_info.c
View File

@ -1,7 +1,7 @@
/* Read initialisation information from card */
/* some bits are hacks, where PINS is not known */
/* Author:
Rudolf Cornelissen 7/2003-4/2004
Rudolf Cornelissen 7/2003-5/2004
*/
#define MODULE_BIT 0x00002000
@ -861,14 +861,31 @@ static void pinsnv10_arch_fake(void)
si->ps.max_dac1_clock_32 = 280;
si->ps.max_dac1_clock_32dh = 250;
/* secondary head */
//fixme? assuming...
si->ps.max_dac2_clock = 200;
si->ps.max_dac2_clock_8 = 200;
si->ps.max_dac2_clock_16 = 200;
si->ps.max_dac2_clock_24 = 200;
si->ps.max_dac2_clock_32 = 200;
/* 'failsave' values */
si->ps.max_dac2_clock_32dh = 180;
if (si->ps.card_type < NV17)
{
/* if a GeForce2 has analog VGA dualhead capability,
* it uses an external secondary DAC probably with limited capability. */
/* (called twinview technology) */
si->ps.max_dac2_clock = 200;
si->ps.max_dac2_clock_8 = 200;
si->ps.max_dac2_clock_16 = 200;
si->ps.max_dac2_clock_24 = 200;
si->ps.max_dac2_clock_32 = 200;
/* 'failsave' values */
si->ps.max_dac2_clock_32dh = 180;
}
else
{
/* GeForce4 cards have dual integrated DACs with identical capaability */
/* (called nview technology) */
si->ps.max_dac2_clock = 350;
si->ps.max_dac2_clock_8 = 350;
si->ps.max_dac2_clock_16 = 350;
/* 'failsave' values */
si->ps.max_dac2_clock_24 = 320;
si->ps.max_dac2_clock_32 = 280;
si->ps.max_dac2_clock_32dh = 250;
}
//fixme: primary & secondary_dvi should be overrule-able via nv.settings
si->ps.primary_dvi = false;
si->ps.secondary_dvi = false;
@ -894,14 +911,15 @@ static void pinsnv20_arch_fake(void)
si->ps.max_dac1_clock_32 = 280;
si->ps.max_dac1_clock_32dh = 250;
/* secondary head */
//fixme? assuming...
si->ps.max_dac2_clock = 200;
si->ps.max_dac2_clock_8 = 200;
si->ps.max_dac2_clock_16 = 200;
si->ps.max_dac2_clock_24 = 200;
si->ps.max_dac2_clock_32 = 200;
/* GeForce4 cards have dual integrated DACs with identical capaability */
/* (called nview technology) */
si->ps.max_dac2_clock = 350;
si->ps.max_dac2_clock_8 = 350;
si->ps.max_dac2_clock_16 = 350;
/* 'failsave' values */
si->ps.max_dac2_clock_32dh = 180;
si->ps.max_dac2_clock_24 = 320;
si->ps.max_dac2_clock_32 = 280;
si->ps.max_dac2_clock_32dh = 250;
//fixme: primary & secondary_dvi should be overrule-able via nv.settings
si->ps.primary_dvi = false;
si->ps.secondary_dvi = false;
@ -927,14 +945,15 @@ static void pinsnv30_arch_fake(void)
si->ps.max_dac1_clock_32 = 280;
si->ps.max_dac1_clock_32dh = 250;
/* secondary head */
//fixme? assuming...
si->ps.max_dac2_clock = 200;
si->ps.max_dac2_clock_8 = 200;
si->ps.max_dac2_clock_16 = 200;
si->ps.max_dac2_clock_24 = 200;
si->ps.max_dac2_clock_32 = 200;
/* GeForceFX cards have dual integrated DACs with identical capaability */
/* (called nview technology) */
si->ps.max_dac2_clock = 350;
si->ps.max_dac2_clock_8 = 350;
si->ps.max_dac2_clock_16 = 350;
/* 'failsave' values */
si->ps.max_dac2_clock_32dh = 180;
si->ps.max_dac2_clock_24 = 320;
si->ps.max_dac2_clock_32 = 280;
si->ps.max_dac2_clock_32dh = 250;
//fixme: primary & secondary_dvi should be overrule-able via nv.settings
si->ps.primary_dvi = false;
si->ps.secondary_dvi = false;