pcnet: add pcn driver
* le still working ok with QEmu * pcn brings support for the following devices in 32-bit mode (instead of 16-bit Lance compatibility mode), all untested, feedback is welcome. AMD Am79C971 PCnet-FAST, AMD Am79C972 PCnet-FAST+, AMD Am79C973/Am79C975 PCnet-FAST III, AMD Am79C976 PCnet-PRO, AMD Am79C978 PCnet-Home, Allied-Telesis LA-PCI * added PHY nsphy, nsphyter and ukphy, which seem the ones needed for pcn. * synched miidevs with FreeBSD 9.2
This commit is contained in:
Jérôme Duval
parent
5de589dae2
commit
47fe7767ca
@ -1,3 +1,5 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network pcnet dev ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network pcnet dev le ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network pcnet dev mii ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network pcnet dev pcn ;
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@ -1,6 +1,7 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network pcnet dev le ;
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UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network ] : true ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
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UsePrivateHeaders net system ;
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@ -14,5 +15,5 @@ KernelAddon pcnet :
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if_le_pci.c
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lance.c
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glue.c
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: libfreebsd_network.a
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: libfreebsd_network.a pcnet_pcn.a pcnet_mii.a
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;
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@ -7,16 +7,91 @@
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#include <net/if_media.h>
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#include <machine/bus.h>
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#include <shared.h>
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#include <dev/le/lancereg.h>
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#include <dev/le/lancevar.h>
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#include <dev/le/am79900var.h>
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HAIKU_FBSD_DRIVER_GLUE(pcnet, le, pci);
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HAIKU_FBSD_DRIVERS_GLUE(pcnet);
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HAIKU_DRIVER_REQUIREMENTS(0);
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NO_HAIKU_FBSD_MII_DRIVER();
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NO_HAIKU_REENABLE_INTERRUPTS();
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extern driver_t *DRIVER_MODULE_NAME(nsphy, miibus);
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extern driver_t *DRIVER_MODULE_NAME(nsphyter, miibus);
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extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus);
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driver_t *
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__haiku_select_miibus_driver(device_t dev)
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{
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driver_t *drivers[] = {
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DRIVER_MODULE_NAME(nsphy, miibus),
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DRIVER_MODULE_NAME(nsphyter, miibus),
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DRIVER_MODULE_NAME(ukphy, miibus),
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NULL
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};
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return __haiku_probe_miibus(dev, drivers);
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}
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int check_disable_interrupts_le(device_t dev);
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void reenable_interrupts_le(device_t dev);
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extern int check_disable_interrupts_pcn(device_t dev);
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extern void reenable_interrupts_pcn(device_t dev);
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extern driver_t *DRIVER_MODULE_NAME(le, pci);
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extern driver_t *DRIVER_MODULE_NAME(pcn, pci);
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status_t
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__haiku_handle_fbsd_drivers_list(status_t (*handler)(driver_t *[]))
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{
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driver_t *drivers[] = {
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DRIVER_MODULE_NAME(le, pci),
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DRIVER_MODULE_NAME(pcn, pci),
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NULL
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};
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return (*handler)(drivers);
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}
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int
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HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev)
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{
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switch (dev->device_name[0]) {
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case 'l':
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return check_disable_interrupts_le(dev);
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case 'p':
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return check_disable_interrupts_pcn(dev);
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default:
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break;
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}
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panic("Unsupported device: %#x (%s)!", dev->device_name[0],
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dev->device_name);
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return 0;
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}
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void
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HAIKU_REENABLE_INTERRUPTS(device_t dev)
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{
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switch (dev->device_name[0]) {
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case 'l':
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break;
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case 'p':
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reenable_interrupts_pcn(dev);
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break;
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default:
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panic("Unsupported device: %#x (%s)!", dev->device_name[0],
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dev->device_name);
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break;
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}
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}
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/* from if_le_pci.c */
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#define PCNET_PCI_RDP 0x10
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@ -35,7 +110,8 @@ struct le_pci_softc {
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bus_dmamap_t sc_dmam;
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};
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int HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev) {
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int
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check_disable_interrupts_le(device_t dev) {
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struct le_pci_softc *lesc = (struct le_pci_softc *)device_get_softc(dev);
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HAIKU_INTR_REGISTER_STATE;
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uint16_t isr;
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@ -57,9 +133,9 @@ int HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev) {
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bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, LE_CSR0);
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bus_barrier(lesc->sc_rres, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE);
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bus_write_2(lesc->sc_rres, PCNET_PCI_RDP, isr & ~(LE_C0_INEA));
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lesc->sc_am79900.lsc.sc_lastisr |= isr;
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HAIKU_INTR_REGISTER_LEAVE();
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return 1;
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23
src/add-ons/kernel/drivers/network/pcnet/dev/mii/Jamfile
Normal file
23
src/add-ons/kernel/drivers/network/pcnet/dev/mii/Jamfile
Normal file
@ -0,0 +1,23 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network pcnet dev mii ;
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UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
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UsePrivateHeaders net system ;
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UsePrivateKernelHeaders ;
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SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
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KernelStaticLibrary pcnet_mii.a
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:
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nsphy.c
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nsphyter.c
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ukphy.c
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ukphy_subr.c
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;
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ObjectHdrs [ FGristFiles nsphy$(SUFOBJ) nsphyter$(SUFOBJ) ]
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: [ FDirName $(TARGET_COMMON_DEBUG_OBJECT_DIR_$(TARGET_PACKAGING_ARCH)) libs
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compat freebsd_network ] ;
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Includes [ FGristFiles nsphy.c nsphyter.c ]
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: <src!libs!compat!freebsd_network>miidevs.h ;
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332
src/add-ons/kernel/drivers/network/pcnet/dev/mii/nsphy.c
Normal file
332
src/add-ons/kernel/drivers/network/pcnet/dev/mii/nsphy.c
Normal file
@ -0,0 +1,332 @@
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/* $NetBSD: nsphy.c,v 1.18 1999/07/14 23:57:36 thorpej Exp $ */
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/*-
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* driver for National Semiconductor's DP83840A ethernet 10/100 PHY
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* Data Sheet available from www.national.com
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/errno.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <dev/mii/nsphyreg.h>
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#include "miibus_if.h"
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static int nsphy_probe(device_t);
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static int nsphy_attach(device_t);
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static device_method_t nsphy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, nsphy_probe),
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DEVMETHOD(device_attach, nsphy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static devclass_t nsphy_devclass;
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static driver_t nsphy_driver = {
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"nsphy",
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nsphy_methods,
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sizeof(struct mii_softc)
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};
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DRIVER_MODULE(nsphy, miibus, nsphy_driver, nsphy_devclass, 0, 0);
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static int nsphy_service(struct mii_softc *, struct mii_data *, int);
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static void nsphy_status(struct mii_softc *);
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static void nsphy_reset(struct mii_softc *);
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static const struct mii_phydesc nsphys[] = {
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MII_PHY_DESC(xxNATSEMI, DP83840),
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MII_PHY_END
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};
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static const struct mii_phy_funcs nsphy_funcs = {
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nsphy_service,
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nsphy_status,
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nsphy_reset
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};
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static int
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nsphy_probe(device_t dev)
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{
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return (mii_phy_dev_probe(dev, nsphys, BUS_PROBE_DEFAULT));
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}
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static int
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nsphy_attach(device_t dev)
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{
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const char *nic;
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u_int flags;
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nic = device_get_name(device_get_parent(device_get_parent(dev)));
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flags = MIIF_NOMANPAUSE;
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/*
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* Am79C971 wedge when isolating all of their external PHYs.
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*/
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if (strcmp(nic, "pcn") == 0)
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flags |= MIIF_NOISOLATE;
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mii_phy_dev_attach(dev, flags, &nsphy_funcs, 1);
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return (0);
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}
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static int
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nsphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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int reg;
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switch (cmd) {
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case MII_POLLSTAT:
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break;
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case MII_MEDIACHG:
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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reg = PHY_READ(sc, MII_NSPHY_PCR);
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/*
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* Set up the PCR to use LED4 to indicate full-duplex
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* in both 10baseT and 100baseTX modes.
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*/
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reg |= PCR_LED4MODE;
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/*
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* Make sure Carrier Integrity Monitor function is
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* disabled (normal for Node operation, but sometimes
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* it's not set?!)
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*/
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reg |= PCR_CIMDIS;
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/*
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* Make sure "force link good" is set to normal mode.
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* It's only intended for debugging.
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*/
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reg |= PCR_FLINK100;
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/*
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* Mystery bits which are supposedly `reserved',
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* but we seem to need to set them when the PHY
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* is connected to some interfaces:
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*
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* 0x0400 is needed for fxp
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* (Intel EtherExpress Pro 10+/100B, 82557 chip)
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* (nsphy with a DP83840 chip)
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* 0x0100 may be needed for some other card
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*/
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reg |= 0x0100 | 0x0400;
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if (strcmp(mii->mii_ifp->if_dname, "fxp") == 0)
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PHY_WRITE(sc, MII_NSPHY_PCR, reg);
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mii_phy_setmedia(sc);
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break;
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case MII_TICK:
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if (mii_phy_tick(sc) == EJUSTRETURN)
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return (0);
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break;
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}
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/* Update the media status. */
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PHY_STATUS(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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nsphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int bmsr, bmcr, par, anlpar;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, MII_BMSR) |
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PHY_READ(sc, MII_BMSR);
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if (bmsr & BMSR_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, MII_BMCR);
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if (bmcr & BMCR_ISO) {
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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|
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if (bmcr & BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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if (bmcr & BMCR_AUTOEN) {
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/*
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* The PAR status bits are only valid if autonegotiation
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* has completed (or it's disabled).
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*/
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if ((bmsr & BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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|
||||
/*
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* Argh. The PAR doesn't seem to indicate duplex mode
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* properly! Determine media based on link partner's
|
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* advertised capabilities.
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*/
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if (PHY_READ(sc, MII_ANER) & ANER_LPAN) {
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anlpar = PHY_READ(sc, MII_ANAR) &
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PHY_READ(sc, MII_ANLPAR);
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if (anlpar & ANLPAR_TX_FD)
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mii->mii_media_active |= IFM_100_TX|IFM_FDX;
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else if (anlpar & ANLPAR_T4)
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mii->mii_media_active |= IFM_100_T4|IFM_HDX;
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else if (anlpar & ANLPAR_TX)
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mii->mii_media_active |= IFM_100_TX|IFM_HDX;
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else if (anlpar & ANLPAR_10_FD)
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mii->mii_media_active |= IFM_10_T|IFM_FDX;
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else if (anlpar & ANLPAR_10)
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mii->mii_media_active |= IFM_10_T|IFM_HDX;
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else
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mii->mii_media_active |= IFM_NONE;
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if ((mii->mii_media_active & IFM_FDX) != 0)
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mii->mii_media_active |=
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mii_phy_flowstatus(sc);
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return;
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}
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/*
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* Link partner is not capable of autonegotiation.
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* We will never be in full-duplex mode if this is
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* the case, so reading the PAR is OK.
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*/
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par = PHY_READ(sc, MII_NSPHY_PAR);
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if (par & PAR_10)
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mii->mii_media_active |= IFM_10_T;
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else
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mii->mii_media_active |= IFM_100_TX;
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mii->mii_media_active |= IFM_HDX;
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} else
|
||||
mii->mii_media_active = ife->ifm_media;
|
||||
}
|
||||
|
||||
static void
|
||||
nsphy_reset(struct mii_softc *sc)
|
||||
{
|
||||
struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
|
||||
int reg, i;
|
||||
|
||||
if (sc->mii_flags & MIIF_NOISOLATE)
|
||||
reg = BMCR_RESET;
|
||||
else
|
||||
reg = BMCR_RESET | BMCR_ISO;
|
||||
PHY_WRITE(sc, MII_BMCR, reg);
|
||||
|
||||
/*
|
||||
* It is best to allow a little time for the reset to settle
|
||||
* in before we start polling the BMCR again. Notably, the
|
||||
* DP83840A manuals state that there should be a 500us delay
|
||||
* between asserting software reset and attempting MII serial
|
||||
* operations. Be conservative.
|
||||
*/
|
||||
DELAY(1000);
|
||||
|
||||
/*
|
||||
* Wait another 2s for it to complete.
|
||||
* This is only a little overkill as under normal circumstances
|
||||
* the PHY can take up to 1s to complete reset.
|
||||
* This is also a bit odd because after a reset, the BMCR will
|
||||
* clear the reset bit and simply reports 0 even though the reset
|
||||
* is not yet complete.
|
||||
*/
|
||||
for (i = 0; i < 1000; i++) {
|
||||
reg = PHY_READ(sc, MII_BMCR);
|
||||
if (reg != 0 && (reg & BMCR_RESET) == 0)
|
||||
break;
|
||||
DELAY(2000);
|
||||
}
|
||||
|
||||
if ((sc->mii_flags & MIIF_NOISOLATE) == 0) {
|
||||
if ((ife == NULL && sc->mii_inst != 0) ||
|
||||
(ife != NULL && IFM_INST(ife->ifm_media) != sc->mii_inst))
|
||||
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
||||
}
|
||||
}
|
||||
108
src/add-ons/kernel/drivers/network/pcnet/dev/mii/nsphyreg.h
Normal file
108
src/add-ons/kernel/drivers/network/pcnet/dev/mii/nsphyreg.h
Normal file
@ -0,0 +1,108 @@
|
||||
/* $NetBSD: nsphyreg.h,v 1.1 1998/08/10 23:58:39 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_MII_NSPHYREG_H_
|
||||
#define _DEV_MII_NSPHYREG_H_
|
||||
|
||||
/*
|
||||
* DP83840 registers.
|
||||
*/
|
||||
|
||||
#define MII_NSPHY_DCR 0x12 /* Disconnect counter */
|
||||
|
||||
#define MII_NSPHY_FCSCR 0x13 /* False carrier sense counter */
|
||||
|
||||
#define MII_NSPHY_RECR 0x15 /* Receive error counter */
|
||||
|
||||
#define MII_NSPHY_SRR 0x16 /* Silicon revision */
|
||||
|
||||
#define MII_NSPHY_PCR 0x17 /* PCS sub-layer configuration */
|
||||
#define PCR_NRZI 0x8000 /* NRZI encoding enabled for 100TX */
|
||||
#define PCR_DESCRTOSEL 0x4000 /* descrambler t/o select (2ms) */
|
||||
#define PCR_DESCRTODIS 0x2000 /* descrambler t/o disable */
|
||||
#define PCR_REPEATER 0x1000 /* repeater mode */
|
||||
#define PCR_ENCSEL 0x0800 /* encoder mode select */
|
||||
#define PCR_CLK25MDIS 0x0080 /* CLK25M disable */
|
||||
#define PCR_FLINK100 0x0040 /* force good link in 100mbps */
|
||||
#define PCR_CIMDIS 0x0020 /* carrier integrity monitor disable */
|
||||
#define PCR_TXOFF 0x0010 /* force transmit off */
|
||||
#define PCR_LED1MODE 0x0004 /* LED1 mode: see below */
|
||||
#define PCR_LED4MODE 0x0002 /* LED4 mode: see below */
|
||||
|
||||
/*
|
||||
* LED1 Mode:
|
||||
*
|
||||
* 1 LED1 output configured to PAR's CON_STATUS, useful for
|
||||
* network management in 100baseTX mode.
|
||||
*
|
||||
* 0 Normal LED1 operation - 10baseTX and 100baseTX transmission
|
||||
* activity.
|
||||
*
|
||||
* LED4 Mode:
|
||||
*
|
||||
* 1 LED4 output configured to indicate full-duplex in both
|
||||
* 10baseT and 100baseTX modes.
|
||||
*
|
||||
* 0 LED4 output configured to indicate polarity in 10baseT
|
||||
* mode and full-duplex in 100baseTX mode.
|
||||
*/
|
||||
|
||||
#define MII_NSPHY_LBREMR 0x18 /* Loopback, bypass, error mask */
|
||||
#define LBREMR_BADSSDEN 0x8000 /* enable bad SSD detection */
|
||||
#define LBREMR_BP4B5B 0x4000 /* bypass 4b/5b encoding */
|
||||
#define LBREMR_BPSCR 0x2000 /* bypass scrambler */
|
||||
#define LBREMR_BPALIGN 0x1000 /* bypass alignment function */
|
||||
#define LBREMR_10LOOP 0x0800 /* 10baseT loopback */
|
||||
#define LBREMR_LB1 0x0200 /* loopback ctl 1 */
|
||||
#define LBREMR_LB0 0x0100 /* loopback ctl 0 */
|
||||
#define LBREMR_ALTCRS 0x0040 /* alt crs operation */
|
||||
#define LBREMR_LOOPXMTDIS 0x0020 /* disable transmit in 100TX loopbk */
|
||||
#define LBREMR_CODEERR 0x0010 /* code errors */
|
||||
#define LBREMR_PEERR 0x0008 /* premature end errors */
|
||||
#define LBREMR_LINKERR 0x0004 /* link errors */
|
||||
#define LBREMR_PKTERR 0x0002 /* packet errors */
|
||||
|
||||
#define MII_NSPHY_PAR 0x19 /* Physical address and status */
|
||||
#define PAR_DISCRSJAB 0x0800 /* disable car sense during jab */
|
||||
#define PAR_ANENSTAT 0x0400 /* autoneg mode status */
|
||||
#define PAR_FEFIEN 0x0100 /* far end fault enable */
|
||||
#define PAR_FDX 0x0080 /* full duplex status */
|
||||
#define PAR_10 0x0040 /* 10mbps mode */
|
||||
#define PAR_CON 0x0020 /* connect status */
|
||||
#define PAR_AMASK 0x001f /* PHY address bits */
|
||||
|
||||
#define MII_NSPHY_10BTSR 0x1b /* 10baseT status */
|
||||
#define MII_NSPHY_10BTCR 0x1c /* 10baseT configuration */
|
||||
|
||||
#endif /* _DEV_MII_NSPHYREG_H_ */
|
||||
268
src/add-ons/kernel/drivers/network/pcnet/dev/mii/nsphyter.c
Normal file
268
src/add-ons/kernel/drivers/network/pcnet/dev/mii/nsphyter.c
Normal file
@ -0,0 +1,268 @@
|
||||
/* $NetBSD: nsphyter.c,v 1.28 2008/01/20 07:58:19 msaitoh Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* Driver for the National Semiconductor's DP83843, DP83847 and DP83849
|
||||
* `PHYTER' Ethernet 10/100 PHYs
|
||||
* Data Sheets are available from http://www.national.com
|
||||
*
|
||||
* We also support the DP83815 `MacPHYTER' internal PHY since, for our
|
||||
* purposes, they are compatible.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/socket.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
#include "miidevs.h"
|
||||
|
||||
#include <dev/mii/nsphyterreg.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static device_probe_t nsphyter_probe;
|
||||
static device_attach_t nsphyter_attach;
|
||||
|
||||
static device_method_t nsphyter_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, nsphyter_probe),
|
||||
DEVMETHOD(device_attach, nsphyter_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static devclass_t nsphyter_devclass;
|
||||
|
||||
static driver_t nsphyter_driver = {
|
||||
"nsphyter",
|
||||
nsphyter_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(nsphyter, miibus, nsphyter_driver, nsphyter_devclass, 0, 0);
|
||||
|
||||
static int nsphyter_service(struct mii_softc *, struct mii_data *, int);
|
||||
static void nsphyter_status(struct mii_softc *);
|
||||
static void nsphyter_reset(struct mii_softc *);
|
||||
|
||||
static const struct mii_phydesc nsphyters[] = {
|
||||
MII_PHY_DESC(xxNATSEMI, DP83815),
|
||||
MII_PHY_DESC(xxNATSEMI, DP83843),
|
||||
MII_PHY_DESC(xxNATSEMI, DP83847),
|
||||
MII_PHY_DESC(xxNATSEMI, DP83849),
|
||||
MII_PHY_END
|
||||
};
|
||||
|
||||
static const struct mii_phy_funcs nsphyter_funcs = {
|
||||
nsphyter_service,
|
||||
nsphyter_status,
|
||||
nsphyter_reset
|
||||
};
|
||||
|
||||
static int
|
||||
nsphyter_probe(device_t dev)
|
||||
{
|
||||
|
||||
return (mii_phy_dev_probe(dev, nsphyters, BUS_PROBE_DEFAULT));
|
||||
}
|
||||
|
||||
static int
|
||||
nsphyter_attach(device_t dev)
|
||||
{
|
||||
|
||||
mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &nsphyter_funcs, 1);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nsphyter_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
/*
|
||||
* If the interface is not up, don't do anything.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
break;
|
||||
|
||||
mii_phy_setmedia(sc);
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
if (mii_phy_tick(sc) == EJUSTRETURN)
|
||||
return (0);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
PHY_STATUS(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
nsphyter_status(struct mii_softc *sc)
|
||||
{
|
||||
struct mii_data *mii = sc->mii_pdata;
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int bmsr, bmcr, physts;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
|
||||
physts = PHY_READ(sc, MII_NSPHYTER_PHYSTS);
|
||||
|
||||
if ((physts & PHYSTS_LINK) != 0)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
bmcr = PHY_READ(sc, MII_BMCR);
|
||||
if ((bmcr & BMCR_ISO) != 0) {
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
mii->mii_media_status = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((bmcr & BMCR_LOOP) != 0)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if ((bmcr & BMCR_AUTOEN) != 0) {
|
||||
/*
|
||||
* The media status bits are only valid if autonegotiation
|
||||
* has completed (or it's disabled).
|
||||
*/
|
||||
if ((bmsr & BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((physts & PHYSTS_SPEED10) != 0)
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
else
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
if ((physts & PHYSTS_DUPLEX) != 0)
|
||||
mii->mii_media_active |=
|
||||
IFM_FDX | mii_phy_flowstatus(sc);
|
||||
else
|
||||
mii->mii_media_active |= IFM_HDX;
|
||||
} else
|
||||
mii->mii_media_active = ife->ifm_media;
|
||||
}
|
||||
|
||||
static void
|
||||
nsphyter_reset(struct mii_softc *sc)
|
||||
{
|
||||
struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
|
||||
int reg, i;
|
||||
|
||||
if ((sc->mii_flags & MIIF_NOISOLATE) != 0)
|
||||
reg = BMCR_RESET;
|
||||
else
|
||||
reg = BMCR_RESET | BMCR_ISO;
|
||||
PHY_WRITE(sc, MII_BMCR, reg);
|
||||
|
||||
/*
|
||||
* It is best to allow a little time for the reset to settle
|
||||
* in before we start polling the BMCR again. Notably, the
|
||||
* DP8384{3,7} manuals state that there should be a 500us delay
|
||||
* between asserting software reset and attempting MII serial
|
||||
* operations. Be conservative. Also, a DP83815 can get into
|
||||
* a bad state on cable removal and reinsertion if we do not
|
||||
* delay here.
|
||||
*/
|
||||
DELAY(1000);
|
||||
|
||||
/*
|
||||
* Wait another 2s for it to complete.
|
||||
* This is only a little overkill as under normal circumstances
|
||||
* the PHY can take up to 1s to complete reset.
|
||||
* This is also a bit odd because after a reset, the BMCR will
|
||||
* clear the reset bit and simply reports 0 even though the reset
|
||||
* is not yet complete.
|
||||
*/
|
||||
for (i = 0; i < 1000; i++) {
|
||||
reg = PHY_READ(sc, MII_BMCR);
|
||||
if (reg != 0 && (reg & BMCR_RESET) == 0)
|
||||
break;
|
||||
DELAY(2000);
|
||||
}
|
||||
|
||||
if ((sc->mii_flags & MIIF_NOISOLATE) == 0) {
|
||||
if ((ife == NULL && sc->mii_inst != 0) ||
|
||||
(ife != NULL && IFM_INST(ife->ifm_media) != sc->mii_inst))
|
||||
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
||||
}
|
||||
}
|
||||
179
src/add-ons/kernel/drivers/network/pcnet/dev/mii/nsphyterreg.h
Normal file
179
src/add-ons/kernel/drivers/network/pcnet/dev/mii/nsphyterreg.h
Normal file
@ -0,0 +1,179 @@
|
||||
/* $NetBSD: nsphyterreg.h,v 1.4 2005/12/11 12:22:42 christos Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1999, 2001 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_MII_NSPHYTERREG_H_
|
||||
#define _DEV_MII_NSPHYTERREG_H_
|
||||
|
||||
/*
|
||||
* DP83843 registers; We also have the MacPHYTER (DP83815) internal
|
||||
* PHY register definitions here, since the two are, for our purposes,
|
||||
* compatible.
|
||||
*/
|
||||
|
||||
#define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
|
||||
#define PHYSTS_REL 0x8000 /* receive error latch */
|
||||
#define PHYSTS_CIML 0x4000 /* CIM latch */
|
||||
#define PHYSTS_FCSL 0x2000 /* false carrier sense latch */
|
||||
#define PHYSTS_DEVRDY 0x0800 /* device ready */
|
||||
#define PHYSTS_PGRX 0x0400 /* page received */
|
||||
#define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */
|
||||
#define PHYSTS_MIIINTR 0x0100 /* MII interrupt */
|
||||
#define PHYSTS_REMFAULT 0x0080 /* remote fault */
|
||||
#define PHYSTS_JABBER 0x0040 /* jabber detect */
|
||||
#define PHYSTS_NWAYCOMP 0x0020 /* NWAY complete */
|
||||
#define PHYSTS_RESETSTAT 0x0010 /* reset status */
|
||||
#define PHYSTS_LOOPBACK 0x0008 /* loopback status */
|
||||
#define PHYSTS_DUPLEX 0x0004 /* full duplex */
|
||||
#define PHYSTS_SPEED10 0x0002 /* speed == 10Mb/s */
|
||||
#define PHYSTS_LINK 0x0001 /* link up */
|
||||
/* Below are the MacPHYTER bits that are different. */
|
||||
#define PHYSTS_MP_REL 0x2000 /* receive error latch */
|
||||
#define PHYSTS_MP_POLARITY 0x1000 /* polarity inverted */
|
||||
#define PHYSTS_MP_FCSL 0x0800 /* false carrier sense latch */
|
||||
#define PHYSTS_MP_SIGNAL 0x0400 /* signal detect */
|
||||
#define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
|
||||
#define PHYSTS_MP_PGRX 0x0100 /* page received */
|
||||
#define PHYSTS_MP_MIIINTR 0x0080 /* MII interrupt */
|
||||
#define PHYSTS_MP_REMFAULT 0x0040 /* remote fault */
|
||||
#define PHYSTS_MP_JABBER 0x0020 /* jabber detect */
|
||||
#define PHYSTS_MP_NWAYCOMP 0x0010 /* NWAY complete */
|
||||
|
||||
|
||||
#define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific
|
||||
control */
|
||||
|
||||
#define MIPSCR_INTEN 0x0002 /* interrupt enable */
|
||||
#define MIPSCR_TINT 0x0001 /* test interrupt */
|
||||
|
||||
|
||||
#define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic
|
||||
status */
|
||||
#define MIPGSR_MINT 0x8000 /* MII interrupt pending */
|
||||
/* The bits below are MacPHYTER only. */
|
||||
#define MIPGSR_MSK_LINK 0x4000 /* mask link status event */
|
||||
#define MIPGSR_MSK_JAB 0x2000 /* mask jabber event */
|
||||
#define MIPGSR_MSK_RF 0x1000 /* mask remote fault event */
|
||||
#define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
|
||||
#define MIPGSR_MSK_FHF 0x0400 /* mask false carrier half full event */
|
||||
#define MIPGSR_MSK_RHF 0x0200 /* mask RX error half full event */
|
||||
|
||||
#define MII_NSPHYTER_DCR 0x13 /* Disconnect counter */
|
||||
|
||||
#define MII_NSPHYTER_FCSCR 0x14 /* False carrier sense counter */
|
||||
|
||||
#define MII_NSPHYTER_RECR 0x15 /* Receive error counter */
|
||||
|
||||
|
||||
#define MII_NSPHYTER_PCSR 0x16 /* PCS configuration and status */
|
||||
#define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
|
||||
#define PCSR_FEFI_EN 0x4000 /* far end fault indication mode */
|
||||
#define PCSR_DESCR_TO_RST 0x2000 /* reset descrambler timeout counter */
|
||||
#define PCSR_DESCR_TO_SEL 0x1000 /* descrambler timer mode */
|
||||
#define PCSR_DESCR_TO_DIS 0x0800 /* descrambler timer disable */
|
||||
#define PCSR_LD_SCR_SD 0x0400 /* load scrambler seed */
|
||||
#define PCSR_TX_QUIET 0x0200 /* 100Mb/s transmit true quiet mode */
|
||||
#define PCSR_TX_PATTERN 0x0180 /* 100Mb/s transmit test pattern */
|
||||
#define PCSR_F_LINK_100 0x0040 /* force good link in 100Mb/s */
|
||||
#define PCSR_CIM_DIS 0x0020 /* carrier integrity monitor disable */
|
||||
#define PCSR_CIM_STATUS 0x0010 /* carrier integrity monitor status */
|
||||
#define PCSR_CODE_ERR 0x0008 /* code errors */
|
||||
#define PCSR_PME_ERR 0x0004 /* premature end errors */
|
||||
#define PCSR_LINK_ERR 0x0002 /* link errors */
|
||||
#define PCSR_PKT_ERR 0x0001 /* packet errors */
|
||||
/* Below are the MacPHYTER bits that are different. */
|
||||
#define PCSR_MP_BYP_4B5B 0x1000 /* bypass encoder */
|
||||
#define PCSR_MP_FREE_CLK 0x0800 /* free funning RX clock */
|
||||
#define PCSR_MP_TQ_EN 0x0400 /* enable True Quiet mode */
|
||||
#define PCSR_MP_SD_FORCE_B 0x0200 /* force signal detection */
|
||||
#define PCSR_MP_SD_OPTION 0x0100 /* enhanced signal detection alg. */
|
||||
#define PCSR_MP_NRZI_BYPASS 0x0004 /* NRZI bypass enabled */
|
||||
|
||||
|
||||
/* The bits below are not on MacPHYTER. */
|
||||
#define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */
|
||||
#define LBR_BP_STRETCH 0x4000 /* bypass LED stretching */
|
||||
#define LBR_BP_4B5B 0x2000 /* bypass encoding/decoding */
|
||||
#define LBR_BP_SCR 0x1000 /* bypass scrambler/descrambler */
|
||||
#define LBR_BP_RX 0x0800 /* bypass receive function */
|
||||
#define LBR_BP_TX 0x0400 /* bypass transmit function */
|
||||
#define LBR_100_DP_CTL 0x0380 /* 100Mb/s data patch control */
|
||||
#define LBR_TW_LBEN 0x0020 /* TWISTER loopback enable */
|
||||
#define LBR_10_ENDEC_LB 0x0010 /* 10Mb/s ENDEC loopback */
|
||||
|
||||
|
||||
/* The bits below are not on MacPHYTER. */
|
||||
#define MII_NSPHYTER_10BTSCR 0x18 /* 10baseT status and control */
|
||||
#define BTSCR_AUI_TPI 0x2000 /* TREX operating mode */
|
||||
#define BTSCR_RX_SERIAL 0x1000 /* 10baseT RX serial mode */
|
||||
#define BTSCR_TX_SERIAL 0x0800 /* 10baseT TX serial mode */
|
||||
#define BTSCR_POL_DS 0x0400 /* polarity detection and correction
|
||||
disable */
|
||||
#define BTSCR_AUTOSW_EN 0x0200 /* AUI/TPI autoswitch */
|
||||
#define BTSCR_LP_DS 0x0100 /* link pulse disable */
|
||||
#define BTSCR_HB_DS 0x0080 /* heartbeat disabled */
|
||||
#define BTSCR_LS_SEL 0x0040 /* low squelch select */
|
||||
#define BTSCR_AUI_SEL 0x0020 /* AUI select */
|
||||
#define BTSCR_JAB_DS 0x0010 /* jabber disable */
|
||||
#define BTSCR_THIN_SEL 0x0008 /* thin ethernet select */
|
||||
#define BTSCR_TX_FILT_DS 0x0004 /* TPI receive filter disable */
|
||||
|
||||
|
||||
#define MII_NSPHYTER_PHYCTRL 0x19 /* PHY control */
|
||||
#define PHYCTRL_TW_EQSEL 0x3000 /* TWISTER e.q. select */
|
||||
#define PHYCTRL_BLW_DS 0x0800 /* TWISTER base line wander disable */
|
||||
#define PHYCTRL_REPEATER 0x0200 /* repeater mode */
|
||||
#define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */
|
||||
#define PHYCTRL_LED_DUP_MODE 0x0040 /* LED DUP mode */
|
||||
#define PHYCTRL_FX_EN 0x0020 /* Fiber mode enable */
|
||||
#define PHYCTRL_PHYADDR 0x001f /* PHY address */
|
||||
/* Below are the MacPHYTER bits that are different. */
|
||||
#define PHYCRTL_MP_PSR_15 0x0800 /* BIST sequence select */
|
||||
#define PHYCTRL_MP_BIST_STAT 0x0400 /* BIST passed */
|
||||
#define PHYCTRL_MP_BIST_START 0x0200 /* start BIST */
|
||||
#define PHYCTRL_MP_BP_STRETCH 0x0100 /* bypass LED stretching */
|
||||
#define PHYCTRL_MP_PAUSE_STS 0x0080 /* pause status */
|
||||
|
||||
|
||||
/* The bits below are MacPHYTER only. */
|
||||
#define MII_MACPHYTER_TBTCTL 0x1a /* 10baseT Control */
|
||||
#define TBTCTL_LOOPBACK_10_DIS 0x0100 /* loopback 10Mb/s disable */
|
||||
#define TBTCTL_LP_DIS 0x0080 /* link pulse disable */
|
||||
#define TBTCTL_FORCE_LINK_10 0x0040 /* force 10Mb/s link good */
|
||||
#define TBTCTL_FORCE_POL_COR 0x0020 /* force polarity correction */
|
||||
#define TBTCTL_INV_POLARITY 0x0010 /* inverted polarity */
|
||||
#define TBTCTL_AUTOPOL_DIS 0x0008 /* auto-polarity disable */
|
||||
#define TBTCTL_HEARTBEAT_DIS 0x0002 /* heartbeat disable */
|
||||
#define TBTCTL_JABBER_DIS 0x0001 /* jabber disable */
|
||||
|
||||
#endif /* _DEV_MII_NSPHYTERREG_H_ */
|
||||
164
src/add-ons/kernel/drivers/network/pcnet/dev/mii/ukphy.c
Normal file
164
src/add-ons/kernel/drivers/network/pcnet/dev/mii/ukphy.c
Normal file
@ -0,0 +1,164 @@
|
||||
/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* driver for generic unknown PHYs
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static int ukphy_probe(device_t);
|
||||
static int ukphy_attach(device_t);
|
||||
|
||||
static device_method_t ukphy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, ukphy_probe),
|
||||
DEVMETHOD(device_attach, ukphy_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static devclass_t ukphy_devclass;
|
||||
|
||||
static driver_t ukphy_driver = {
|
||||
"ukphy",
|
||||
ukphy_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0);
|
||||
|
||||
static int ukphy_service(struct mii_softc *, struct mii_data *, int);
|
||||
|
||||
static const struct mii_phy_funcs ukphy_funcs = {
|
||||
ukphy_service,
|
||||
ukphy_status,
|
||||
mii_phy_reset
|
||||
};
|
||||
|
||||
static int
|
||||
ukphy_probe(device_t dev)
|
||||
{
|
||||
|
||||
/*
|
||||
* We know something is here, so always match at a low priority.
|
||||
*/
|
||||
device_set_desc(dev, "Generic IEEE 802.3u media interface");
|
||||
return (BUS_PROBE_GENERIC);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_attach(device_t dev)
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &ukphy_funcs, 1);
|
||||
mii_phy_setmedia(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
/*
|
||||
* If the interface is not up, don't do anything.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
break;
|
||||
|
||||
mii_phy_setmedia(sc);
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
if (mii_phy_tick(sc) == EJUSTRETURN)
|
||||
return (0);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
PHY_STATUS(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
129
src/add-ons/kernel/drivers/network/pcnet/dev/mii/ukphy_subr.c
Normal file
129
src/add-ons/kernel/drivers/network/pcnet/dev/mii/ukphy_subr.c
Normal file
@ -0,0 +1,129 @@
|
||||
/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* Subroutines shared by the ukphy driver and other PHY drivers.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
/*
|
||||
* Media status subroutine. If a PHY driver does media detection simply
|
||||
* by decoding the NWay autonegotiation, use this routine.
|
||||
*/
|
||||
void
|
||||
ukphy_status(struct mii_softc *phy)
|
||||
{
|
||||
struct mii_data *mii = phy->mii_pdata;
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int bmsr, bmcr, anlpar, gtcr, gtsr;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
|
||||
if (bmsr & BMSR_LINK)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
bmcr = PHY_READ(phy, MII_BMCR);
|
||||
if (bmcr & BMCR_ISO) {
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
mii->mii_media_status = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if (bmcr & BMCR_LOOP)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if (bmcr & BMCR_AUTOEN) {
|
||||
/*
|
||||
* NWay autonegotiation takes the highest-order common
|
||||
* bit of the ANAR and ANLPAR (i.e. best media advertised
|
||||
* both by us and our link partner).
|
||||
*/
|
||||
if ((bmsr & BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
|
||||
if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
|
||||
(phy->mii_extcapabilities &
|
||||
(EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) {
|
||||
gtcr = PHY_READ(phy, MII_100T2CR);
|
||||
gtsr = PHY_READ(phy, MII_100T2SR);
|
||||
} else
|
||||
gtcr = gtsr = 0;
|
||||
|
||||
if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX))
|
||||
mii->mii_media_active |= IFM_1000_T|IFM_FDX;
|
||||
else if ((gtcr & GTCR_ADV_1000THDX) &&
|
||||
(gtsr & GTSR_LP_1000THDX))
|
||||
mii->mii_media_active |= IFM_1000_T|IFM_HDX;
|
||||
else if (anlpar & ANLPAR_TX_FD)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_T4)
|
||||
mii->mii_media_active |= IFM_100_T4|IFM_HDX;
|
||||
else if (anlpar & ANLPAR_TX)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_HDX;
|
||||
else if (anlpar & ANLPAR_10_FD)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_10)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_HDX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
|
||||
if ((mii->mii_media_active & IFM_1000_T) != 0 &&
|
||||
(gtsr & GTSR_MS_RES) != 0)
|
||||
mii->mii_media_active |= IFM_ETH_MASTER;
|
||||
|
||||
if ((mii->mii_media_active & IFM_FDX) != 0)
|
||||
mii->mii_media_active |= mii_phy_flowstatus(phy);
|
||||
} else
|
||||
mii->mii_media_active = ife->ifm_media;
|
||||
}
|
||||
15
src/add-ons/kernel/drivers/network/pcnet/dev/pcn/Jamfile
Normal file
15
src/add-ons/kernel/drivers/network/pcnet/dev/pcn/Jamfile
Normal file
@ -0,0 +1,15 @@
|
||||
SubDir HAIKU_TOP src add-ons kernel drivers network pcnet dev pcn ;
|
||||
|
||||
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
|
||||
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
|
||||
|
||||
UsePrivateHeaders net system ;
|
||||
UsePrivateKernelHeaders ;
|
||||
|
||||
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
|
||||
|
||||
KernelStaticLibrary pcnet_pcn.a
|
||||
:
|
||||
if_pcn.c
|
||||
glue.c
|
||||
;
|
||||
77
src/add-ons/kernel/drivers/network/pcnet/dev/pcn/glue.c
Normal file
77
src/add-ons/kernel/drivers/network/pcnet/dev/pcn/glue.c
Normal file
@ -0,0 +1,77 @@
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/ethernet.h>
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <dev/pcn/if_pcnreg.h>
|
||||
|
||||
#define PCN_CSR_SETBIT(sc, reg, x) \
|
||||
pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
|
||||
|
||||
#define PCN_CSR_CLRBIT(sc, reg, x) \
|
||||
pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
|
||||
|
||||
|
||||
int check_disable_interrupts_pcn(device_t dev);
|
||||
void reenable_interrupts_pcn(device_t dev);
|
||||
|
||||
|
||||
static u_int32_t
|
||||
pcn_csr_read(sc, reg)
|
||||
struct pcn_softc *sc;
|
||||
int reg;
|
||||
{
|
||||
CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
|
||||
return(CSR_READ_4(sc, PCN_IO32_RDP));
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
pcn_csr_write(sc, reg, val)
|
||||
struct pcn_softc *sc;
|
||||
int reg;
|
||||
int val;
|
||||
{
|
||||
CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
|
||||
CSR_WRITE_4(sc, PCN_IO32_RDP, val);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
check_disable_interrupts_pcn(device_t dev)
|
||||
{
|
||||
struct pcn_softc *sc = device_get_softc(dev);
|
||||
HAIKU_INTR_REGISTER_STATE;
|
||||
uint32_t status;
|
||||
|
||||
HAIKU_INTR_REGISTER_ENTER();
|
||||
|
||||
/* get current flags */
|
||||
CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
|
||||
status = CSR_READ_4(sc, PCN_IO32_RDP);
|
||||
|
||||
/* is there a pending interrupt? */
|
||||
if ((status & PCN_CSR_INTR) == 0) {
|
||||
HAIKU_INTR_REGISTER_LEAVE();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* set the new flags, disable interrupts */
|
||||
PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
|
||||
|
||||
HAIKU_INTR_REGISTER_LEAVE();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
reenable_interrupts_pcn(device_t dev)
|
||||
{
|
||||
struct pcn_softc *sc = device_get_softc(dev);
|
||||
PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
|
||||
}
|
||||
1518
src/add-ons/kernel/drivers/network/pcnet/dev/pcn/if_pcn.c
Normal file
1518
src/add-ons/kernel/drivers/network/pcnet/dev/pcn/if_pcn.c
Normal file
File diff suppressed because it is too large
Load Diff
531
src/add-ons/kernel/drivers/network/pcnet/dev/pcn/if_pcnreg.h
Normal file
531
src/add-ons/kernel/drivers/network/pcnet/dev/pcn/if_pcnreg.h
Normal file
@ -0,0 +1,531 @@
|
||||
/*-
|
||||
* Copyright (c) 2000 Berkeley Software Design, Inc.
|
||||
* Copyright (c) 1997, 1998, 1999, 2000
|
||||
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* I/O map in 16-bit mode. To switch to 32-bit mode,
|
||||
* you need to perform a 32-bit write to the RDP register
|
||||
* (writing a 0 is recommended).
|
||||
*/
|
||||
#define PCN_IO16_APROM00 0x00
|
||||
#define PCN_IO16_APROM01 0x02
|
||||
#define PCN_IO16_APROM02 0x04
|
||||
#define PCN_IO16_APROM03 0x06
|
||||
#define PCN_IO16_APROM04 0x08
|
||||
#define PCN_IO16_APROM05 0x0A
|
||||
#define PCN_IO16_APROM06 0x0C
|
||||
#define PCN_IO16_APROM07 0x0E
|
||||
#define PCN_IO16_RDP 0x10
|
||||
#define PCN_IO16_RAP 0x12
|
||||
#define PCN_IO16_RESET 0x14
|
||||
#define PCN_IO16_BDP 0x16
|
||||
|
||||
/*
|
||||
* I/O map in 32-bit mode.
|
||||
*/
|
||||
#define PCN_IO32_APROM00 0x00
|
||||
#define PCN_IO32_APROM01 0x04
|
||||
#define PCN_IO32_APROM02 0x08
|
||||
#define PCN_IO32_APROM03 0x0C
|
||||
#define PCN_IO32_RDP 0x10
|
||||
#define PCN_IO32_RAP 0x14
|
||||
#define PCN_IO32_RESET 0x18
|
||||
#define PCN_IO32_BDP 0x1C
|
||||
|
||||
/*
|
||||
* CSR registers
|
||||
*/
|
||||
#define PCN_CSR_CSR 0x00
|
||||
#define PCN_CSR_IAB0 0x01
|
||||
#define PCN_CSR_IAB1 0x02
|
||||
#define PCN_CSR_IMR 0x03
|
||||
#define PCN_CSR_TFEAT 0x04
|
||||
#define PCN_CSR_EXTCTL1 0x05
|
||||
#define PCN_CSR_DTBLLEN 0x06
|
||||
#define PCN_CSR_EXTCTL2 0x07
|
||||
#define PCN_CSR_MAR0 0x08
|
||||
#define PCN_CSR_MAR1 0x09
|
||||
#define PCN_CSR_MAR2 0x0A
|
||||
#define PCN_CSR_MAR3 0x0B
|
||||
#define PCN_CSR_PAR0 0x0C
|
||||
#define PCN_CSR_PAR1 0x0D
|
||||
#define PCN_CSR_PAR2 0x0E
|
||||
#define PCN_CSR_MODE 0x0F
|
||||
#define PCN_CSR_RXADDR0 0x18
|
||||
#define PCN_CSR_RXADDR1 0x19
|
||||
#define PCN_CSR_TXADDR0 0x1E
|
||||
#define PCN_CSR_TXADDR1 0x1F
|
||||
#define PCN_CSR_TXPOLL 0x2F
|
||||
#define PCN_CSR_RXPOLL 0x31
|
||||
#define PCN_CSR_RXRINGLEN 0x4C
|
||||
#define PCN_CSR_TXRINGLEN 0x4E
|
||||
#define PCN_CSR_DMACTL 0x50
|
||||
#define PCN_CSR_BUSTIMER 0x52
|
||||
#define PCN_CSR_MEMERRTIMEO 0x64
|
||||
#define PCN_CSR_ONNOWMISC 0x74
|
||||
#define PCN_CSR_ADVFEAT 0x7A
|
||||
#define PCN_CSR_MACCFG 0x7D
|
||||
#define PCN_CSR_CHIPID0 0x58
|
||||
#define PCN_CSR_CHIPID1 0x59
|
||||
|
||||
/*
|
||||
* Control and status register (CSR0)
|
||||
*/
|
||||
#define PCN_CSR_INIT 0x0001
|
||||
#define PCN_CSR_START 0x0002
|
||||
#define PCN_CSR_STOP 0x0004
|
||||
#define PCN_CSR_TX 0x0008
|
||||
#define PCN_CSR_TXON 0x0010
|
||||
#define PCN_CSR_RXON 0x0020
|
||||
#define PCN_CSR_INTEN 0x0040
|
||||
#define PCN_CSR_INTR 0x0080
|
||||
#define PCN_CSR_IDONE 0x0100
|
||||
#define PCN_CSR_TINT 0x0200
|
||||
#define PCN_CSR_RINT 0x0400
|
||||
#define PCN_CSR_MERR 0x0800
|
||||
#define PCN_CSR_MISS 0x1000
|
||||
#define PCN_CSR_CERR 0x2000
|
||||
#define PCN_CSR_ERR 0x8000
|
||||
|
||||
/*
|
||||
* Interrupt masks and deferral control (CSR3)
|
||||
*/
|
||||
#define PCN_IMR_BSWAP 0x0004
|
||||
#define PCN_IMR_ENMBA 0x0008 /* enable modified backoff alg */
|
||||
#define PCN_IMR_DXMT2PD 0x0010
|
||||
#define PCN_IMR_LAPPEN 0x0020 /* lookahead packet processing enb */
|
||||
#define PCN_IMR_DXSUFLO 0x0040 /* disable TX stop on underflow */
|
||||
#define PCN_IMR_IDONE 0x0100
|
||||
#define PCN_IMR_TINT 0x0200
|
||||
#define PCN_IMR_RINT 0x0400
|
||||
#define PCN_IMR_MERR 0x0800
|
||||
#define PCN_IMR_MISS 0x1000
|
||||
|
||||
/*
|
||||
* Test and features control (CSR4)
|
||||
*/
|
||||
#define PCN_TFEAT_TXSTRTMASK 0x0004
|
||||
#define PCN_TFEAT_TXSTRT 0x0008
|
||||
#define PCN_TFEAT_RXCCOFLOWM 0x0010 /* Rx collision counter oflow */
|
||||
#define PCN_TFEAT_RXCCOFLOW 0x0020
|
||||
#define PCN_TFEAT_UINT 0x0040
|
||||
#define PCN_TFEAT_UINTREQ 0x0080
|
||||
#define PCN_TFEAT_MISSOFLOWM 0x0100
|
||||
#define PCN_TFEAT_MISSOFLOW 0x0200
|
||||
#define PCN_TFEAT_STRIP_FCS 0x0400
|
||||
#define PCN_TFEAT_PAD_TX 0x0800
|
||||
#define PCN_TFEAT_TXDPOLL 0x1000
|
||||
#define PCN_TFEAT_DMAPLUS 0x4000
|
||||
|
||||
/*
|
||||
* Extended control and interrupt 1 (CSR5)
|
||||
*/
|
||||
#define PCN_EXTCTL1_SPND 0x0001 /* suspend */
|
||||
#define PCN_EXTCTL1_MPMODE 0x0002 /* magic packet mode */
|
||||
#define PCN_EXTCTL1_MPENB 0x0004 /* magic packet enable */
|
||||
#define PCN_EXTCTL1_MPINTEN 0x0008 /* magic packet interrupt enable */
|
||||
#define PCN_EXTCTL1_MPINT 0x0010 /* magic packet interrupt */
|
||||
#define PCN_EXTCTL1_MPPLBA 0x0020 /* magic packet phys. logical bcast */
|
||||
#define PCN_EXTCTL1_EXDEFEN 0x0040 /* excessive deferral interrupt enb. */
|
||||
#define PCN_EXTCTL1_EXDEF 0x0080 /* excessive deferral interrupt */
|
||||
#define PCN_EXTCTL1_SINTEN 0x0400 /* system interrupt enable */
|
||||
#define PCN_EXTCTL1_SINT 0x0800 /* system interrupt */
|
||||
#define PCN_EXTCTL1_LTINTEN 0x4000 /* last TX interrupt enb */
|
||||
#define PCN_EXTCTL1_TXOKINTD 0x8000 /* TX OK interrupt disable */
|
||||
|
||||
/*
|
||||
* RX/TX descriptor len (CSR6)
|
||||
*/
|
||||
#define PCN_DTBLLEN_RLEN 0x0F00
|
||||
#define PCN_DTBLLEN_TLEN 0xF000
|
||||
|
||||
/*
|
||||
* Extended control and interrupt 2 (CSR7)
|
||||
*/
|
||||
#define PCN_EXTCTL2_MIIPDTINTE 0x0001
|
||||
#define PCN_EXTCTL2_MIIPDTINT 0x0002
|
||||
#define PCN_EXTCTL2_MCCIINTE 0x0004
|
||||
#define PCN_EXTCTL2_MCCIINT 0x0008
|
||||
#define PCN_EXTCTL2_MCCINTE 0x0010
|
||||
#define PCN_EXTCTL2_MCCINT 0x0020
|
||||
#define PCN_EXTCTL2_MAPINTE 0x0040
|
||||
#define PCN_EXTCTL2_MAPINT 0x0080
|
||||
#define PCN_EXTCTL2_MREINTE 0x0100
|
||||
#define PCN_EXTCTL2_MREINT 0x0200
|
||||
#define PCN_EXTCTL2_STINTE 0x0400
|
||||
#define PCN_EXTCTL2_STINT 0x0800
|
||||
#define PCN_EXTCTL2_RXDPOLL 0x1000
|
||||
#define PCN_EXTCTL2_RDMD 0x2000
|
||||
#define PCN_EXTCTL2_RXFRTG 0x4000
|
||||
#define PCN_EXTCTL2_FASTSPNDE 0x8000
|
||||
|
||||
|
||||
/*
|
||||
* Mode (CSR15)
|
||||
*/
|
||||
#define PCN_MODE_RXD 0x0001 /* RX disable */
|
||||
#define PCN_MODE_TXD 0x0002 /* TX disable */
|
||||
#define PCN_MODE_LOOP 0x0004 /* loopback enable */
|
||||
#define PCN_MODE_TXCRCD 0x0008
|
||||
#define PCN_MODE_FORCECOLL 0x0010
|
||||
#define PCN_MODE_RETRYD 0x0020
|
||||
#define PCN_MODE_INTLOOP 0x0040
|
||||
#define PCN_MODE_PORTSEL 0x0180
|
||||
#define PCN_MODE_RXVPAD 0x2000
|
||||
#define PCN_MODE_RXNOBROAD 0x4000
|
||||
#define PCN_MODE_PROMISC 0x8000
|
||||
|
||||
/* Settings for PCN_MODE_PORTSEL when ASEL (BCR2[1]) is 0 */
|
||||
#define PCN_PORT_AUI 0x0000
|
||||
#define PCN_PORT_10BASET 0x0080
|
||||
#define PCN_PORT_GPSI 0x0100
|
||||
#define PCN_PORT_MII 0x0180
|
||||
|
||||
/*
|
||||
* Chip ID values.
|
||||
*/
|
||||
/* CSR88-89: Chip ID masks */
|
||||
#define AMD_MASK 0x003
|
||||
#define PART_MASK 0xffff
|
||||
#define Am79C971 0x2623
|
||||
#define Am79C972 0x2624
|
||||
#define Am79C973 0x2625
|
||||
#define Am79C978 0x2626
|
||||
#define Am79C975 0x2627
|
||||
#define Am79C976 0x2628
|
||||
|
||||
/*
|
||||
* Advanced feature control (CSR122)
|
||||
*/
|
||||
#define PCN_AFC_RXALIGN 0x0001
|
||||
|
||||
/*
|
||||
* BCR (bus control) registers
|
||||
*/
|
||||
#define PCN_BCR_MMRA 0x00 /* Master Mode Read Active */
|
||||
#define PCN_BCR_MMW 0x01 /* Master Mode Write Active */
|
||||
#define PCN_BCR_MISCCFG 0x02
|
||||
#define PCN_BCR_LED0 0x04
|
||||
#define PCN_BCR_LED1 0x05
|
||||
#define PCN_BCR_LED2 0x06
|
||||
#define PCN_BCR_LED3 0x07
|
||||
#define PCN_BCR_DUPLEX 0x09
|
||||
#define PCN_BCR_BUSCTL 0x12
|
||||
#define PCN_BCR_EECTL 0x13
|
||||
#define PCN_BCR_SSTYLE 0x14
|
||||
#define PCN_BCR_PCILAT 0x16
|
||||
#define PCN_BCR_PCISUBVENID 0x17
|
||||
#define PCN_BCR_PCISUBSYSID 0x18
|
||||
#define PCN_BCR_SRAMSIZE 0x19
|
||||
#define PCN_BCR_SRAMBOUND 0x1A
|
||||
#define PCN_BCR_SRAMCTL 0x1B
|
||||
#define PCN_BCR_MIICTL 0x20
|
||||
#define PCN_BCR_MIIADDR 0x21
|
||||
#define PCN_BCR_MIIDATA 0x22
|
||||
#define PCN_BCR_PCIVENID 0x23
|
||||
#define PCN_BCR_PCIPCAP 0x24
|
||||
#define PCN_BCR_DATA0 0x25
|
||||
#define PCN_BCR_DATA1 0x26
|
||||
#define PCN_BCR_DATA2 0x27
|
||||
#define PCN_BCR_DATA3 0x28
|
||||
#define PCN_BCR_DATA4 0x29
|
||||
#define PCN_BCR_DATA5 0x2A
|
||||
#define PCN_BCR_DATA6 0x2B
|
||||
#define PCN_BCR_DATA7 0x2C
|
||||
#define PCN_BCR_ONNOWPAT0 0x2D
|
||||
#define PCN_BCR_ONNOWPAT1 0x2E
|
||||
#define PCN_BCR_ONNOWPAT2 0x2F
|
||||
#define PCN_BCR_PHYSEL 0x31
|
||||
|
||||
/*
|
||||
* Miscellaneous Configuration (BCR2)
|
||||
*/
|
||||
#define PCN_MISC_TMAULOOP 1<<14 /* T-MAU Loopback packet enable. */
|
||||
#define PCN_MISC_LEDPE 1<<12 /* LED Program Enable */
|
||||
#define PCN_MISC_APROMWE 1<<8 /* Address PROM Write Enable */
|
||||
#define PCN_MISC_INTLEVEL 1<<7 /* Interrupt level */
|
||||
#define PCN_MISC_EADISEL 1<<3 /* EADI Select */
|
||||
#define PCN_MISC_AWAKE 1<<2 /* Power saving mode select */
|
||||
#define PCN_MISC_ASEL 1<<1 /* Auto Select */
|
||||
#define PCN_MISC_XMAUSEL 1<<0 /* Reserved. */
|
||||
|
||||
/*
|
||||
* Full duplex control (BCR9)
|
||||
*/
|
||||
#define PCN_DUPLEX_FDEN 0x0001 /* Full-duplex enable */
|
||||
#define PCN_DUPLEX_AUI 0x0002 /* AUI full-duplex */
|
||||
#define PCN_DUPLEX_FDRPAD 0x0004 /* Full-duplex runt pkt accept dis. */
|
||||
|
||||
/*
|
||||
* Burst and bus control register (BCR18)
|
||||
*/
|
||||
#define PCN_BUSCTL_BWRITE 0x0020
|
||||
#define PCN_BUSCTL_BREAD 0x0040
|
||||
#define PCN_BUSCTL_DWIO 0x0080
|
||||
#define PCN_BUSCTL_EXTREQ 0x0100
|
||||
#define PCN_BUSCTL_MEMCMD 0x0200
|
||||
#define PCN_BUSCTL_NOUFLOW 0x0800
|
||||
#define PCN_BUSCTL_ROMTMG 0xF000
|
||||
|
||||
/*
|
||||
* EEPROM control (BCR19)
|
||||
*/
|
||||
#define PCN_EECTL_EDATA 0x0001
|
||||
#define PCN_EECTL_ECLK 0x0002
|
||||
#define PCN_EECTL_EECS 0x0004
|
||||
#define PCN_EECTL_EEN 0x0100
|
||||
#define PCN_EECTL_EEDET 0x2000
|
||||
#define PCN_EECTL_PREAD 0x4000
|
||||
#define PCN_EECTL_PVALID 0x8000
|
||||
|
||||
/*
|
||||
* Software style (BCR20)
|
||||
*/
|
||||
#define PCN_SSTYLE_APERREN 0x0400 /* advanced parity error checking */
|
||||
#define PCN_SSTYLE_SSIZE32 0x0100
|
||||
#define PCN_SSTYLE_SWSTYLE 0x00FF
|
||||
|
||||
#define PCN_SWSTYLE_LANCE 0x0000
|
||||
#define PCN_SWSTYLE_PCNETPCI 0x0102
|
||||
#define PCN_SWSTYLE_PCNETPCI_BURST 0x0103
|
||||
|
||||
/*
|
||||
* MII control and status (BCR32)
|
||||
*/
|
||||
#define PCN_MIICTL_MIILP 0x0002 /* MII internal loopback */
|
||||
#define PCN_MIICTL_XPHYSP 0x0008 /* external PHY speed */
|
||||
#define PCN_MIICTL_XPHYFD 0x0010 /* external PHY full duplex */
|
||||
#define PCN_MIICTL_XPHYANE 0x0020 /* external phy auto-neg enable */
|
||||
#define PCN_MIICTL_XPHYRST 0x0040 /* external PHY reset */
|
||||
#define PCN_MIICTL_DANAS 0x0080 /* disable auto-neg auto-setup */
|
||||
#define PCN_MIICTL_APDW 0x0700 /* auto-poll dwell time */
|
||||
#define PCN_MIICTL_APEP 0x0100 /* auto-poll external PHY */
|
||||
#define PCN_MIICTL_FMDC 0x3000 /* data clock speed */
|
||||
#define PCN_MIICTL_MIIPD 0x4000 /* PHY detect */
|
||||
#define PCN_MIICTL_ANTST 0x8000 /* Manufacturing test */
|
||||
|
||||
/*
|
||||
* MII address register (BCR33)
|
||||
*/
|
||||
#define PCN_MIIADDR_REGAD 0x001F
|
||||
#define PCN_MIIADDR_PHYAD 0x03E0
|
||||
|
||||
/* addresses of internal PHYs */
|
||||
#define PCN_PHYAD_100BTX 30
|
||||
#define PCN_PHYAD_10BT 31
|
||||
|
||||
/*
|
||||
* MII data register (BCR34)
|
||||
*/
|
||||
#define PCN_MIIDATA_MIIMD 0xFFFF
|
||||
|
||||
/*
|
||||
* PHY selection (BCR49) (HomePNA NIC only)
|
||||
*/
|
||||
#define PCN_PHYSEL_PHYSEL 0x0003
|
||||
#define PCN_PHYSEL_DEFAULT 0x0300
|
||||
#define PCN_PHYSEL_PCNET 0x8000
|
||||
|
||||
#define PCN_PHY_10BT 0x0000
|
||||
#define PCN_PHY_HOMEPNA 0x0001
|
||||
#define PCN_PHY_EXTERNAL 0x0002
|
||||
|
||||
struct pcn_rx_desc {
|
||||
u_int16_t pcn_rxlen;
|
||||
u_int16_t pcn_rsvd0;
|
||||
u_int16_t pcn_bufsz;
|
||||
u_int16_t pcn_rxstat;
|
||||
u_int32_t pcn_rbaddr;
|
||||
u_int32_t pcn_uspace;
|
||||
};
|
||||
|
||||
#define PCN_RXSTAT_BPE 0x0080 /* bus parity error */
|
||||
#define PCN_RXSTAT_ENP 0x0100 /* end of packet */
|
||||
#define PCN_RXSTAT_STP 0x0200 /* start of packet */
|
||||
#define PCN_RXSTAT_BUFF 0x0400 /* buffer error */
|
||||
#define PCN_RXSTAT_CRC 0x0800 /* CRC error */
|
||||
#define PCN_RXSTAT_OFLOW 0x1000 /* rx overrun */
|
||||
#define PCN_RXSTAT_FRAM 0x2000 /* framing error */
|
||||
#define PCN_RXSTAT_ERR 0x4000 /* error summary */
|
||||
#define PCN_RXSTAT_OWN 0x8000
|
||||
|
||||
#define PCN_RXLEN_MBO 0xF000
|
||||
#define PCN_RXLEN_BUFSZ 0x0FFF
|
||||
|
||||
#define PCN_OWN_RXDESC(x) (((x)->pcn_rxstat & PCN_RXSTAT_OWN) == 0)
|
||||
|
||||
struct pcn_tx_desc {
|
||||
u_int32_t pcn_txstat;
|
||||
u_int32_t pcn_txctl;
|
||||
u_int32_t pcn_tbaddr;
|
||||
u_int32_t pcn_uspace;
|
||||
};
|
||||
|
||||
#define PCN_TXSTAT_TRC 0x0000000F /* transmit retries */
|
||||
#define PCN_TXSTAT_RTRY 0x04000000 /* retry */
|
||||
#define PCN_TXSTAT_LCAR 0x08000000 /* lost carrier */
|
||||
#define PCN_TXSTAT_LCOL 0x10000000 /* late collision */
|
||||
#define PCN_TXSTAT_EXDEF 0x20000000 /* excessive deferrals */
|
||||
#define PCN_TXSTAT_UFLOW 0x40000000 /* transmit underrun */
|
||||
#define PCN_TXSTAT_BUFF 0x80000000 /* buffer error */
|
||||
|
||||
#define PCN_TXCTL_OWN 0x80000000
|
||||
#define PCN_TXCTL_ERR 0x40000000 /* error summary */
|
||||
#define PCN_TXCTL_ADD_FCS 0x20000000 /* add FCS to pkt */
|
||||
#define PCN_TXCTL_MORE_LTINT 0x10000000
|
||||
#define PCN_TXCTL_ONE 0x08000000
|
||||
#define PCN_TXCTL_DEF 0x04000000
|
||||
#define PCN_TXCTL_STP 0x02000000
|
||||
#define PCN_TXCTL_ENP 0x01000000
|
||||
#define PCN_TXCTL_BPE 0x00800000
|
||||
#define PCN_TXCTL_MBO 0x0000F000
|
||||
#define PCN_TXCTL_BUFSZ 0x00000FFF
|
||||
|
||||
#define PCN_OWN_TXDESC(x) (((x)->pcn_txctl & PCN_TXCTL_OWN) == 0)
|
||||
|
||||
#define PCN_RX_LIST_CNT 64
|
||||
#define PCN_TX_LIST_CNT 256
|
||||
|
||||
struct pcn_list_data {
|
||||
struct pcn_rx_desc pcn_rx_list[PCN_RX_LIST_CNT];
|
||||
struct pcn_tx_desc pcn_tx_list[PCN_TX_LIST_CNT];
|
||||
};
|
||||
|
||||
struct pcn_ring_data {
|
||||
struct mbuf *pcn_rx_chain[PCN_RX_LIST_CNT];
|
||||
struct mbuf *pcn_tx_chain[PCN_TX_LIST_CNT];
|
||||
int pcn_rx_prod;
|
||||
int pcn_tx_prod;
|
||||
int pcn_tx_cons;
|
||||
int pcn_tx_cnt;
|
||||
};
|
||||
|
||||
/*
|
||||
* AMD PCI vendor ID.
|
||||
*/
|
||||
#define PCN_VENDORID 0x1022
|
||||
|
||||
/*
|
||||
* AMD PCnet/PCI device IDs
|
||||
*/
|
||||
#define PCN_DEVICEID_PCNET 0x2000
|
||||
#define PCN_DEVICEID_HOME 0x2001
|
||||
|
||||
struct pcn_type {
|
||||
u_int16_t pcn_vid;
|
||||
u_int16_t pcn_did;
|
||||
const char *pcn_name;
|
||||
};
|
||||
|
||||
struct pcn_softc {
|
||||
struct ifnet *pcn_ifp;
|
||||
bus_space_handle_t pcn_bhandle;
|
||||
bus_space_tag_t pcn_btag;
|
||||
struct resource *pcn_res;
|
||||
struct resource *pcn_irq;
|
||||
void *pcn_intrhand;
|
||||
device_t pcn_miibus;
|
||||
u_int8_t pcn_link;
|
||||
int8_t pcn_extphyaddr;
|
||||
int8_t pcn_inst_10bt;
|
||||
int pcn_if_flags;
|
||||
int pcn_type;
|
||||
struct pcn_list_data *pcn_ldata;
|
||||
struct pcn_ring_data pcn_cdata;
|
||||
struct callout pcn_stat_callout;
|
||||
struct mtx pcn_mtx;
|
||||
int pcn_timer;
|
||||
};
|
||||
|
||||
#define PCN_LOCK(_sc) mtx_lock(&(_sc)->pcn_mtx)
|
||||
#define PCN_UNLOCK(_sc) mtx_unlock(&(_sc)->pcn_mtx)
|
||||
#define PCN_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->pcn_mtx, MA_OWNED)
|
||||
|
||||
/*
|
||||
* register space access macros
|
||||
*/
|
||||
#define CSR_WRITE_4(sc, reg, val) \
|
||||
bus_space_write_4(sc->pcn_btag, sc->pcn_bhandle, reg, val)
|
||||
|
||||
#define CSR_READ_4(sc, reg) \
|
||||
bus_space_read_4(sc->pcn_btag, sc->pcn_bhandle, reg)
|
||||
|
||||
#define CSR_WRITE_2(sc, reg, val) \
|
||||
bus_space_write_2(sc->pcn_btag, sc->pcn_bhandle, reg, val)
|
||||
|
||||
#define CSR_READ_2(sc, reg) \
|
||||
bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg)
|
||||
|
||||
#define PCN_TIMEOUT 1000
|
||||
#define ETHER_ALIGN 2
|
||||
#define PCN_RXLEN 1536
|
||||
#define PCN_MIN_FRAMELEN 60
|
||||
#define PCN_INC(x, y) (x) = (x + 1) % y
|
||||
/*
|
||||
* PCI low memory base and low I/O base register, and
|
||||
* other PCI registers.
|
||||
*/
|
||||
|
||||
#define PCN_PCI_VENDOR_ID 0x00
|
||||
#define PCN_PCI_DEVICE_ID 0x02
|
||||
#define PCN_PCI_COMMAND 0x04
|
||||
#define PCN_PCI_STATUS 0x06
|
||||
#define PCN_PCI_REVID 0x08
|
||||
#define PCN_PCI_CLASSCODE 0x09
|
||||
#define PCN_PCI_CACHELEN 0x0C
|
||||
#define PCN_PCI_LATENCY_TIMER 0x0D
|
||||
#define PCN_PCI_HEADER_TYPE 0x0E
|
||||
#define PCN_PCI_LOIO 0x10
|
||||
#define PCN_PCI_LOMEM 0x14
|
||||
#define PCN_PCI_BIOSROM 0x30
|
||||
#define PCN_PCI_INTLINE 0x3C
|
||||
#define PCN_PCI_INTPIN 0x3D
|
||||
#define PCN_PCI_MINGNT 0x3E
|
||||
#define PCN_PCI_MINLAT 0x3F
|
||||
#define PCN_PCI_RESETOPT 0x48
|
||||
#define PCN_PCI_EEPROM_DATA 0x4C
|
||||
|
||||
/* power management registers */
|
||||
#define PCN_PCI_CAPID 0x50 /* 8 bits */
|
||||
#define PCN_PCI_NEXTPTR 0x51 /* 8 bits */
|
||||
#define PCN_PCI_PWRMGMTCAP 0x52 /* 16 bits */
|
||||
#define PCN_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
|
||||
|
||||
#define PCN_PSTATE_MASK 0x0003
|
||||
#define PCN_PSTATE_D0 0x0000
|
||||
#define PCN_PSTATE_D1 0x0001
|
||||
#define PCN_PSTATE_D2 0x0002
|
||||
#define PCN_PSTATE_D3 0x0003
|
||||
#define PCN_PME_EN 0x0010
|
||||
#define PCN_PME_STATUS 0x8000
|
||||
@ -178,7 +178,7 @@ model BROADCOM2 BCM5722 0x002d BCM5722 1000BASE-T media interface
|
||||
model BROADCOM2 BCM5784 0x003a BCM5784 10/100/1000baseT PHY
|
||||
model BROADCOM2 BCM5709C 0x003c BCM5709 10/100/1000baseT PHY
|
||||
model BROADCOM2 BCM5761 0x003d BCM5761 10/100/1000baseT PHY
|
||||
model BROADCOM2 BCM5709S 0x003f BCM5709S 1000/2500baseSX PHY
|
||||
model BROADCOM2 BCM5709S 0x003f BCM5709S/5720S 1000/2500baseSX PHY
|
||||
model BROADCOM3 BCM57780 0x0019 BCM57780 1000BASE-T media interface
|
||||
model BROADCOM3 BCM5717C 0x0020 BCM5717C 1000BASE-T media interface
|
||||
model BROADCOM3 BCM5719C 0x0022 BCM5719C 1000BASE-T media interface
|
||||
|
||||
Loading…
Reference in New Issue
Block a user