From 471bc81038546316a061d3e766b0c4615e66b21e Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Sat, 12 Dec 2015 00:11:30 -0600 Subject: [PATCH] intel_extreme: Fix LVDS pll DAC timing --- src/add-ons/accelerants/intel_extreme/pll.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/add-ons/accelerants/intel_extreme/pll.cpp b/src/add-ons/accelerants/intel_extreme/pll.cpp index 5d159015ba..f6126d72ad 100644 --- a/src/add-ons/accelerants/intel_extreme/pll.cpp +++ b/src/add-ons/accelerants/intel_extreme/pll.cpp @@ -215,13 +215,13 @@ compute_pll_divisors(display_mode* current, pll_divisors* divisors, if (requestedPixelClock > 112.999 || (read32(INTEL_DIGITAL_LVDS_PORT) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) { + // fast DAC timing via 2 channels + divisors->post2 = limits.max.post2; + divisors->post2_high = limits.max.post2_high; + } else { // slow DAC timing divisors->post2 = limits.min.post2; divisors->post2_high = limits.min.post2_high; - } else { - // fast DAC timing - divisors->post2 = limits.max.post2; - divisors->post2_high = limits.max.post2_high; } } else { if (current->timing.pixel_clock < limits.min_post2_frequency) {