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intel_extreme: Fix LVDS pll DAC timing

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This commit is contained in:
Alexander von Gluck IV 2015-12-12 00:11:30 -06:00
parent 5202e45a52
commit 471bc81038
1 changed files with 4 additions and 4 deletions
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8
src/add-ons/accelerants/intel_extreme/pll.cpp
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@ -215,13 +215,13 @@ compute_pll_divisors(display_mode* current, pll_divisors* divisors,
if (requestedPixelClock > 112.999
|| (read32(INTEL_DIGITAL_LVDS_PORT) & LVDS_CLKB_POWER_MASK)
== LVDS_CLKB_POWER_UP) {
// fast DAC timing via 2 channels
divisors->post2 = limits.max.post2;
divisors->post2_high = limits.max.post2_high;
} else {
// slow DAC timing
divisors->post2 = limits.min.post2;
divisors->post2_high = limits.min.post2_high;
} else {
// fast DAC timing
divisors->post2 = limits.max.post2;
divisors->post2_high = limits.max.post2_high;
}
} else {
if (current->timing.pixel_clock < limits.min_post2_frequency) {