freebsd_network: Clean up and break PCI methods out of bus.cpp.
This commit is contained in:
Augustin Cavalier
parent
ccb7655078
commit
462fb495fa
@ -41,6 +41,7 @@ KernelStaticLibrary libfreebsd_network.a :
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mbuf.c
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mii.c
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mutex.c
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pci.cpp
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priv.cpp
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smp.c
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subr_autoconf.cpp
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@ -9,11 +9,11 @@ extern "C" {
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#include "device.h"
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}
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#include <stdlib.h>
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#include <algorithm>
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#include <cstdlib>
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#include <PCI_x86.h>
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#include <arch/cpu.h>
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#include <int.h>
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extern "C" {
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#include <compat/dev/pci/pcireg.h>
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@ -25,11 +25,6 @@ extern "C" {
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#include <compat/sys/bus.h>
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}
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// private kernel header to get B_NO_HANDLED_INFO
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#include <int.h>
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#include <PCI_x86.h>
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//#define DEBUG_BUS_SPACE_RW
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#ifdef DEBUG_BUS_SPACE_RW
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@ -38,13 +33,6 @@ extern "C" {
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# define TRACE_BUS_SPACE_RW(x)
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#endif
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define TRACE_PCI(dev, format, args...) device_printf(dev, format , ##args)
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#else
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# define TRACE_PCI(dev, format, args...) do { } while (0)
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#endif
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struct internal_intr {
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device_t dev;
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@ -580,450 +568,3 @@ bus_enumerate_hinted_children(device_t bus)
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UNIMPLEMENTED();
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#endif
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}
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// #pragma mark - PCI functions
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uint32_t
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pci_read_config(device_t dev, int offset, int size)
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{
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pci_info *info = &((struct root_device_softc *)dev->root->softc)->pci_info;
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uint32_t value = gPci->read_pci_config(info->bus, info->device,
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info->function, offset, size);
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TRACE_PCI(dev, "pci_read_config(%i, %i) = 0x%x\n", offset, size, value);
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return value;
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}
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void
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pci_write_config(device_t dev, int offset, uint32_t value, int size)
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{
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pci_info *info = &((struct root_device_softc *)dev->root->softc)->pci_info;
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TRACE_PCI(dev, "pci_write_config(%i, 0x%x, %i)\n", offset, value, size);
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gPci->write_pci_config(info->bus, info->device, info->function, offset,
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size, value);
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}
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uint16_t
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pci_get_vendor(device_t dev)
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{
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return pci_read_config(dev, PCI_vendor_id, 2);
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}
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uint16_t
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pci_get_device(device_t dev)
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{
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return pci_read_config(dev, PCI_device_id, 2);
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}
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uint16_t
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pci_get_subvendor(device_t dev)
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{
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return pci_read_config(dev, PCI_subsystem_vendor_id, 2);
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}
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uint16_t
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pci_get_subdevice(device_t dev)
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{
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return pci_read_config(dev, PCI_subsystem_id, 2);
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}
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uint8_t
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pci_get_revid(device_t dev)
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{
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return pci_read_config(dev, PCI_revision, 1);
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}
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uint32_t
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pci_get_domain(device_t dev)
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{
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return 0;
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}
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uint32_t
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pci_get_devid(device_t dev)
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{
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return pci_read_config(dev, PCI_device_id, 2) << 16 |
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pci_read_config(dev, PCI_vendor_id, 2);
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}
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uint8_t
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pci_get_cachelnsz(device_t dev)
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{
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return pci_read_config(dev, PCI_line_size, 1);
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}
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uint8_t *
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pci_get_ether(device_t dev)
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{
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/* used in if_dc to get the MAC from CardBus CIS for Xircom card */
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return NULL; /* NULL is handled in the caller correctly */
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}
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uint8_t
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pci_get_bus(device_t dev)
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{
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pci_info *info
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= &((struct root_device_softc *)dev->root->softc)->pci_info;
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return info->bus;
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}
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uint8_t
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pci_get_slot(device_t dev)
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{
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pci_info *info
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= &((struct root_device_softc *)dev->root->softc)->pci_info;
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return info->device;
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}
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uint8_t
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pci_get_function(device_t dev)
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{
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pci_info *info
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= &((struct root_device_softc *)dev->root->softc)->pci_info;
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return info->function;
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}
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device_t
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pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
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{
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// We don't support that yet - if we want to support the multi port
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// feature of the Broadcom BCM 570x driver, we would have to change
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// that.
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return NULL;
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}
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static void
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pci_set_command_bit(device_t dev, uint16_t bit)
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{
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uint16_t command = pci_read_config(dev, PCI_command, 2);
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pci_write_config(dev, PCI_command, command | bit, 2);
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}
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int
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pci_enable_busmaster(device_t dev)
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{
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pci_set_command_bit(dev, PCI_command_master);
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return 0;
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}
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int
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pci_enable_io(device_t dev, int space)
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{
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/* adapted from FreeBSD's pci_enable_io_method */
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int bit = 0;
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switch (space) {
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case SYS_RES_IOPORT:
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bit = PCI_command_io;
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break;
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case SYS_RES_MEMORY:
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bit = PCI_command_memory;
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break;
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default:
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return EINVAL;
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}
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pci_set_command_bit(dev, bit);
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if (pci_read_config(dev, PCI_command, 2) & bit)
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return 0;
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device_printf(dev, "pci_enable_io(%d) failed.\n", space);
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return ENXIO;
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}
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int
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pci_find_cap(device_t dev, int capability, int *capreg)
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{
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return pci_find_extcap(dev, capability, capreg);
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}
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int
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pci_find_extcap(device_t child, int capability, int *_capabilityRegister)
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{
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uint8 capabilityPointer;
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uint8 headerType;
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uint16 status;
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status = pci_read_config(child, PCIR_STATUS, 2);
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if ((status & PCIM_STATUS_CAPPRESENT) == 0)
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return ENXIO;
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headerType = pci_read_config(child, PCI_header_type, 1);
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switch (headerType & PCIM_HDRTYPE) {
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case 0:
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case 1:
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capabilityPointer = PCIR_CAP_PTR;
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break;
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case 2:
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capabilityPointer = PCIR_CAP_PTR_2;
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break;
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default:
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return ENXIO;
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}
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capabilityPointer = pci_read_config(child, capabilityPointer, 1);
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while (capabilityPointer != 0) {
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if (pci_read_config(child, capabilityPointer + PCICAP_ID, 1)
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== capability) {
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if (_capabilityRegister != NULL)
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*_capabilityRegister = capabilityPointer;
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return 0;
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}
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capabilityPointer = pci_read_config(child,
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capabilityPointer + PCICAP_NEXTPTR, 1);
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}
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return ENOENT;
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}
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int
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pci_msi_count(device_t dev)
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{
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pci_info *info;
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if (gPCIx86 == NULL)
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return 0;
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info = &((struct root_device_softc *)dev->root->softc)->pci_info;
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return gPCIx86->get_msi_count(info->bus, info->device, info->function);
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}
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int
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pci_alloc_msi(device_t dev, int *count)
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{
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pci_info *info;
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uint8 startVector = 0;
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if (gPCIx86 == NULL)
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return ENODEV;
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info = &((struct root_device_softc *)dev->root->softc)->pci_info;
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if (gPCIx86->configure_msi(info->bus, info->device, info->function, *count,
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&startVector) != B_OK) {
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return ENODEV;
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}
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((struct root_device_softc *)dev->root->softc)->is_msi = true;
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info->u.h0.interrupt_line = startVector;
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return EOK;
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}
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int
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pci_release_msi(device_t dev)
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{
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pci_info *info;
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if (gPCIx86 == NULL)
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return ENODEV;
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info = &((struct root_device_softc *)dev->root->softc)->pci_info;
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gPCIx86->unconfigure_msi(info->bus, info->device, info->function);
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((struct root_device_softc *)dev->root->softc)->is_msi = false;
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((struct root_device_softc *)dev->root->softc)->is_msix = false;
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return EOK;
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}
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int
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pci_msix_table_bar(device_t dev)
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{
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pci_info *info = &((struct root_device_softc *)dev->root->softc)->pci_info;
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uint8 capability_offset;
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if (gPci->find_pci_capability(info->bus, info->device, info->function,
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PCI_cap_id_msix, &capability_offset) != B_OK)
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return -1;
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uint32 table_value = gPci->read_pci_config(info->bus, info->device, info->function,
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capability_offset + PCI_msix_table, 4);
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uint32 bar = table_value & PCI_msix_bir_mask;
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return PCIR_BAR(bar);
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}
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int
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pci_msix_count(device_t dev)
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{
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pci_info *info;
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if (gPCIx86 == NULL)
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return 0;
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info = &((struct root_device_softc *)dev->root->softc)->pci_info;
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return gPCIx86->get_msix_count(info->bus, info->device, info->function);
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}
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int
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pci_alloc_msix(device_t dev, int *count)
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{
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pci_info *info;
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uint8 startVector = 0;
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if (gPCIx86 == NULL)
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return ENODEV;
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info = &((struct root_device_softc *)dev->root->softc)->pci_info;
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if (gPCIx86->configure_msix(info->bus, info->device, info->function, *count,
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&startVector) != B_OK) {
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return ENODEV;
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}
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((struct root_device_softc *)dev->root->softc)->is_msix = true;
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info->u.h0.interrupt_line = startVector;
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return EOK;
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}
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int
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pci_get_max_read_req(device_t dev)
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{
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int cap;
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uint16_t val;
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if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) != 0)
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return (0);
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val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
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val &= PCIM_EXP_CTL_MAX_READ_REQUEST;
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val >>= 12;
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return (1 << (val + 7));
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}
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int
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pci_set_max_read_req(device_t dev, int size)
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{
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int cap;
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uint16_t val;
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if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) != 0)
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return (0);
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if (size < 128)
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size = 128;
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if (size > 4096)
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size = 4096;
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size = (1 << (fls(size) - 1));
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val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
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val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
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val |= (fls(size) - 8) << 12;
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pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
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return (size);
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}
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int
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pci_get_powerstate(device_t dev)
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{
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int capabilityRegister;
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uint16 status;
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int powerState = PCI_POWERSTATE_D0;
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if (pci_find_extcap(dev, PCIY_PMG, &capabilityRegister) != EOK)
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return powerState;
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status = pci_read_config(dev, capabilityRegister + PCIR_POWER_STATUS, 2);
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switch (status & PCI_pm_mask) {
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case PCI_pm_state_d0:
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break;
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case PCI_pm_state_d1:
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powerState = PCI_POWERSTATE_D1;
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break;
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case PCI_pm_state_d2:
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powerState = PCI_POWERSTATE_D2;
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break;
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case PCI_pm_state_d3:
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powerState = PCI_POWERSTATE_D3;
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break;
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default:
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powerState = PCI_POWERSTATE_UNKNOWN;
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break;
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}
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TRACE_PCI(dev, "%s: D%i\n", __func__, powerState);
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return powerState;
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}
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int
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pci_set_powerstate(device_t dev, int newPowerState)
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{
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int capabilityRegister;
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int oldPowerState;
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uint8 currentPowerManagementStatus;
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uint8 newPowerManagementStatus;
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uint16 powerManagementCapabilities;
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bigtime_t stateTransitionDelayInUs = 0;
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if (pci_find_extcap(dev, PCIY_PMG, &capabilityRegister) != EOK)
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return EOPNOTSUPP;
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oldPowerState = pci_get_powerstate(dev);
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if (oldPowerState == newPowerState)
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return EOK;
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switch (std::max(oldPowerState, newPowerState)) {
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case PCI_POWERSTATE_D2:
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stateTransitionDelayInUs = 200;
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break;
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case PCI_POWERSTATE_D3:
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stateTransitionDelayInUs = 10000;
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break;
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}
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currentPowerManagementStatus = pci_read_config(dev, capabilityRegister
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+ PCIR_POWER_STATUS, 2);
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newPowerManagementStatus = currentPowerManagementStatus & ~PCI_pm_mask;
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powerManagementCapabilities = pci_read_config(dev, capabilityRegister
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+ PCIR_POWER_CAP, 2);
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switch (newPowerState) {
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case PCI_POWERSTATE_D0:
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newPowerManagementStatus |= PCIM_PSTAT_D0;
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break;
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case PCI_POWERSTATE_D1:
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if ((powerManagementCapabilities & PCI_pm_d1supp) == 0)
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return EOPNOTSUPP;
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newPowerManagementStatus |= PCIM_PSTAT_D1;
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break;
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case PCI_POWERSTATE_D2:
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if ((powerManagementCapabilities & PCI_pm_d2supp) == 0)
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return EOPNOTSUPP;
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newPowerManagementStatus |= PCIM_PSTAT_D2;
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break;
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case PCI_POWERSTATE_D3:
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newPowerManagementStatus |= PCIM_PSTAT_D3;
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break;
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default:
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return EINVAL;
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}
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TRACE_PCI(dev, "%s: D%i -> D%i\n", __func__, oldPowerState, newPowerState);
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pci_write_config(dev, capabilityRegister + PCIR_POWER_STATUS,
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newPowerManagementStatus, 2);
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if (stateTransitionDelayInUs != 0)
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snooze(stateTransitionDelayInUs);
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return EOK;
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}
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466
src/libs/compat/freebsd_network/pci.cpp
Normal file
466
src/libs/compat/freebsd_network/pci.cpp
Normal file
@ -0,0 +1,466 @@
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/*
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* Copyright 2022, Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*/
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extern "C" {
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#include "device.h"
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#include <compat/machine/resource.h>
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#include <compat/dev/pci/pcireg.h>
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#include <compat/dev/pci/pcivar.h>
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}
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#include <PCI.h>
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#include <PCI_x86.h>
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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||||
# define TRACE_PCI(dev, format, args...) device_printf(dev, format , ##args)
|
||||
#else
|
||||
# define TRACE_PCI(dev, format, args...) do { } while (0)
|
||||
#endif
|
||||
|
||||
|
||||
uint32_t
|
||||
pci_read_config(device_t dev, int offset, int size)
|
||||
{
|
||||
pci_info *info = &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
|
||||
uint32_t value = gPci->read_pci_config(info->bus, info->device,
|
||||
info->function, offset, size);
|
||||
TRACE_PCI(dev, "pci_read_config(%i, %i) = 0x%x\n", offset, size, value);
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
pci_write_config(device_t dev, int offset, uint32_t value, int size)
|
||||
{
|
||||
pci_info *info = &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
|
||||
TRACE_PCI(dev, "pci_write_config(%i, 0x%x, %i)\n", offset, value, size);
|
||||
|
||||
gPci->write_pci_config(info->bus, info->device, info->function, offset,
|
||||
size, value);
|
||||
}
|
||||
|
||||
|
||||
uint16_t
|
||||
pci_get_vendor(device_t dev)
|
||||
{
|
||||
return pci_read_config(dev, PCI_vendor_id, 2);
|
||||
}
|
||||
|
||||
|
||||
uint16_t
|
||||
pci_get_device(device_t dev)
|
||||
{
|
||||
return pci_read_config(dev, PCI_device_id, 2);
|
||||
}
|
||||
|
||||
|
||||
uint16_t
|
||||
pci_get_subvendor(device_t dev)
|
||||
{
|
||||
return pci_read_config(dev, PCI_subsystem_vendor_id, 2);
|
||||
}
|
||||
|
||||
|
||||
uint16_t
|
||||
pci_get_subdevice(device_t dev)
|
||||
{
|
||||
return pci_read_config(dev, PCI_subsystem_id, 2);
|
||||
}
|
||||
|
||||
|
||||
uint8_t
|
||||
pci_get_revid(device_t dev)
|
||||
{
|
||||
return pci_read_config(dev, PCI_revision, 1);
|
||||
}
|
||||
|
||||
|
||||
uint32_t
|
||||
pci_get_domain(device_t dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t
|
||||
pci_get_devid(device_t dev)
|
||||
{
|
||||
return pci_read_config(dev, PCI_device_id, 2) << 16 |
|
||||
pci_read_config(dev, PCI_vendor_id, 2);
|
||||
}
|
||||
|
||||
uint8_t
|
||||
pci_get_cachelnsz(device_t dev)
|
||||
{
|
||||
return pci_read_config(dev, PCI_line_size, 1);
|
||||
}
|
||||
|
||||
uint8_t *
|
||||
pci_get_ether(device_t dev)
|
||||
{
|
||||
/* used in if_dc to get the MAC from CardBus CIS for Xircom card */
|
||||
return NULL; /* NULL is handled in the caller correctly */
|
||||
}
|
||||
|
||||
uint8_t
|
||||
pci_get_bus(device_t dev)
|
||||
{
|
||||
pci_info *info
|
||||
= &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
return info->bus;
|
||||
}
|
||||
|
||||
|
||||
uint8_t
|
||||
pci_get_slot(device_t dev)
|
||||
{
|
||||
pci_info *info
|
||||
= &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
return info->device;
|
||||
}
|
||||
|
||||
|
||||
uint8_t
|
||||
pci_get_function(device_t dev)
|
||||
{
|
||||
pci_info *info
|
||||
= &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
return info->function;
|
||||
}
|
||||
|
||||
|
||||
device_t
|
||||
pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
|
||||
{
|
||||
// We don't support that yet - if we want to support the multi port
|
||||
// feature of the Broadcom BCM 570x driver, we would have to change
|
||||
// that.
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
pci_set_command_bit(device_t dev, uint16_t bit)
|
||||
{
|
||||
uint16_t command = pci_read_config(dev, PCI_command, 2);
|
||||
pci_write_config(dev, PCI_command, command | bit, 2);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_enable_busmaster(device_t dev)
|
||||
{
|
||||
pci_set_command_bit(dev, PCI_command_master);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_enable_io(device_t dev, int space)
|
||||
{
|
||||
/* adapted from FreeBSD's pci_enable_io_method */
|
||||
int bit = 0;
|
||||
|
||||
switch (space) {
|
||||
case SYS_RES_IOPORT:
|
||||
bit = PCI_command_io;
|
||||
break;
|
||||
case SYS_RES_MEMORY:
|
||||
bit = PCI_command_memory;
|
||||
break;
|
||||
default:
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
pci_set_command_bit(dev, bit);
|
||||
if (pci_read_config(dev, PCI_command, 2) & bit)
|
||||
return 0;
|
||||
|
||||
device_printf(dev, "pci_enable_io(%d) failed.\n", space);
|
||||
|
||||
return ENXIO;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_find_cap(device_t dev, int capability, int *capreg)
|
||||
{
|
||||
return pci_find_extcap(dev, capability, capreg);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_find_extcap(device_t child, int capability, int *_capabilityRegister)
|
||||
{
|
||||
uint8 capabilityPointer;
|
||||
uint8 headerType;
|
||||
uint16 status;
|
||||
|
||||
status = pci_read_config(child, PCIR_STATUS, 2);
|
||||
if ((status & PCIM_STATUS_CAPPRESENT) == 0)
|
||||
return ENXIO;
|
||||
|
||||
headerType = pci_read_config(child, PCI_header_type, 1);
|
||||
switch (headerType & PCIM_HDRTYPE) {
|
||||
case 0:
|
||||
case 1:
|
||||
capabilityPointer = PCIR_CAP_PTR;
|
||||
break;
|
||||
case 2:
|
||||
capabilityPointer = PCIR_CAP_PTR_2;
|
||||
break;
|
||||
default:
|
||||
return ENXIO;
|
||||
}
|
||||
capabilityPointer = pci_read_config(child, capabilityPointer, 1);
|
||||
|
||||
while (capabilityPointer != 0) {
|
||||
if (pci_read_config(child, capabilityPointer + PCICAP_ID, 1)
|
||||
== capability) {
|
||||
if (_capabilityRegister != NULL)
|
||||
*_capabilityRegister = capabilityPointer;
|
||||
return 0;
|
||||
}
|
||||
capabilityPointer = pci_read_config(child,
|
||||
capabilityPointer + PCICAP_NEXTPTR, 1);
|
||||
}
|
||||
|
||||
return ENOENT;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_msi_count(device_t dev)
|
||||
{
|
||||
pci_info *info;
|
||||
if (gPCIx86 == NULL)
|
||||
return 0;
|
||||
|
||||
info = &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
return gPCIx86->get_msi_count(info->bus, info->device, info->function);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_alloc_msi(device_t dev, int *count)
|
||||
{
|
||||
pci_info *info;
|
||||
uint8 startVector = 0;
|
||||
if (gPCIx86 == NULL)
|
||||
return ENODEV;
|
||||
|
||||
info = &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
|
||||
if (gPCIx86->configure_msi(info->bus, info->device, info->function, *count,
|
||||
&startVector) != B_OK) {
|
||||
return ENODEV;
|
||||
}
|
||||
|
||||
((struct root_device_softc *)dev->root->softc)->is_msi = true;
|
||||
info->u.h0.interrupt_line = startVector;
|
||||
return EOK;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_release_msi(device_t dev)
|
||||
{
|
||||
pci_info *info;
|
||||
if (gPCIx86 == NULL)
|
||||
return ENODEV;
|
||||
|
||||
info = &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
gPCIx86->unconfigure_msi(info->bus, info->device, info->function);
|
||||
((struct root_device_softc *)dev->root->softc)->is_msi = false;
|
||||
((struct root_device_softc *)dev->root->softc)->is_msix = false;
|
||||
return EOK;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_msix_table_bar(device_t dev)
|
||||
{
|
||||
pci_info *info = &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
|
||||
uint8 capability_offset;
|
||||
if (gPci->find_pci_capability(info->bus, info->device, info->function,
|
||||
PCI_cap_id_msix, &capability_offset) != B_OK)
|
||||
return -1;
|
||||
|
||||
uint32 table_value = gPci->read_pci_config(info->bus, info->device, info->function,
|
||||
capability_offset + PCI_msix_table, 4);
|
||||
|
||||
uint32 bar = table_value & PCI_msix_bir_mask;
|
||||
return PCIR_BAR(bar);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_msix_count(device_t dev)
|
||||
{
|
||||
pci_info *info;
|
||||
if (gPCIx86 == NULL)
|
||||
return 0;
|
||||
|
||||
info = &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
return gPCIx86->get_msix_count(info->bus, info->device, info->function);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_alloc_msix(device_t dev, int *count)
|
||||
{
|
||||
pci_info *info;
|
||||
uint8 startVector = 0;
|
||||
if (gPCIx86 == NULL)
|
||||
return ENODEV;
|
||||
|
||||
info = &((struct root_device_softc *)dev->root->softc)->pci_info;
|
||||
|
||||
if (gPCIx86->configure_msix(info->bus, info->device, info->function, *count,
|
||||
&startVector) != B_OK) {
|
||||
return ENODEV;
|
||||
}
|
||||
|
||||
((struct root_device_softc *)dev->root->softc)->is_msix = true;
|
||||
info->u.h0.interrupt_line = startVector;
|
||||
return EOK;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_get_max_read_req(device_t dev)
|
||||
{
|
||||
int cap;
|
||||
uint16_t val;
|
||||
|
||||
if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) != 0)
|
||||
return (0);
|
||||
val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
|
||||
val &= PCIM_EXP_CTL_MAX_READ_REQUEST;
|
||||
val >>= 12;
|
||||
return (1 << (val + 7));
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_set_max_read_req(device_t dev, int size)
|
||||
{
|
||||
int cap;
|
||||
uint16_t val;
|
||||
|
||||
if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) != 0)
|
||||
return (0);
|
||||
if (size < 128)
|
||||
size = 128;
|
||||
if (size > 4096)
|
||||
size = 4096;
|
||||
size = (1 << (fls(size) - 1));
|
||||
val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
|
||||
val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
|
||||
val |= (fls(size) - 8) << 12;
|
||||
pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
|
||||
return (size);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_get_powerstate(device_t dev)
|
||||
{
|
||||
int capabilityRegister;
|
||||
uint16 status;
|
||||
int powerState = PCI_POWERSTATE_D0;
|
||||
|
||||
if (pci_find_extcap(dev, PCIY_PMG, &capabilityRegister) != EOK)
|
||||
return powerState;
|
||||
|
||||
status = pci_read_config(dev, capabilityRegister + PCIR_POWER_STATUS, 2);
|
||||
switch (status & PCI_pm_mask) {
|
||||
case PCI_pm_state_d0:
|
||||
break;
|
||||
case PCI_pm_state_d1:
|
||||
powerState = PCI_POWERSTATE_D1;
|
||||
break;
|
||||
case PCI_pm_state_d2:
|
||||
powerState = PCI_POWERSTATE_D2;
|
||||
break;
|
||||
case PCI_pm_state_d3:
|
||||
powerState = PCI_POWERSTATE_D3;
|
||||
break;
|
||||
default:
|
||||
powerState = PCI_POWERSTATE_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
TRACE_PCI(dev, "%s: D%i\n", __func__, powerState);
|
||||
return powerState;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pci_set_powerstate(device_t dev, int newPowerState)
|
||||
{
|
||||
int capabilityRegister;
|
||||
int oldPowerState;
|
||||
uint8 currentPowerManagementStatus;
|
||||
uint8 newPowerManagementStatus;
|
||||
uint16 powerManagementCapabilities;
|
||||
bigtime_t stateTransitionDelayInUs = 0;
|
||||
|
||||
if (pci_find_extcap(dev, PCIY_PMG, &capabilityRegister) != EOK)
|
||||
return EOPNOTSUPP;
|
||||
|
||||
oldPowerState = pci_get_powerstate(dev);
|
||||
if (oldPowerState == newPowerState)
|
||||
return EOK;
|
||||
|
||||
switch (max_c(oldPowerState, newPowerState)) {
|
||||
case PCI_POWERSTATE_D2:
|
||||
stateTransitionDelayInUs = 200;
|
||||
break;
|
||||
case PCI_POWERSTATE_D3:
|
||||
stateTransitionDelayInUs = 10000;
|
||||
break;
|
||||
}
|
||||
|
||||
currentPowerManagementStatus = pci_read_config(dev, capabilityRegister
|
||||
+ PCIR_POWER_STATUS, 2);
|
||||
newPowerManagementStatus = currentPowerManagementStatus & ~PCI_pm_mask;
|
||||
powerManagementCapabilities = pci_read_config(dev, capabilityRegister
|
||||
+ PCIR_POWER_CAP, 2);
|
||||
|
||||
switch (newPowerState) {
|
||||
case PCI_POWERSTATE_D0:
|
||||
newPowerManagementStatus |= PCIM_PSTAT_D0;
|
||||
break;
|
||||
case PCI_POWERSTATE_D1:
|
||||
if ((powerManagementCapabilities & PCI_pm_d1supp) == 0)
|
||||
return EOPNOTSUPP;
|
||||
newPowerManagementStatus |= PCIM_PSTAT_D1;
|
||||
break;
|
||||
case PCI_POWERSTATE_D2:
|
||||
if ((powerManagementCapabilities & PCI_pm_d2supp) == 0)
|
||||
return EOPNOTSUPP;
|
||||
newPowerManagementStatus |= PCIM_PSTAT_D2;
|
||||
break;
|
||||
case PCI_POWERSTATE_D3:
|
||||
newPowerManagementStatus |= PCIM_PSTAT_D3;
|
||||
break;
|
||||
default:
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
TRACE_PCI(dev, "%s: D%i -> D%i\n", __func__, oldPowerState, newPowerState);
|
||||
pci_write_config(dev, capabilityRegister + PCIR_POWER_STATUS,
|
||||
newPowerManagementStatus, 2);
|
||||
if (stateTransitionDelayInUs != 0)
|
||||
snooze(stateTransitionDelayInUs);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user