diff --git a/src/system/kernel/arch/m68k/arch_cpu.cpp b/src/system/kernel/arch/m68k/arch_cpu.cpp
index 829fe87f2a..f3dcfcd7c4 100644
--- a/src/system/kernel/arch/m68k/arch_cpu.cpp
+++ b/src/system/kernel/arch/m68k/arch_cpu.cpp
@@ -48,7 +48,7 @@ arch_cpu_init_post_modules(kernel_args *args)
 	return B_OK;
 }
 
-#define CACHELINE 32
+#define CACHELINE 16
 
 void 
 arch_cpu_sync_icache(void *address, size_t len)
@@ -65,8 +65,20 @@ arch_cpu_sync_icache(void *address, size_t len)
 	asm volatile ("movec %%cacr,%0" : "=r"(cacr):);
 	cacr |= 0x00000004; /* ClearInstructionCacheEntry */
 	do {
-		asm volatile ("movec %0,%%caar" :: "r"(p));
-		asm volatile ("movec %0,%%cacr" :: "r"(cacr));
+		/* the 030 invalidates only 1 long of the cache line */
+		//XXX: what about 040 and 060 ?
+		asm volatile ("movec %0,%%caar\n"		\
+					  "movec %1,%%cacr\n"		\
+					  "addq.l #4,%0\n"			\
+					  "movec %0,%%caar\n"		\
+					  "movec %1,%%cacr\n"		\
+					  "addq.l #4,%0\n"			\
+					  "movec %0,%%caar\n"		\
+					  "movec %1,%%cacr\n"		\
+					  "addq.l #4,%0\n"			\
+					  "movec %0,%%caar\n"		\
+					  "movec %1,%%cacr\n"		\
+					  :: "r"(p), "r"(cacr));
 		p += CACHELINE;
 	} while ((l -= CACHELINE) > 0);
 	m68k_nop();
diff --git a/src/system/kernel/arch/m68k/arch_cpu_asm.S b/src/system/kernel/arch/m68k/arch_cpu_asm.S
index e90b01ff35..47e5b798e3 100644
--- a/src/system/kernel/arch/m68k/arch_cpu_asm.S
+++ b/src/system/kernel/arch/m68k/arch_cpu_asm.S
@@ -7,6 +7,7 @@
 
 .text
 
+#if 0 /* PPC stuff ahead... */
 /* uint32 get_sdr1(void);
  */
 FUNCTION(get_sdr1):
@@ -175,4 +176,4 @@ FUNCTION(reset_dbats):
 FUNCTION(__eieio):
 	eieio
 	blr
-
+#endif