* Add TMDS Set and Power controls
* Call TMDS controls if the monitor is TMDS connected git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42467 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
parent
9e26987aff
commit
422a49d2f8
@ -342,6 +342,9 @@ radeon_set_display_mode(display_mode *mode)
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// Power up the output
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PLLPower(gDisplay[display_id]->connection_id, RHD_POWER_ON);
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DACPower(gDisplay[display_id]->connection_id, RHD_POWER_ON);
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} else if ((gDisplay[display_id]->connection_type & CONNECTION_TMDS) != 0) {
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TMDSSet(gDisplay[display_id]->connection_id, mode);
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TMDSPower(gDisplay[display_id]->connection_id, RHD_POWER_ON);
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}
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// Ensure screen isn't blanked
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@ -22,6 +22,83 @@ extern "C" void _sPrintf(const char *format, ...);
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#endif
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/*
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* From Xorg Driver
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* This information is not provided in an atombios data table.
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*/
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static struct R5xxTMDSAMacro {
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uint16 device;
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uint32 macro;
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} R5xxTMDSAMacro[] = {
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{ 0x7104, 0x00C00414 }, /* R520 */
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{ 0x7142, 0x00A00415 }, /* RV515 */
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{ 0x7145, 0x00A00416 }, /* M54 */
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{ 0x7146, 0x00C0041F }, /* RV515 */
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{ 0x7147, 0x00C00418 }, /* RV505 */
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{ 0x7149, 0x00800416 }, /* M56 */
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{ 0x7152, 0x00A00415 }, /* RV515 */
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{ 0x7183, 0x00600412 }, /* RV530 */
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{ 0x71C1, 0x00C0041F }, /* RV535 */
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{ 0x71C2, 0x00A00416 }, /* RV530 */
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{ 0x71C4, 0x00A00416 }, /* M56 */
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{ 0x71C5, 0x00A00416 }, /* M56 */
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{ 0x71C6, 0x00A00513 }, /* RV530 */
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{ 0x71D2, 0x00A00513 }, /* RV530 */
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{ 0x71D5, 0x00A00513 }, /* M66 */
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{ 0x7249, 0x00A00513 }, /* R580 */
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{ 0x724B, 0x00A00513 }, /* R580 */
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{ 0x7280, 0x00C0041F }, /* RV570 */
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{ 0x7288, 0x00C0041F }, /* RV570 */
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{ 0x9400, 0x00910419 }, /* R600: */
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{ 0, 0} /* End marker */
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};
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static struct Rv6xxTMDSAMacro {
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uint16 device;
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uint32 pll;
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uint32 tx;
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} Rv6xxTMDSAMacro[] = {
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{ 0x94C1, 0x00010416, 0x00010308 }, /* RV610 */
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{ 0x94C3, 0x00010416, 0x00010308 }, /* RV610 */
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{ 0x9501, 0x00010416, 0x00010308 }, /* RV670: != atombios */
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{ 0x9505, 0x00010416, 0x00010308 }, /* RV670: != atombios */
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{ 0x950F, 0x00010416, 0x00010308 }, /* R680 : != atombios */
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{ 0x9581, 0x00030410, 0x00301044 }, /* M76 */
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{ 0x9587, 0x00010416, 0x00010308 }, /* RV630 */
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{ 0x9588, 0x00010416, 0x00010388 }, /* RV630 */
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{ 0x9589, 0x00010416, 0x00010388 }, /* RV630 */
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{ 0, 0, 0} /* End marker */
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};
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void
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TMDSVoltageControl(uint8 tmdsIndex)
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{
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int i;
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radeon_shared_info &info = *gInfo->shared_info;
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if (info.device_chipset < (RADEON_R600 | 0x10)) {
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for (i = 0; R5xxTMDSAMacro[i].device; i++) {
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if (R5xxTMDSAMacro[i].device == info.device_id) {
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Write32(OUT, TMDSA_MACRO_CONTROL, R5xxTMDSAMacro[i].macro);
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return;
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}
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}
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TRACE("%s : unhandled chipset 0x%X\n", __func__, info.device_id);
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} else {
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for (i = 0; Rv6xxTMDSAMacro[i].device; i++) {
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if (Rv6xxTMDSAMacro[i].device == info.device_id) {
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Write32(OUT, TMDSA_PLL_ADJUST, Rv6xxTMDSAMacro[i].pll);
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Write32(OUT, TMDSA_TRANSMITTER_ADJUST, Rv6xxTMDSAMacro[i].tx);
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return;
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}
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}
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TRACE("%s : unhandled chipset 0x%X\n", __func__, info.device_id);
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}
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}
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bool
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TMDSSense(uint8 tmdsIndex)
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{
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@ -44,3 +121,106 @@ TMDSSense(uint8 tmdsIndex)
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}
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status_t
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TMDSPower(uint8 tmdsIndex, int command)
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{
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// For now radeon cards only have TMDSA and no TMDSB
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switch (command) {
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case RHD_POWER_ON:
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{
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TRACE("%s: TMDS %d Power On\n", __func__, tmdsIndex);
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Write32Mask(OUT, TMDSA_CNTL, 0x1, 0x00000001);
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Write32Mask(OUT, TMDSA_TRANSMITTER_CONTROL, 0x00000001, 0x00000001);
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snooze(20);
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// Reset transmitter
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Write32Mask(OUT, TMDSA_TRANSMITTER_CONTROL, 0x00000002, 0x00000002);
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snooze(2);
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Write32Mask(OUT, TMDSA_TRANSMITTER_CONTROL, 0, 0x00000002);
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snooze(30);
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// Restart data sync
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// TODO : <R600
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Write32Mask(OUT, TMDSA_DATA_SYNCHRONIZATION_R600,
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0x00000001, 0x00000001);
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snooze(2);
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Write32Mask(OUT, TMDSA_DATA_SYNCHRONIZATION_R600,
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0x00000100, 0x00000100);
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Write32Mask(OUT, TMDSA_DATA_SYNCHRONIZATION_R600, 0, 0x00000001);
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// TODO : DualLink, for now we assume not.
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Write32Mask(OUT, TMDSA_TRANSMITTER_ENABLE, 0x0000001F, 0x00001F1F);
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// TODO : HdmiEnable true
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return B_OK;
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}
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case RHD_POWER_RESET:
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{
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TRACE("%s: TMDS %d Power Reset\n", __func__, tmdsIndex);
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Write32Mask(OUT, TMDSA_TRANSMITTER_ENABLE, 0, 0x00001F1F);
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return B_OK;
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}
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case RHD_POWER_SHUTDOWN:
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default:
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{
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Write32Mask(OUT, TMDSA_TRANSMITTER_CONTROL, 0x00000002, 0x00000002);
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snooze(2);
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Write32Mask(OUT, TMDSA_TRANSMITTER_CONTROL, 0, 0x00000001);
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Write32Mask(OUT, TMDSA_TRANSMITTER_ENABLE, 0, 0x00001F1F);
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Write32Mask(OUT, TMDSA_CNTL, 0, 0x00000001);
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// TODO : HdmiEnable false
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}
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}
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return B_OK;
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}
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status_t
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TMDSSet(uint8 tmdsIndex, display_mode *mode)
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{
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TRACE("%s: TMDS %d Set\n", __func__, tmdsIndex);
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// Clear HPD events
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Write32Mask(OUT, TMDSA_TRANSMITTER_CONTROL, 0, 0x0000000C);
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Write32Mask(OUT, TMDSA_TRANSMITTER_ENABLE, 0, 0x00070000);
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Write32Mask(OUT, TMDSA_CNTL, 0, 0x00000010);
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// Disable transmitter
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Write32Mask(OUT, TMDSA_TRANSMITTER_ENABLE, 0, 0x00001D1F);
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// Disable bit reduction and reset dither
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Write32Mask(OUT, TMDSA_BIT_DEPTH_CONTROL, 0, 0x00010101);
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// TODO : <R600
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Write32Mask(OUT, TMDSA_BIT_DEPTH_CONTROL, 0x02000000, 0x02000000);
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snooze(2);
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Write32Mask(OUT, TMDSA_BIT_DEPTH_CONTROL, 0, 0x02000000);
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// Reset phase on vsync
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Write32Mask(OUT, TMDSA_CNTL, 0x00001000, 0x00011000);
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// TODO : for now we assume crt 0, needs refactoring
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Write32Mask(OUT, TMDSA_SOURCE_SELECT, 0, 0x00010101);
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Write32(OUT, TMDSA_COLOR_FORMAT, 0);
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// Set single link for now
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// TODO : SynthClock > 165000 this is DualLink
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Write32Mask(OUT, TMDSA_CNTL, 0, 0x01000000);
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// Disable force data
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Write32Mask(OUT, TMDSA_FORCE_OUTPUT_CNTL, 0, 0x00000001);
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// Enable DC balancer
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Write32Mask(OUT, TMDSA_DCBALANCER_CONTROL, 0x00000001, 0x00000001);
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TMDSVoltageControl(tmdsIndex);
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// USE IDCLK
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Write32Mask(OUT, TMDSA_TRANSMITTER_CONTROL, 0x00000010, 0x00000010);
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// TODO : if coherent? For now lets asume false
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Write32Mask(OUT, TMDSA_TRANSMITTER_CONTROL, 0x10000000, 0x10000000);
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// TODO : HdmiSetMode(mode)
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return B_OK;
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}
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@ -9,7 +9,10 @@
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#define RADEON_HD_TMDS_H
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void TMDSVoltageControl(uint8 tmdsIndex);
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bool TMDSSense(uint8 tmdsIndex);
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status_t TMDSPower(uint8 tmdsIndex, int command);
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status_t TMDSSet(uint8 tmdsIndex, display_mode *mode);
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#endif
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