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intel_extreme: if no EDID found use boottime EDID if there

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This commit is contained in:
Rudolf Cornelissen 2022-01-31 22:02:50 +00:00
parent f9e868fc8f
commit 41f6b7906d
2 changed files with 18 additions and 4 deletions
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13
src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
View File

@ -330,6 +330,11 @@ FDILink::Train(display_timing* target) // fixme: seperate FDI training and PIPE
Receiver().DisablePLL();
#endif
TRACE("%s: FDI M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_M1));
TRACE("%s: FDI N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_N1));
TRACE("%s: FDI M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_M1));
TRACE("%s: FDI N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_N1));
//Setup Data M/N
uint64 linkspeed = lanes * linkBandwidth * 8;
uint64 ret_n = 1;
@ -366,10 +371,10 @@ FDILink::Train(display_timing* target) // fixme: seperate FDI training and PIPE
//Writing Link N triggers all four registers to be activated also (on next VBlank)
write32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_N1, ret_n);
TRACE("%s: FDI data M1: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_M1));
TRACE("%s: FDI data N1: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_N1));
TRACE("%s: FDI link M1: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_M1));
TRACE("%s: FDI link N1: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_N1));
TRACE("%s: FDI M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_M1));
TRACE("%s: FDI N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_N1));
TRACE("%s: FDI M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_M1));
TRACE("%s: FDI N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_N1));
//Set receiving end TU size bits to match sending end's setting
write32(Receiver().Base() + PCH_FDI_RX_TRANS_UNIT_SIZE_1, FDI_RX_TRANS_UNIT_MASK);

9
src/add-ons/accelerants/intel_extreme/mode.cpp
View File

@ -203,6 +203,15 @@ create_mode_list(void)
if (status == B_OK)
gInfo->has_edid = true;
}
// use EDID found at boot time if there since we don't have any ourselves
if (!gInfo->has_edid && gInfo->shared_info->has_vesa_edid_info) {
TRACE("%s: Using VESA edid info\n", __func__);
memcpy(&gInfo->edid_info, &gInfo->shared_info->vesa_edid_info,
sizeof(edid1_info));
// show in log what we got
edid_dump(&gInfo->edid_info);
gInfo->has_edid = true;
}
display_mode* list;
uint32 count = 0;