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kernel: implement clear_caches for riscv64

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Change-Id: I28296725ce22b47e94481abf794b92cf4ffd98a5
Reviewed-on: https://review.haiku-os.org/c/haiku/+/6217
Tested-by: Automation <automation@haiku-os.org>
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
This commit is contained in:
X512 2023-03-17 20:14:13 +09:00 committed by waddlesplash
parent 1e4146cbc6
commit 408a7e27d9
3 changed files with 13 additions and 2 deletions
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6
src/system/kernel/arch/riscv64/arch_cpu.cpp
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@ -90,6 +90,12 @@ arch_cpu_init_post_modules(kernel_args *args)
void
arch_cpu_sync_icache(void *address, size_t len)
{
FenceI();
if (smp_get_num_cpus() > 1) {
memory_full_barrier();
sbi_remote_fence_i(0, -1);
}
}

5
src/system/kernel/cpu.cpp
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@ -189,7 +189,10 @@ cpu_frequency(int32 cpu)
void
clear_caches(void *address, size_t length, uint32 flags)
{
// ToDo: implement me!
// TODO: data cache
if ((B_INVALIDATE_ICACHE & flags) != 0) {
arch_cpu_sync_icache(address, length);
}
}

4
src/system/libroot/os/arch/riscv64/cachectl.cpp
View File

@ -3,9 +3,11 @@
* Distributed under the terms of the MIT License.
*/
#include <image.h>
extern "C" void
__riscv_flush_icache(void *start, void *end, unsigned long int flags)
{
__asm__ volatile ("fence.i");
clear_caches(start, (uint8*)end - (uint8*)start, B_INVALIDATE_ICACHE);
}