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updated DPMS programming to take DVI panels into account for TVout modes on the same head. Enabled TVout support for all cards as long as they have a supported encoder (test-image is now shut-off). TVout support should be complete now, apart from adding support for more encoder-types. Bumped version to 0.63.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14939 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-11-15 12:12:45 +00:00
parent d89467ed24
commit 4022652c41
8 changed files with 67 additions and 45 deletions
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22
src/add-ons/accelerants/nvidia/SetDisplayMode.c
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@ -84,8 +84,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
if (si->ps.tvout) BT_stop_tvout(); if (si->ps.tvout) BT_stop_tvout();
/* turn off screen(s) _after_ TVout is disabled (if applicable) */ /* turn off screen(s) _after_ TVout is disabled (if applicable) */
head1_dpms(false, false, false); head1_dpms(false, false, false, true);
if (si->ps.secondary_head) head2_dpms(false, false, false); if (si->ps.secondary_head) head2_dpms(false, false, false, true);
if (si->ps.tvout) BT_dpms(false); if (si->ps.tvout) BT_dpms(false);
/*where in framebuffer the screen is (should this be dependant on previous MOVEDISPLAY?)*/ /*where in framebuffer the screen is (should this be dependant on previous MOVEDISPLAY?)*/
@ -479,15 +479,18 @@ void SET_INDEXED_COLORS(uint count, uint8 first, uint8 *color_data, uint32 flags
/* Put the display into one of the Display Power Management modes. */ /* Put the display into one of the Display Power Management modes. */
status_t SET_DPMS_MODE(uint32 dpms_flags) status_t SET_DPMS_MODE(uint32 dpms_flags)
{ {
bool display, h1h, h1v, h2h, h2v; bool display, h1h, h1v, h2h, h2v, do_p1, do_p2;
interrupt_enable(false); interrupt_enable(false);
LOG(4,("SET_DPMS_MODE: 0x%08x\n", dpms_flags)); LOG(4,("SET_DPMS_MODE: $%08x\n", dpms_flags));
/* note current DPMS state for our reference */ /* note current DPMS state for our reference */
si->dpms_flags = dpms_flags; si->dpms_flags = dpms_flags;
/* preset: DPMS for panels should be executed */
do_p1 = do_p2 = true;
/* determine signals to send to head(s) */ /* determine signals to send to head(s) */
display = h1h = h1v = h2h = h2v = true; display = h1h = h1v = h2h = h2v = true;
switch(dpms_flags) switch(dpms_flags)
@ -504,7 +507,7 @@ status_t SET_DPMS_MODE(uint32 dpms_flags)
display = h1h = h1v = h2h = h2v = false; display = h1h = h1v = h2h = h2v = false;
break; break;
default: default:
LOG(8,("SET: Invalid DPMS settings (DH) 0x%08x\n", dpms_flags)); LOG(8,("SET: Invalid DPMS settings $%08x\n", dpms_flags));
interrupt_enable(true); interrupt_enable(true);
return B_ERROR; return B_ERROR;
} }
@ -530,6 +533,8 @@ status_t SET_DPMS_MODE(uint32 dpms_flags)
* This leaves Hsync only for shutting off the VGA screen. */ * This leaves Hsync only for shutting off the VGA screen. */
h1h = false; h1h = false;
h1v = true; h1v = true;
/* block panel DPMS updates */
do_p1 = false;
} }
else else
{ {
@ -551,6 +556,7 @@ status_t SET_DPMS_MODE(uint32 dpms_flags)
{ {
h2h = false; h2h = false;
h2v = true; h2v = true;
do_p2 = false;
} }
else else
{ {
@ -569,6 +575,7 @@ status_t SET_DPMS_MODE(uint32 dpms_flags)
{ {
h2h = false; h2h = false;
h2v = true; h2v = true;
do_p2 = false;
} }
else else
{ {
@ -582,6 +589,7 @@ status_t SET_DPMS_MODE(uint32 dpms_flags)
{ {
h1h = false; h1h = false;
h1v = true; h1v = true;
do_p1 = false;
} }
else else
{ {
@ -593,9 +601,9 @@ status_t SET_DPMS_MODE(uint32 dpms_flags)
} }
/* issue actual DPMS commands as far as applicable */ /* issue actual DPMS commands as far as applicable */
head1_dpms(display, h1h, h1v); head1_dpms(display, h1h, h1v, do_p1);
if ((si->ps.secondary_head) && (si->dm.flags & DUALHEAD_BITS)) if ((si->ps.secondary_head) && (si->dm.flags & DUALHEAD_BITS))
head2_dpms(display, h2h, h2v); head2_dpms(display, h2h, h2v, do_p2);
if (si->dm.flags & TV_BITS) if (si->dm.flags & TV_BITS)
BT_dpms(display); BT_dpms(display);

14
src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c
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@ -1632,6 +1632,13 @@ status_t BT_stop_tvout(void)
* a full encoder chip reset could be done here (so after decoupling crtc)... */ * a full encoder chip reset could be done here (so after decoupling crtc)... */
/* (but: beware of the 'locked SDA' syndrome then!) */ /* (but: beware of the 'locked SDA' syndrome then!) */
/* fixme if needed: we _could_ setup a TVout mode and apply the testsignal here... */
if (0)
{
//set mode (selecting PAL/NTSC according to board wiring for example) etc, then:
BT_testsignal();
}
return B_OK; return B_OK;
}//end BT_stop_tvout. }//end BT_stop_tvout.
@ -1735,13 +1742,6 @@ status_t BT_setmode(display_mode target)
head1_set_timing(tv_target); head1_set_timing(tv_target);
} }
//fixme: only testing older cards for now...
if (si->ps.secondary_head && (si->ps.card_type > NV15))
{
BT_testsignal();
return B_OK;
}
/* now set GPU CRTC to slave mode */ /* now set GPU CRTC to slave mode */
BT_start_tvout(tv_target); BT_start_tvout(tv_target);

27
src/add-ons/accelerants/nvidia/engine/nv_crtc.c
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@ -548,11 +548,12 @@ status_t nv_crtc_depth(int mode)
return B_OK; return B_OK;
} }
status_t nv_crtc_dpms(bool display, bool h, bool v) status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel)
{ {
uint8 temp; uint8 temp;
char msg[100];
LOG(4,("CRTC: setting DPMS: ")); sprintf(msg, "CRTC: setting DPMS: ");
/* enable access to primary head */ /* enable access to primary head */
set_crtc_owner(0); set_crtc_owner(0);
@ -569,7 +570,7 @@ status_t nv_crtc_dpms(bool display, bool h, bool v)
/* end synchronous reset because display should be enabled */ /* end synchronous reset because display should be enabled */
SEQW(RESET, 0x03); SEQW(RESET, 0x03);
if (si->ps.tmds1_active && !si->ps.laptop) if (do_panel && si->ps.tmds1_active && !si->ps.laptop)
{ {
/* restore original panelsync and panel-enable */ /* restore original panelsync and panel-enable */
uint32 panelsync = 0x00000000; uint32 panelsync = 0x00000000;
@ -590,16 +591,18 @@ status_t nv_crtc_dpms(bool display, bool h, bool v)
/* ... and powerup external TMDS transmitter if it exists */ /* ... and powerup external TMDS transmitter if it exists */
/* (confirmed OK on NV28 and NV34) */ /* (confirmed OK on NV28 and NV34) */
//CRTCW(0x59, (CRTCR(0x59) | 0x01)); //CRTCW(0x59, (CRTCR(0x59) | 0x01));
sprintf(msg, "%s(panel-)", msg);
} }
LOG(4,("display on, ")); sprintf(msg, "%sdisplay on, ", msg);
} }
else else
{ {
/* turn screen off */ /* turn screen off */
SEQW(CLKMODE, (temp | 0x20)); SEQW(CLKMODE, (temp | 0x20));
if (si->ps.tmds1_active && !si->ps.laptop) if (do_panel && si->ps.tmds1_active && !si->ps.laptop)
{ {
/* shutoff panelsync and disable panel */ /* shutoff panelsync and disable panel */
DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022));
@ -615,32 +618,36 @@ status_t nv_crtc_dpms(bool display, bool h, bool v)
/* ... and powerdown external TMDS transmitter if it exists */ /* ... and powerdown external TMDS transmitter if it exists */
/* (confirmed OK on NV28 and NV34) */ /* (confirmed OK on NV28 and NV34) */
//CRTCW(0x59, (CRTCR(0x59) & 0xfe)); //CRTCW(0x59, (CRTCR(0x59) & 0xfe));
sprintf(msg, "%s(panel-)", msg);
} }
LOG(4,("display off, ")); sprintf(msg, "%sdisplay off, ", msg);
} }
if (h) if (h)
{ {
CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f)); CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f));
LOG(4,("hsync enabled, ")); sprintf(msg, "%shsync enabled, ", msg);
} }
else else
{ {
CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x80)); CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x80));
LOG(4,("hsync disabled, ")); sprintf(msg, "%shsync disabled, ", msg);
} }
if (v) if (v)
{ {
CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf)); CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf));
LOG(4,("vsync enabled\n")); sprintf(msg, "%svsync enabled\n", msg);
} }
else else
{ {
CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x40)); CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x40));
LOG(4,("vsync disabled\n")); sprintf(msg, "%svsync disabled\n", msg);
} }
LOG(4, (msg));
return B_OK; return B_OK;
} }

27
src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
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@ -531,11 +531,12 @@ status_t nv_crtc2_depth(int mode)
return B_OK; return B_OK;
} }
status_t nv_crtc2_dpms(bool display, bool h, bool v) status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel)
{ {
uint8 temp; uint8 temp;
char msg[100];
LOG(4,("CRTC2: setting DPMS: ")); sprintf(msg, "CRTC2: setting DPMS: ");
/* enable access to secondary head */ /* enable access to secondary head */
set_crtc_owner(1); set_crtc_owner(1);
@ -552,7 +553,7 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v)
/* end synchronous reset because display should be enabled */ /* end synchronous reset because display should be enabled */
SEQW(RESET, 0x03); SEQW(RESET, 0x03);
if (si->ps.tmds2_active && !si->ps.laptop) if (do_panel && si->ps.tmds2_active && !si->ps.laptop)
{ {
/* restore original panelsync and panel-enable */ /* restore original panelsync and panel-enable */
uint32 panelsync = 0x00000000; uint32 panelsync = 0x00000000;
@ -573,16 +574,18 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v)
/* ... and powerup external TMDS transmitter if it exists */ /* ... and powerup external TMDS transmitter if it exists */
/* (confirmed OK on NV28 and NV34) */ /* (confirmed OK on NV28 and NV34) */
//CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); //CRTC2W(0x59, (CRTC2R(0x59) | 0x01));
sprintf(msg, "%s(panel-)", msg);
} }
LOG(4,("display on, ")); sprintf(msg, "%sdisplay on, ", msg);
} }
else else
{ {
/* turn screen off */ /* turn screen off */
SEQW(CLKMODE, (temp | 0x20)); SEQW(CLKMODE, (temp | 0x20));
if (si->ps.tmds2_active && !si->ps.laptop) if (do_panel && si->ps.tmds2_active && !si->ps.laptop)
{ {
/* shutoff panelsync and disable panel */ /* shutoff panelsync and disable panel */
DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022));
@ -598,32 +601,36 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v)
/* ... and powerdown external TMDS transmitter if it exists */ /* ... and powerdown external TMDS transmitter if it exists */
/* (confirmed OK on NV28 and NV34) */ /* (confirmed OK on NV28 and NV34) */
//CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); //CRTC2W(0x59, (CRTC2R(0x59) & 0xfe));
sprintf(msg, "%s(panel-)", msg);
} }
LOG(4,("display off, ")); sprintf(msg, "%sdisplay off, ", msg);
} }
if (h) if (h)
{ {
CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f));
LOG(4,("hsync enabled, ")); sprintf(msg, "%shsync enabled, ", msg);
} }
else else
{ {
CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80));
LOG(4,("hsync disabled, ")); sprintf(msg, "%shsync disabled, ", msg);
} }
if (v) if (v)
{ {
CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf));
LOG(4,("vsync enabled\n")); sprintf(msg, "%svsync enabled\n", msg);
} }
else else
{ {
CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40));
LOG(4,("vsync disabled\n")); sprintf(msg, "%svsync disabled\n", msg);
} }
LOG(4, (msg));
return B_OK; return B_OK;
} }

6
src/add-ons/accelerants/nvidia/engine/nv_general.c
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@ -91,7 +91,7 @@ status_t nv_general_powerup()
{ {
status_t status; status_t status;
LOG(1,("POWERUP: Haiku nVidia Accelerant 0.62 running.\n")); LOG(1,("POWERUP: Haiku nVidia Accelerant 0.63 running.\n"));
/* log VBLANK INT usability status */ /* log VBLANK INT usability status */
if (si->ps.int_assigned) if (si->ps.int_assigned)
@ -1267,11 +1267,11 @@ static status_t nv_general_bios_to_powergraphics()
unlock_card(); unlock_card();
/* turn off both displays and the hardcursors (also disables transfers) */ /* turn off both displays and the hardcursors (also disables transfers) */
head1_dpms(false, false, false); head1_dpms(false, false, false, true);
head1_cursor_hide(); head1_cursor_hide();
if (si->ps.secondary_head) if (si->ps.secondary_head)
{ {
head2_dpms(false, false, false); head2_dpms(false, false, false, true);
head2_cursor_hide(); head2_cursor_hide();
} }

2
src/add-ons/accelerants/nvidia/engine/nv_globals.h
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@ -15,7 +15,7 @@ extern nv_in_out_isa nv_isa_access;
typedef status_t (*crtc_validate_timing)(uint16*, uint16*, uint16*, uint16*, uint16*, uint16*, uint16*, uint16*); typedef status_t (*crtc_validate_timing)(uint16*, uint16*, uint16*, uint16*, uint16*, uint16*, uint16*, uint16*);
typedef status_t (*crtc_set_timing)(display_mode); typedef status_t (*crtc_set_timing)(display_mode);
typedef status_t (*crtc_depth)(int); typedef status_t (*crtc_depth)(int);
typedef status_t (*crtc_dpms)(bool, bool, bool); typedef status_t (*crtc_dpms)(bool, bool, bool, bool);
typedef status_t (*crtc_set_display_pitch)(void); typedef status_t (*crtc_set_display_pitch)(void);
typedef status_t (*crtc_set_display_start)(uint32, uint8); typedef status_t (*crtc_set_display_start)(uint32, uint8);
typedef status_t (*crtc_cursor_init)(void); typedef status_t (*crtc_cursor_init)(void);

10
src/add-ons/accelerants/nvidia/engine/nv_info.c
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@ -1,7 +1,7 @@
/* Read initialisation information from card */ /* Read initialisation information from card */
/* some bits are hacks, where PINS is not known */ /* some bits are hacks, where PINS is not known */
/* Author: /* Author:
Rudolf Cornelissen 7/2003-10/2005 Rudolf Cornelissen 7/2003-11/2005
*/ */
#define MODULE_BIT 0x00002000 #define MODULE_BIT 0x00002000
@ -263,11 +263,11 @@ static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 in
} }
/* turn off both displays and the hardcursors (also disables transfers) */ /* turn off both displays and the hardcursors (also disables transfers) */
nv_crtc_dpms(false, false, false); nv_crtc_dpms(false, false, false, true);
nv_crtc_cursor_hide(); nv_crtc_cursor_hide();
if (si->ps.secondary_head) if (si->ps.secondary_head)
{ {
nv_crtc2_dpms(false, false, false); nv_crtc2_dpms(false, false, false, true);
nv_crtc2_cursor_hide(); nv_crtc2_cursor_hide();
} }
@ -341,11 +341,11 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
} }
/* turn off both displays and the hardcursors (also disables transfers) */ /* turn off both displays and the hardcursors (also disables transfers) */
nv_crtc_dpms(false, false, false); nv_crtc_dpms(false, false, false, true);
nv_crtc_cursor_hide(); nv_crtc_cursor_hide();
if (si->ps.secondary_head) if (si->ps.secondary_head)
{ {
nv_crtc2_dpms(false, false, false); nv_crtc2_dpms(false, false, false, true);
nv_crtc2_cursor_hide(); nv_crtc2_cursor_hide();
} }

4
src/add-ons/accelerants/nvidia/engine/nv_proto.h
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@ -74,7 +74,7 @@ status_t nv_crtc_set_timing(display_mode target);
status_t nv_crtc_depth(int mode); status_t nv_crtc_depth(int mode);
status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp); status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp);
status_t nv_crtc_set_display_pitch(void); status_t nv_crtc_set_display_pitch(void);
status_t nv_crtc_dpms(bool, bool, bool); status_t nv_crtc_dpms(bool, bool, bool, bool);
status_t nv_crtc_mem_priority(uint8); status_t nv_crtc_mem_priority(uint8);
status_t nv_crtc_cursor_init(void); status_t nv_crtc_cursor_init(void);
status_t nv_crtc_cursor_define(uint8*,uint8*); status_t nv_crtc_cursor_define(uint8*,uint8*);
@ -93,7 +93,7 @@ status_t nv_crtc2_set_timing(display_mode target);
status_t nv_crtc2_depth(int mode); status_t nv_crtc2_depth(int mode);
status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp); status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp);
status_t nv_crtc2_set_display_pitch(void); status_t nv_crtc2_set_display_pitch(void);
status_t nv_crtc2_dpms(bool, bool, bool); status_t nv_crtc2_dpms(bool, bool, bool, bool);
status_t nv_crtc2_mem_priority(uint8); status_t nv_crtc2_mem_priority(uint8);
status_t nv_crtc2_cursor_init(void); status_t nv_crtc2_cursor_init(void);
status_t nv_crtc2_cursor_define(uint8*,uint8*); status_t nv_crtc2_cursor_define(uint8*,uint8*);