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added cache descriptions reported by Intel Atom processor

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@30200 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
David McPaul 2009-04-16 11:50:12 +00:00
parent 4e5191e9c1
commit 3da76c0bec
1 changed files with 5 additions and 0 deletions
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5
src/bin/sysinfo.c
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@ -33,6 +33,7 @@ struct cache_description {
{0x0A, "L1 data cache: 8 KB, 2-way set associative, 32 bytes/line"},
{0x0C, "L1 data cache: 16 KB, 4-way set associative, 32 bytes/line"},
{0x0D, "L1 data cache: 16 KB, 4-way set associative, 64-bytes/line, ECC"},
{0x0E, "L1 data cache, 24 KB, 6-way set associative, 64-bytes/line"},
{0x10, /* IA-64 */ "L1 data cache: 16 KB, 4-way set associative, 32 bytes/line"},
{0x15, /* IA-64 */ "L1 inst cache: 16 KB, 4-way set associative, 32 bytes/line"},
{0x1A, /* IA-64 */ "L2 cache: 96 KB, 6-way set associative, 64 bytes/line"},
@ -65,12 +66,14 @@ struct cache_description {
{0x4C, "L3 cache: 12288 KB, 12-way set associative, 64 bytes/line"},
{0x4D, "L3 cache: 16384 KB, 16-way set associative, 64 bytes/line"},
{0x4E, "L2 cache: 6144 KB, 24-way set associative, 64 bytes/line"},
{0x4F, "Inst TLB, 4K-bytes pages, ???, 32 entries"},
{0x50, "Inst TLB: 4K/4M/2M-bytes pages, fully associative, 64 entries"},
{0x51, "Inst TLB: 4K/4M/2M-bytes pages, fully associative, 128 entries"},
{0x52, "Inst TLB: 4K/4M/2M-bytes pages, fully associative, 256 entries"},
{0x55, "Inst TLB: 2M/4M-bytes pages, fully associative, 7 entries"},
{0x56, "L1 Data TLB: 4M-bytes pages, 4-way set associative, 16 entries"},
{0x57, "L1 Data TLB: 4K-bytes pages, 4-way set associative, 16 entries"},
{0x59, "L0 Data TLB, 4K-bytes pages, fully associative, 16 entries"},
{0x5A, "Data TLB: 2M/4M-bytes pages, 4-way set associative, 32 entries"},
{0x5B, "Data TLB: 4K/4M-bytes pages, fully associative, 64 entries"},
{0x5C, "Data TLB: 4K/4M-bytes pages, fully associative, 128 entries"},
@ -112,6 +115,8 @@ struct cache_description {
{0xB2, "Inst TLB: 4K-bytes pages, 4-way set associative, 64 entries"},
{0xB3, "Data TLB: 4K-bytes pages, 4-way set associative, 128 entries"},
{0xB4, "Data TLB: 4K-bytes pages, 4-way set associative, 256 entries"},
{0xBA, "Data TLB, 4K-bytes pages, 4-way set associative, 64 entries"},
{0xC0, "Data TLB, 4K-4M bytes pages, 4-way set associative, 8 entries"},
{0xCA, "Shared 2nd-level TLB: 4K, 4-way set associative, 512 entries"},
{0xD0, "L3 cache: 512 KB, 4-way set associative, 64-bytes/line"},
{0xD1, "L3 cache: 1024 KB, 4-way set associative, 64-bytes/line"},