Patch from Jérôme Leveque: Work in progress: code cleanup (includes dos newlines and 80 chars by line)
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41778 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Jérôme Duval
parent
d61187a1f3
commit
3cd099e2d4
@ -11,8 +11,6 @@
|
||||
#ifndef _DEBUG_ICE1712_H_
|
||||
#define _DEBUG_ICE1712_H_
|
||||
|
||||
#include <Debug.h>
|
||||
|
||||
#ifdef TRACE
|
||||
# undef TRACE
|
||||
#endif
|
||||
@ -24,6 +22,11 @@
|
||||
# define TRACE(a...) ;
|
||||
#endif
|
||||
|
||||
#define ICE1712_VERY_VERBOSE 0
|
||||
//#define ICE1712_VERY_VERBOSE
|
||||
#ifdef ICE1712_VERY_VERBOSE
|
||||
# define TRACE_VV(a...) dprintf("\33[34mice1712:\33[0m " a)
|
||||
#else
|
||||
# define TRACE_VV(a...) ;
|
||||
#endif
|
||||
|
||||
#endif // _DEBUG_ICE1712_H_
|
||||
|
||||
@ -18,13 +18,13 @@
|
||||
#include <midi_driver.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "debug.h"
|
||||
#include "ice1712.h"
|
||||
#include "ice1712_reg.h"
|
||||
#include "io.h"
|
||||
#include "multi.h"
|
||||
#include "util.h"
|
||||
|
||||
#include "debug.h"
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
@ -65,10 +65,6 @@ int32 api_version = B_CUR_DRIVER_API_VERSION;
|
||||
//extern status_t unload_kernel_addon(image_id imid);
|
||||
|
||||
//------------------------------------------------------
|
||||
|
||||
static status_t load_settings(ice1712 *ice);
|
||||
static status_t save_settings(ice1712 *ice);
|
||||
|
||||
//------------------------------------------------------
|
||||
|
||||
status_t init_hardware(void)
|
||||
@ -164,27 +160,39 @@ ice1712_setup(ice1712 *ice)
|
||||
write_ccs_uint8(ice, CCS_SERR_SHADOW, 0x01);
|
||||
|
||||
//Write all configurations register from EEProm
|
||||
ice->info.device_id = ice->eeprom_data[E2PROM_MAP_SUBVENDOR_HIGH] << 8 | ice->eeprom_data[E2PROM_MAP_SUBVENDOR_LOW];
|
||||
ice->info.vendor_id = ice->eeprom_data[E2PROM_MAP_SUBDEVICE_HIGH] << 8 | ice->eeprom_data[E2PROM_MAP_SUBDEVICE_LOW];
|
||||
ice->info.device_id = ice->eeprom_data[E2PROM_MAP_SUBVENDOR_HIGH] << 8
|
||||
| ice->eeprom_data[E2PROM_MAP_SUBVENDOR_LOW];
|
||||
ice->info.vendor_id = ice->eeprom_data[E2PROM_MAP_SUBDEVICE_HIGH] << 8
|
||||
| ice->eeprom_data[E2PROM_MAP_SUBDEVICE_LOW];
|
||||
ice->product = ice->info.vendor_id << 16 | ice->info.device_id;
|
||||
TRACE("Product ID : 0x%x\n", ice->product);
|
||||
|
||||
write_cci_uint8(ice, CCI_GPIO_WRITE_MASK, ice->eeprom_data[E2PROM_MAP_GPIOMASK]);
|
||||
write_cci_uint8(ice, CCI_GPIO_DATA, ice->eeprom_data[E2PROM_MAP_GPIOSTATE]);
|
||||
write_cci_uint8(ice, CCI_GPIO_DIRECTION_CONTROL, ice->eeprom_data[E2PROM_MAP_GPIODIR]);
|
||||
write_cci_uint8(ice, CCI_GPIO_WRITE_MASK,
|
||||
ice->eeprom_data[E2PROM_MAP_GPIOMASK]);
|
||||
write_cci_uint8(ice, CCI_GPIO_DATA,
|
||||
ice->eeprom_data[E2PROM_MAP_GPIOSTATE]);
|
||||
write_cci_uint8(ice, CCI_GPIO_DIRECTION_CONTROL,
|
||||
ice->eeprom_data[E2PROM_MAP_GPIODIR]);
|
||||
|
||||
TRACE("CCI_GPIO_WRITE_MASK : 0x%x\n", ice->eeprom_data[E2PROM_MAP_GPIOMASK]);
|
||||
TRACE("CCI_GPIO_DATA : 0x%x\n", ice->eeprom_data[E2PROM_MAP_GPIOSTATE]);
|
||||
TRACE("CCI_GPIO_DIRECTION_CONTROL : 0x%x\n", ice->eeprom_data[E2PROM_MAP_GPIODIR]);
|
||||
TRACE("CCI_GPIO_WRITE_MASK : 0x%x\n",
|
||||
ice->eeprom_data[E2PROM_MAP_GPIOMASK]);
|
||||
TRACE("CCI_GPIO_DATA : 0x%x\n",
|
||||
ice->eeprom_data[E2PROM_MAP_GPIOSTATE]);
|
||||
TRACE("CCI_GPIO_DIRECTION_CONTROL : 0x%x\n",
|
||||
ice->eeprom_data[E2PROM_MAP_GPIODIR]);
|
||||
|
||||
|
||||
//Write Configuration in the PCI configuration Register
|
||||
(pci->write_pci_config)(ice->info.bus, ice->info.device, ice->info.function, 0x60, 1, ice->eeprom_data[E2PROM_MAP_CONFIG]);
|
||||
(pci->write_pci_config)(ice->info.bus, ice->info.device, ice->info.function, 0x61, 1, ice->eeprom_data[E2PROM_MAP_ACL]);
|
||||
(pci->write_pci_config)(ice->info.bus, ice->info.device, ice->info.function, 0x62, 1, ice->eeprom_data[E2PROM_MAP_I2S]);
|
||||
(pci->write_pci_config)(ice->info.bus, ice->info.device, ice->info.function, 0x63, 1, ice->eeprom_data[E2PROM_MAP_SPDIF]);
|
||||
(pci->write_pci_config)(ice->info.bus, ice->info.device,
|
||||
ice->info.function, 0x60, 1, ice->eeprom_data[E2PROM_MAP_CONFIG]);
|
||||
(pci->write_pci_config)(ice->info.bus, ice->info.device,
|
||||
ice->info.function, 0x61, 1, ice->eeprom_data[E2PROM_MAP_ACL]);
|
||||
(pci->write_pci_config)(ice->info.bus, ice->info.device,
|
||||
ice->info.function, 0x62, 1, ice->eeprom_data[E2PROM_MAP_I2S]);
|
||||
(pci->write_pci_config)(ice->info.bus, ice->info.device,
|
||||
ice->info.function, 0x63, 1, ice->eeprom_data[E2PROM_MAP_SPDIF]);
|
||||
|
||||
TRACE("E2PROM_MAP_CONFIG : 0x%x\n", ice->eeprom_data[E2PROM_MAP_CONFIG]);
|
||||
TRACE("E2PROM_MAP_CONFIG : 0x%x\n", ice->eeprom_data[E2PROM_MAP_CONFIG]);
|
||||
reg8 = ice->eeprom_data[E2PROM_MAP_CONFIG];
|
||||
//Bits signification for E2PROM_MAP_CONFIG Byte
|
||||
//
|
||||
@ -215,7 +223,8 @@ ice1712_setup(ice1712 *ice)
|
||||
ice->nb_MPU401 = (reg8 & 0x1) + 1;
|
||||
|
||||
for (i = 0; i < ice->nb_MPU401; i++) {
|
||||
sprintf(ice->midi_interf[i].name, "midi/ice1712/%ld/%d", ice - cards + 1, i + 1);
|
||||
sprintf(ice->midi_interf[i].name, "midi/ice1712/%ld/%d",
|
||||
ice - cards + 1, i + 1);
|
||||
names[num_names++] = ice->midi_interf[i].name;
|
||||
}
|
||||
|
||||
@ -225,31 +234,35 @@ ice1712_setup(ice1712 *ice)
|
||||
switch (ice->product) {
|
||||
case ICE1712_SUBDEVICE_DELTA66 :
|
||||
case ICE1712_SUBDEVICE_DELTA44 :
|
||||
ice->commlines.clock = DELTA66_CLK;
|
||||
ice->commlines.data_in = 0;
|
||||
ice->commlines.data_out = DELTA66_DOUT;
|
||||
ice->commlines.cs_mask = DELTA66_CLK | DELTA66_DOUT | DELTA66_CODEC_CS_0 | DELTA66_CODEC_CS_1;
|
||||
ice->CommLines.clock = DELTA66_CLK;
|
||||
ice->CommLines.data_in = 0;
|
||||
ice->CommLines.data_out = DELTA66_DOUT;
|
||||
ice->CommLines.cs_mask = DELTA66_CLK | DELTA66_DOUT
|
||||
| DELTA66_CODEC_CS_0 | DELTA66_CODEC_CS_1;
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA410 :
|
||||
case ICE1712_SUBDEVICE_AUDIOPHILE_2496 :
|
||||
case ICE1712_SUBDEVICE_DELTADIO2496 :
|
||||
ice->commlines.clock = AP2496_CLK;
|
||||
ice->commlines.data_in = AP2496_DIN;
|
||||
ice->commlines.data_out = AP2496_DOUT;
|
||||
ice->commlines.cs_mask = AP2496_CLK | AP2496_DIN | AP2496_DOUT | AP2496_SPDIF_CS | AP2496_CODEC_CS;
|
||||
ice->CommLines.clock = AP2496_CLK;
|
||||
ice->CommLines.data_in = AP2496_DIN;
|
||||
ice->CommLines.data_out = AP2496_DOUT;
|
||||
ice->CommLines.cs_mask = AP2496_CLK | AP2496_DIN
|
||||
| AP2496_DOUT | AP2496_SPDIF_CS | AP2496_CODEC_CS;
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA1010 :
|
||||
case ICE1712_SUBDEVICE_DELTA1010LT :
|
||||
ice->commlines.clock = DELTA1010LT_CLK;
|
||||
ice->commlines.data_in = DELTA1010LT_DIN;
|
||||
ice->commlines.data_out = DELTA1010LT_DOUT;
|
||||
ice->commlines.cs_mask = DELTA1010LT_CLK | DELTA1010LT_DIN | DELTA1010LT_DOUT | DELTA1010LT_CS_NONE;
|
||||
ice->CommLines.clock = DELTA1010LT_CLK;
|
||||
ice->CommLines.data_in = DELTA1010LT_DIN;
|
||||
ice->CommLines.data_out = DELTA1010LT_DOUT;
|
||||
ice->CommLines.cs_mask = DELTA1010LT_CLK | DELTA1010LT_DIN
|
||||
| DELTA1010LT_DOUT | DELTA1010LT_CS_NONE;
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_VX442 :
|
||||
ice->commlines.clock = VX442_CLK;
|
||||
ice->commlines.data_in = VX442_DIN;
|
||||
ice->commlines.data_out = VX442_DOUT;
|
||||
ice->commlines.cs_mask = VX442_SPDIF_CS | VX442_CODEC_CS_0 | VX442_CODEC_CS_1;
|
||||
ice->CommLines.clock = VX442_CLK;
|
||||
ice->CommLines.data_in = VX442_DIN;
|
||||
ice->CommLines.data_out = VX442_DOUT;
|
||||
ice->CommLines.cs_mask = VX442_SPDIF_CS | VX442_CODEC_CS_0
|
||||
| VX442_CODEC_CS_1;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -291,8 +304,6 @@ ice1712_setup(ice1712 *ice)
|
||||
memset(ice->log_addr_pb, 0, PLAYBACK_BUFFER_TOTAL_SIZE);
|
||||
memset(ice->log_addr_rec, 0, RECORD_BUFFER_TOTAL_SIZE);
|
||||
|
||||
load_settings(ice);
|
||||
|
||||
ice->sampling_rate = 0x08;
|
||||
ice->buffer = 0;
|
||||
ice->frames_count = 0;
|
||||
@ -307,15 +318,15 @@ ice1712_setup(ice1712 *ice)
|
||||
ice->total_input_channels += 2;
|
||||
|
||||
//Write bits in the GPIO
|
||||
write_cci_uint8(ice, CCI_GPIO_WRITE_MASK, ~(ice->commlines.cs_mask));
|
||||
write_cci_uint8(ice, CCI_GPIO_WRITE_MASK, ~(ice->CommLines.cs_mask));
|
||||
//Deselect CS
|
||||
write_cci_uint8(ice, CCI_GPIO_DATA, ice->commlines.cs_mask);
|
||||
write_cci_uint8(ice, CCI_GPIO_DATA, ice->CommLines.cs_mask);
|
||||
|
||||
//Set the rampe volume to a faster one
|
||||
write_mt_uint16(ice, MT_VOLUME_CONTROL_RATE, 0x01);
|
||||
|
||||
//Digital Mixer To DAC 0 and SPDIF Out
|
||||
// write_mt_uint16(ice, MT_ROUTING_CONTROL_PSDOUT, 0x0101);
|
||||
write_mt_uint16(ice, MT_ROUTING_CONTROL_PSDOUT, 0x0101);
|
||||
// write_mt_uint16(ice, MT_ROUTING_CONTROL_SPDOUT, 0x0005);
|
||||
|
||||
//Just to route all input to all output
|
||||
@ -432,8 +443,6 @@ ice_1712_shutdown(ice1712 *ice)
|
||||
delete_area(ice->mem_id_rec);
|
||||
|
||||
codec_write(ice, AK45xx_RESET_REGISTER, 0x00);
|
||||
|
||||
save_settings(ice);
|
||||
}
|
||||
|
||||
|
||||
@ -519,7 +528,8 @@ ice_1712_control(void *cookie, uint32 op, void *arg, size_t len)
|
||||
switch (op) {
|
||||
case B_MULTI_GET_DESCRIPTION :
|
||||
TRACE("B_MULTI_GET_DESCRIPTION\n");
|
||||
return ice1712_get_description((ice1712 *)cookie, (multi_description*)arg);
|
||||
return ice1712_get_description((ice1712 *)cookie,
|
||||
(multi_description*)arg);
|
||||
case B_MULTI_GET_EVENT_INFO :
|
||||
TRACE("B_MULTI_GET_EVENT_INFO\n");
|
||||
return B_ERROR;
|
||||
@ -531,16 +541,20 @@ ice_1712_control(void *cookie, uint32 op, void *arg, size_t len)
|
||||
return B_ERROR;
|
||||
case B_MULTI_GET_ENABLED_CHANNELS :
|
||||
TRACE("B_MULTI_GET_ENABLED_CHANNELS\n");
|
||||
return ice1712_get_enabled_channels((ice1712*)cookie, (multi_channel_enable*)arg);
|
||||
return ice1712_get_enabled_channels((ice1712*)cookie,
|
||||
(multi_channel_enable*)arg);
|
||||
case B_MULTI_SET_ENABLED_CHANNELS :
|
||||
TRACE("B_MULTI_SET_ENABLED_CHANNELS\n");
|
||||
return ice1712_set_enabled_channels((ice1712*)cookie, (multi_channel_enable*)arg);
|
||||
return ice1712_set_enabled_channels((ice1712*)cookie,
|
||||
(multi_channel_enable*)arg);
|
||||
case B_MULTI_GET_GLOBAL_FORMAT :
|
||||
TRACE("B_MULTI_GET_GLOBAL_FORMAT\n");
|
||||
return ice1712_get_global_format((ice1712*)cookie, (multi_format_info *)arg);
|
||||
return ice1712_get_global_format((ice1712*)cookie,
|
||||
(multi_format_info *)arg);
|
||||
case B_MULTI_SET_GLOBAL_FORMAT :
|
||||
TRACE("B_MULTI_SET_GLOBAL_FORMAT\n");
|
||||
return ice1712_set_global_format((ice1712*)cookie, (multi_format_info *)arg);
|
||||
return ice1712_set_global_format((ice1712*)cookie,
|
||||
(multi_format_info *)arg);
|
||||
case B_MULTI_GET_CHANNEL_FORMATS :
|
||||
TRACE("B_MULTI_GET_CHANNEL_FORMATS\n");
|
||||
return B_ERROR;
|
||||
@ -549,22 +563,28 @@ ice_1712_control(void *cookie, uint32 op, void *arg, size_t len)
|
||||
return B_ERROR;
|
||||
case B_MULTI_GET_MIX :
|
||||
TRACE("B_MULTI_GET_MIX\n");
|
||||
return ice1712_get_mix((ice1712*)cookie, (multi_mix_value_info *)arg);
|
||||
return ice1712_get_mix((ice1712*)cookie,
|
||||
(multi_mix_value_info *)arg);
|
||||
case B_MULTI_SET_MIX :
|
||||
TRACE("B_MULTI_SET_MIX\n");
|
||||
return ice1712_set_mix((ice1712*)cookie, (multi_mix_value_info *)arg);
|
||||
return ice1712_set_mix((ice1712*)cookie,
|
||||
(multi_mix_value_info *)arg);
|
||||
case B_MULTI_LIST_MIX_CHANNELS :
|
||||
TRACE("B_MULTI_LIST_MIX_CHANNELS\n");
|
||||
return ice1712_list_mix_channels((ice1712*)cookie, (multi_mix_channel_info *)arg);
|
||||
return ice1712_list_mix_channels((ice1712*)cookie,
|
||||
(multi_mix_channel_info *)arg);
|
||||
case B_MULTI_LIST_MIX_CONTROLS :
|
||||
TRACE("B_MULTI_LIST_MIX_CONTROLS\n");
|
||||
return ice1712_list_mix_controls((ice1712*)cookie, (multi_mix_control_info *)arg);
|
||||
return ice1712_list_mix_controls((ice1712*)cookie,
|
||||
(multi_mix_control_info *)arg);
|
||||
case B_MULTI_LIST_MIX_CONNECTIONS :
|
||||
TRACE("B_MULTI_LIST_MIX_CONNECTIONS\n");
|
||||
return ice1712_list_mix_connections((ice1712*)cookie, (multi_mix_connection_info *)arg);
|
||||
return ice1712_list_mix_connections((ice1712*)cookie,
|
||||
(multi_mix_connection_info *)arg);
|
||||
case B_MULTI_GET_BUFFERS :
|
||||
TRACE("B_MULTI_GET_BUFFERS\n");
|
||||
return ice1712_get_buffers((ice1712*)cookie, (multi_buffer_list*)arg);
|
||||
return ice1712_get_buffers((ice1712*)cookie,
|
||||
(multi_buffer_list*)arg);
|
||||
case B_MULTI_SET_BUFFERS :
|
||||
TRACE("B_MULTI_SET_BUFFERS\n");
|
||||
return B_ERROR;
|
||||
@ -573,7 +593,8 @@ ice_1712_control(void *cookie, uint32 op, void *arg, size_t len)
|
||||
return B_ERROR;
|
||||
case B_MULTI_BUFFER_EXCHANGE :
|
||||
// TRACE("B_MULTI_BUFFER_EXCHANGE\n");
|
||||
return ice1712_buffer_exchange((ice1712*)cookie, (multi_buffer_info *)arg);
|
||||
return ice1712_buffer_exchange((ice1712*)cookie,
|
||||
(multi_buffer_info *)arg);
|
||||
case B_MULTI_BUFFER_FORCE_STOP :
|
||||
TRACE("B_MULTI_BUFFER_FORCE_STOP\n");
|
||||
return ice1712_buffer_force_stop((ice1712*)cookie);
|
||||
@ -613,7 +634,8 @@ ice_1712_read(void *cookie, off_t position, void *buf, size_t *num_bytes)
|
||||
|
||||
|
||||
static status_t
|
||||
ice_1712_write(void *cookie, off_t position, const void *buffer, size_t *num_bytes)
|
||||
ice_1712_write(void *cookie, off_t position, const void *buffer,
|
||||
size_t *num_bytes)
|
||||
{
|
||||
TRACE("===write()===\n");
|
||||
*num_bytes = 0;
|
||||
@ -674,57 +696,22 @@ find_device(const char * name)
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
status_t
|
||||
load_settings(ice1712 *ice)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 10; i++) {
|
||||
ice->settings.playback[i].volume = -10.5;
|
||||
ice->settings.playback[i].mute = false;
|
||||
}
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
ice->settings.record[i].volume = -10.5;
|
||||
ice->settings.record[i].mute = false;
|
||||
}
|
||||
|
||||
ice->settings.clock = 0;
|
||||
ice->settings.sample_rate = 3;
|
||||
ice->settings.buffer_size = 3;
|
||||
ice->settings.debug_mode = 0;
|
||||
|
||||
//S/PDIF Settings
|
||||
ice->settings.out_format = 0;
|
||||
ice->settings.emphasis = 0;
|
||||
ice->settings.copy_mode = 0;
|
||||
|
||||
return apply_settings(ice);
|
||||
}
|
||||
|
||||
|
||||
status_t
|
||||
save_settings(ice1712 *ice)
|
||||
{
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
#define ICE1712_MUTE_VALUE (0x7F)
|
||||
|
||||
status_t
|
||||
apply_settings(ice1712 *card)
|
||||
applySettings(ice1712 *card)
|
||||
{
|
||||
int i;
|
||||
uint16 val;
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
for (i = 0; i < MAX_HARDWARE_VOLUME; i++) {
|
||||
//Select the channel
|
||||
write_mt_uint8(card, MT_VOLUME_CONTROL_CHANNEL_INDEX, i);
|
||||
|
||||
if (card->settings.playback[i].mute) {
|
||||
if (card->settings.Playback[i].Mute == true) {
|
||||
val = (ICE1712_MUTE_VALUE << 0) | (ICE1712_MUTE_VALUE << 8);
|
||||
} else {
|
||||
unsigned char volume = card->settings.playback[i].volume / -1.5;
|
||||
unsigned char volume = card->settings.Playback[i].Volume / -1.5;
|
||||
if (i & 1) {//a right channel
|
||||
val = ICE1712_MUTE_VALUE << 0; //Mute left volume
|
||||
val |= volume << 8;
|
||||
@ -735,18 +722,18 @@ apply_settings(ice1712 *card)
|
||||
}
|
||||
|
||||
write_mt_uint16(card, MT_LR_VOLUME_CONTROL, val);
|
||||
if (ICE1712_VERY_VERBOSE)
|
||||
TRACE("Apply Settings %d : 0x%x\n", i, val);
|
||||
TRACE_VV("Apply Settings %d : 0x%x\n", i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
for (i = 0; i < MAX_HARDWARE_VOLUME; i++) {
|
||||
//Select the channel
|
||||
write_mt_uint8(card, MT_VOLUME_CONTROL_CHANNEL_INDEX, i + 10);
|
||||
write_mt_uint8(card, MT_VOLUME_CONTROL_CHANNEL_INDEX,
|
||||
i + MAX_HARDWARE_VOLUME);
|
||||
|
||||
if (card->settings.record[i].mute == true) {
|
||||
if (card->settings.Record[i].Mute == true) {
|
||||
val = (ICE1712_MUTE_VALUE << 0) | (ICE1712_MUTE_VALUE << 8);
|
||||
} else {
|
||||
unsigned char volume = card->settings.record[i].volume / -1.5;
|
||||
unsigned char volume = card->settings.Record[i].Volume / -1.5;
|
||||
if (i & 1) {//a right channel
|
||||
val = ICE1712_MUTE_VALUE << 0; //Mute left volume
|
||||
val |= volume << 8;
|
||||
@ -757,9 +744,10 @@ apply_settings(ice1712 *card)
|
||||
}
|
||||
|
||||
write_mt_uint16(card, MT_LR_VOLUME_CONTROL, val);
|
||||
TRACE_VV("Apply Settings %d : 0x%x\n", i, val);
|
||||
}
|
||||
|
||||
//Output selection
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
@ -1,266 +1,265 @@
|
||||
/*
|
||||
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
|
||||
*
|
||||
* Copyright (c) 2002, Jerome Duval (jerome.duval@free.fr)
|
||||
* Copyright (c) 2003, Marcus Overhagen (marcus@overhagen.de)
|
||||
* Copyright (c) 2007, Jerome Leveque (leveque.jerome@neuf.fr)
|
||||
*
|
||||
* All rights reserved
|
||||
* Distributed under the terms of the MIT license.
|
||||
*/
|
||||
|
||||
#ifndef _ICE1712_H_
|
||||
#define _ICE1712_H_
|
||||
|
||||
#include <PCI.h>
|
||||
|
||||
#define DRIVER_NAME "ice1712"
|
||||
#define VERSION "0.4"
|
||||
|
||||
#define ICE1712_VENDOR_ID 0x1412
|
||||
#define ICE1712_DEVICE_ID 0x1712
|
||||
|
||||
typedef enum product_t {
|
||||
ICE1712_SUBDEVICE_DELTA1010 = 0x121430d6,
|
||||
ICE1712_SUBDEVICE_DELTADIO2496 = 0x121431d6,
|
||||
ICE1712_SUBDEVICE_DELTA66 = 0x121432d6,
|
||||
ICE1712_SUBDEVICE_DELTA44 = 0x121433d6,
|
||||
ICE1712_SUBDEVICE_AUDIOPHILE_2496 = 0x121434d6,
|
||||
ICE1712_SUBDEVICE_DELTA410 = 0x121438d6,
|
||||
ICE1712_SUBDEVICE_DELTA1010LT = 0x12143bd6,
|
||||
ICE1712_SUBDEVICE_VX442 = 0x12143cd6,
|
||||
} product_t;
|
||||
|
||||
#define NUM_CARDS 4
|
||||
#define MAX_ADC 12 // + the output of the Digital mixer
|
||||
#define MAX_DAC 10
|
||||
#define SWAPPING_BUFFERS 2
|
||||
#define SAMPLE_SIZE 4
|
||||
#define MIN_BUFFER_FRAMES 256
|
||||
#define MAX_BUFFER_FRAMES 2048
|
||||
|
||||
#define PLAYBACK_BUFFER_SIZE (MAX_BUFFER_FRAMES * MAX_DAC * SAMPLE_SIZE)
|
||||
#define RECORD_BUFFER_SIZE (MAX_BUFFER_FRAMES * MAX_ADC * SAMPLE_SIZE)
|
||||
|
||||
#define PLAYBACK_BUFFER_TOTAL_SIZE (PLAYBACK_BUFFER_SIZE * SWAPPING_BUFFERS)
|
||||
#define RECORD_BUFFER_TOTAL_SIZE (RECORD_BUFFER_SIZE * SWAPPING_BUFFERS)
|
||||
|
||||
#define SPDIF_LEFT 8
|
||||
#define SPDIF_RIGHT 9
|
||||
#define MIXER_OUT_LEFT 10
|
||||
#define MIXER_OUT_RIGHT 11
|
||||
|
||||
|
||||
typedef enum {
|
||||
NO_IN_NO_OUT = 0,
|
||||
NO_IN_YES_OUT = 1,
|
||||
YES_IN_NO_OUT = 2,
|
||||
YES_IN_YES_OUT = 3,
|
||||
} _spdif_config_ ;
|
||||
|
||||
|
||||
typedef struct _midi_dev {
|
||||
struct _ice1712_ *card;
|
||||
void *driver;
|
||||
void *cookie;
|
||||
int32 count;
|
||||
char name[64];
|
||||
} midi_dev;
|
||||
|
||||
|
||||
typedef struct _codec_commlines
|
||||
{
|
||||
uint8 clock;
|
||||
uint8 data_in;
|
||||
uint8 data_out;
|
||||
uint8 cs_mask; //a Mask for removing all Chip select
|
||||
uint8 reserved[4];
|
||||
} codec_comm_lines;
|
||||
|
||||
|
||||
typedef struct channel_volume
|
||||
{
|
||||
float volume;
|
||||
bool mute;
|
||||
} channel_volume;
|
||||
|
||||
|
||||
typedef struct ice1712_settings
|
||||
{
|
||||
channel_volume playback[10]; //Can't change the volume of the digital mixer
|
||||
channel_volume record[10];
|
||||
|
||||
//General Settings
|
||||
uint8 clock; //an index
|
||||
uint8 sample_rate; //an index
|
||||
uint8 buffer_size; //an index
|
||||
uint8 debug_mode; //an index for debugging
|
||||
|
||||
//S/PDif Settings
|
||||
uint8 out_format; //an index
|
||||
uint8 emphasis; //an index
|
||||
uint8 copy_mode; //an index
|
||||
|
||||
uint8 reserved[32];
|
||||
} ice1712_settings;
|
||||
|
||||
|
||||
typedef struct ice1712
|
||||
{
|
||||
uint32 irq;
|
||||
pci_info info;
|
||||
char name[128];
|
||||
|
||||
midi_dev midi_interf[2];
|
||||
|
||||
uint32 Controller; //PCI_10
|
||||
uint32 DDMA; //PCI_14
|
||||
uint32 DMA_Path; //PCI_18
|
||||
uint32 Multi_Track; //PCI_1C
|
||||
|
||||
uint8 eeprom_data[32];
|
||||
|
||||
int8 nb_ADC; //Mono Channel
|
||||
int8 nb_DAC; //Mono Channel
|
||||
_spdif_config_ spdif_config;
|
||||
int8 nb_MPU401;
|
||||
|
||||
product_t product;
|
||||
|
||||
//We hope all manufacturers will use same communication lines for speaking with codec
|
||||
codec_comm_lines commlines;
|
||||
|
||||
uint32 buffer;
|
||||
bigtime_t played_time;
|
||||
uint32 buffer_size; //in frames
|
||||
uint32 frames_count;
|
||||
|
||||
//Output
|
||||
area_id mem_id_pb;
|
||||
void *phys_addr_pb, *log_addr_pb;
|
||||
uint8 total_output_channels;
|
||||
|
||||
//Input
|
||||
area_id mem_id_rec;
|
||||
void *phys_addr_rec, *log_addr_rec;
|
||||
uint8 total_input_channels;
|
||||
|
||||
sem_id buffer_ready_sem;
|
||||
|
||||
uint8 sampling_rate; //in the format of the register
|
||||
uint32 lock_source;
|
||||
|
||||
ice1712_settings settings;
|
||||
} ice1712;
|
||||
|
||||
|
||||
status_t apply_settings(ice1712 *card);
|
||||
|
||||
|
||||
//For midi.c
|
||||
extern int32 num_cards;
|
||||
extern ice1712 cards[NUM_CARDS];
|
||||
|
||||
//???????
|
||||
#define GPIO_SPDIF_STATUS 0x02 //Status
|
||||
#define GPIO_SPDIF_CCLK 0x04 //data Clock
|
||||
#define GPIO_SPDIF_DOUT 0x08 //data output
|
||||
|
||||
//For Delta 66 / Delta 44
|
||||
#define DELTA66_DOUT 0x10 // data output
|
||||
#define DELTA66_CLK 0x20 // clock
|
||||
#define DELTA66_CODEC_CS_0 0x40 // AK4524 #0
|
||||
#define DELTA66_CODEC_CS_1 0x80 // AK4524 #1
|
||||
|
||||
//For AudioPhile 2496 / Delta 410
|
||||
#define AP2496_CLK 0x02 // clock
|
||||
#define AP2496_DIN 0x04 // data input
|
||||
#define AP2496_DOUT 0x08 // data output
|
||||
#define AP2496_SPDIF_CS 0x10 // CS8427 chip select
|
||||
#define AP2496_CODEC_CS 0x20 // AK4528 chip select
|
||||
|
||||
//For Delta 1010 LT
|
||||
#define DELTA1010LT_CLK 0x02 // clock
|
||||
#define DELTA1010LT_DIN 0x04 // data input
|
||||
#define DELTA1010LT_DOUT 0x08 // data output
|
||||
#define DELTA1010LT_CODEC_CS_0 0x00 // AK4524 #0
|
||||
#define DELTA1010LT_CODEC_CS_1 0x10 // AK4524 #1
|
||||
#define DELTA1010LT_CODEC_CS_2 0x20 // AK4524 #2
|
||||
#define DELTA1010LT_CODEC_CS_3 0x30 // AK4524 #3
|
||||
#define DELTA1010LT_SPDIF_CS 0x40 // CS8427
|
||||
#define DELTA1010LT_CS_NONE 0x50 // All CS deselected
|
||||
|
||||
//For VX442
|
||||
#define VX442_CLK 0x02 // clock
|
||||
#define VX442_DIN 0x04 // data input
|
||||
#define VX442_DOUT 0x08 // data output
|
||||
#define VX442_SPDIF_CS 0x10 // CS8427
|
||||
#define VX442_CODEC_CS_0 0x20 // ?? #0
|
||||
#define VX442_CODEC_CS_1 0x40 // ?? #1
|
||||
|
||||
#define GPIO_I2C_DELAY 5 //Clock Delay for writing I2C data throw GPIO
|
||||
|
||||
//Register definition for the AK45xx codec (xx = 24 or 28)
|
||||
#define AK45xx_CHIP_ADDRESS 0x02 //Chip address of the codec
|
||||
#define AK45xx_RESET_REGISTER 0x01
|
||||
#define AK45xx_CLOCK_FORMAT_REGISTER 0x02
|
||||
//Other register are not defined cause they are not used, I'm very lazy...
|
||||
|
||||
//Register definition for the CS84xx codec (xx = 27)
|
||||
#define CS84xx_CHIP_ADDRESS 0x10 //Chip address of the codec
|
||||
#define CS84xx_CONTROL_1_PORT_REG 0x01
|
||||
#define CS84xx_CONTROL_2_PORT_REG 0x02
|
||||
#define CS84xx_DATA_FLOW_CONTROL_REG 0x03
|
||||
#define CS84xx_CLOCK_SOURCE_REG 0x04
|
||||
#define CS84xx_SERIAL_INPUT_FORMAT_REG 0x05
|
||||
#define CS84xx_SERIAL_OUTPUT_FORMAT_REG 0x06
|
||||
|
||||
#define CS84xx_VERSION_AND_CHIP_ID 0x7F
|
||||
//Other register are not defined cause they are not used, I'm very lazy...
|
||||
|
||||
|
||||
/* A default switch for all suported product
|
||||
switch (card->product)
|
||||
{
|
||||
case ICE1712_SUBDEVICE_DELTA1010 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTADIO2496 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA66 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA44 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_AUDIOPHILE :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA410 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA1010LT :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_VX442 :
|
||||
break;
|
||||
}
|
||||
*/
|
||||
|
||||
//This map comes from ALSA sound drivers
|
||||
#define E2PROM_MAP_SUBVENDOR_LOW 0x00
|
||||
#define E2PROM_MAP_SUBVENDOR_HIGH 0x01
|
||||
#define E2PROM_MAP_SUBDEVICE_LOW 0x02
|
||||
#define E2PROM_MAP_SUBDEVICE_HIGH 0x03
|
||||
#define E2PROM_MAP_SIZE 0x04
|
||||
#define E2PROM_MAP_VERSION 0x05
|
||||
#define E2PROM_MAP_CONFIG 0x06
|
||||
#define E2PROM_MAP_ACL 0x07
|
||||
#define E2PROM_MAP_I2S 0x08
|
||||
#define E2PROM_MAP_SPDIF 0x09
|
||||
#define E2PROM_MAP_GPIOMASK 0x0A
|
||||
#define E2PROM_MAP_GPIOSTATE 0x0B
|
||||
#define E2PROM_MAP_GPIODIR 0x0C
|
||||
#define E2PROM_MAP_AC97MAIN 0x0D
|
||||
#define E2PROM_MAP_AC97PCM 0x0F
|
||||
#define E2PROM_MAP_AC97REC 0x11
|
||||
#define E2PROM_MAP_AC97REC_SOURCE 0x13
|
||||
#define E2PROM_MAP_DAC_ID 0x14
|
||||
#define E2PROM_MAP_ADC_ID 0x18
|
||||
#define E2PROM_MAP_EXTRA 0x1C
|
||||
|
||||
#endif
|
||||
/*
|
||||
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
|
||||
*
|
||||
* Copyright (c) 2002, Jerome Duval (jerome.duval@free.fr)
|
||||
* Copyright (c) 2003, Marcus Overhagen (marcus@overhagen.de)
|
||||
* Copyright (c) 2007, Jerome Leveque (leveque.jerome@neuf.fr)
|
||||
*
|
||||
* All rights reserved
|
||||
* Distributed under the terms of the MIT license.
|
||||
*/
|
||||
|
||||
#ifndef _ICE1712_H_
|
||||
#define _ICE1712_H_
|
||||
|
||||
#include <PCI.h>
|
||||
#include "hmulti_audio.h"
|
||||
|
||||
#define DRIVER_NAME "ice1712"
|
||||
#define VERSION "0.4"
|
||||
|
||||
#define ICE1712_VENDOR_ID 0x1412
|
||||
#define ICE1712_DEVICE_ID 0x1712
|
||||
|
||||
typedef enum product_t {
|
||||
ICE1712_SUBDEVICE_DELTA1010 = 0x121430d6,
|
||||
ICE1712_SUBDEVICE_DELTADIO2496 = 0x121431d6,
|
||||
ICE1712_SUBDEVICE_DELTA66 = 0x121432d6,
|
||||
ICE1712_SUBDEVICE_DELTA44 = 0x121433d6,
|
||||
ICE1712_SUBDEVICE_AUDIOPHILE_2496 = 0x121434d6,
|
||||
ICE1712_SUBDEVICE_DELTA410 = 0x121438d6,
|
||||
ICE1712_SUBDEVICE_DELTA1010LT = 0x12143bd6,
|
||||
ICE1712_SUBDEVICE_VX442 = 0x12143cd6,
|
||||
} product_t;
|
||||
|
||||
#define NUM_CARDS 4
|
||||
#define MAX_ADC 12 // + the output of the Digital mixer
|
||||
#define MAX_DAC 10
|
||||
#define SWAPPING_BUFFERS 2
|
||||
#define SAMPLE_SIZE 4
|
||||
#define MIN_BUFFER_FRAMES 64
|
||||
#define MAX_BUFFER_FRAMES 2048
|
||||
|
||||
#define MAX_HARDWARE_VOLUME 10
|
||||
|
||||
#define PLAYBACK_BUFFER_SIZE (MAX_BUFFER_FRAMES * MAX_DAC * SAMPLE_SIZE)
|
||||
#define RECORD_BUFFER_SIZE (MAX_BUFFER_FRAMES * MAX_ADC * SAMPLE_SIZE)
|
||||
|
||||
#define PLAYBACK_BUFFER_TOTAL_SIZE (PLAYBACK_BUFFER_SIZE * SWAPPING_BUFFERS)
|
||||
#define RECORD_BUFFER_TOTAL_SIZE (RECORD_BUFFER_SIZE * SWAPPING_BUFFERS)
|
||||
|
||||
#define SPDIF_LEFT 8
|
||||
#define SPDIF_RIGHT 9
|
||||
#define MIXER_OUT_LEFT 10
|
||||
#define MIXER_OUT_RIGHT 11
|
||||
|
||||
typedef enum {
|
||||
NO_IN_NO_OUT = 0,
|
||||
NO_IN_YES_OUT = 1,
|
||||
YES_IN_NO_OUT = 2,
|
||||
YES_IN_YES_OUT = 3,
|
||||
} _spdif_config_ ;
|
||||
|
||||
typedef struct _midi_dev {
|
||||
struct _ice1712_ *card;
|
||||
void *driver;
|
||||
void *cookie;
|
||||
int32 count;
|
||||
char name[64];
|
||||
} midi_dev;
|
||||
|
||||
typedef struct _codecCommLines
|
||||
{
|
||||
uint8 clock;
|
||||
uint8 data_in;
|
||||
uint8 data_out;
|
||||
uint8 cs_mask; //a Mask for removing all Chip select
|
||||
uint8 reserved[4];
|
||||
} codecCommLines;
|
||||
|
||||
typedef struct ChannelVolume
|
||||
{
|
||||
float Volume;
|
||||
bool Mute;
|
||||
} ChannelVolume;
|
||||
|
||||
typedef struct Ice1712_Settings
|
||||
{
|
||||
ChannelVolume Playback[MAX_HARDWARE_VOLUME];
|
||||
ChannelVolume Record[MAX_HARDWARE_VOLUME];
|
||||
|
||||
//General Settings
|
||||
uint8 Clock; //an index
|
||||
uint8 BufferSize; //an index
|
||||
uint8 DebugMode; //an index for debugging
|
||||
|
||||
//S/PDif Settings
|
||||
uint8 OutFormat; //an index
|
||||
uint8 Emphasis; //an index
|
||||
uint8 CopyMode; //an index
|
||||
|
||||
//Output settings
|
||||
uint8 Output[5]; //an index
|
||||
|
||||
uint8 Reserved[32];
|
||||
} Ice1712_Settings;
|
||||
|
||||
typedef struct ice1712
|
||||
{
|
||||
uint32 irq;
|
||||
pci_info info;
|
||||
char name[128];
|
||||
|
||||
midi_dev midi_interf[2];
|
||||
|
||||
uint32 Controller; //PCI_10
|
||||
uint32 DDMA; //PCI_14
|
||||
uint32 DMA_Path; //PCI_18
|
||||
uint32 Multi_Track; //PCI_1C
|
||||
|
||||
uint8 eeprom_data[32];
|
||||
|
||||
int8 nb_ADC; //Mono Channel
|
||||
int8 nb_DAC; //Mono Channel
|
||||
_spdif_config_ spdif_config;
|
||||
int8 nb_MPU401;
|
||||
|
||||
product_t product;
|
||||
|
||||
//We hope all manufacturers will use same
|
||||
//communication lines for speaking with codec
|
||||
codecCommLines CommLines;
|
||||
|
||||
uint32 buffer;
|
||||
bigtime_t played_time;
|
||||
uint32 buffer_size; //in frames
|
||||
uint32 frames_count;
|
||||
|
||||
//Output
|
||||
area_id mem_id_pb;
|
||||
void *phys_addr_pb, *log_addr_pb;
|
||||
uint8 total_output_channels;
|
||||
|
||||
//Input
|
||||
area_id mem_id_rec;
|
||||
void *phys_addr_rec, *log_addr_rec;
|
||||
uint8 total_input_channels;
|
||||
|
||||
sem_id buffer_ready_sem;
|
||||
|
||||
uint8 sampling_rate; //in the format of the register
|
||||
uint32 lock_source;
|
||||
|
||||
Ice1712_Settings settings;
|
||||
} ice1712;
|
||||
|
||||
status_t applySettings(ice1712 *card);
|
||||
|
||||
//For midi.c
|
||||
extern int32 num_cards;
|
||||
extern ice1712 cards[NUM_CARDS];
|
||||
|
||||
//???????
|
||||
#define GPIO_SPDIF_STATUS 0x02 //Status
|
||||
#define GPIO_SPDIF_CCLK 0x04 //data Clock
|
||||
#define GPIO_SPDIF_DOUT 0x08 //data output
|
||||
|
||||
//For Delta 66 / Delta 44
|
||||
#define DELTA66_DOUT 0x10 // data output
|
||||
#define DELTA66_CLK 0x20 // clock
|
||||
#define DELTA66_CODEC_CS_0 0x40 // AK4524 #0
|
||||
#define DELTA66_CODEC_CS_1 0x80 // AK4524 #1
|
||||
|
||||
//For AudioPhile 2496 / Delta 410
|
||||
#define AP2496_CLK 0x02 // clock
|
||||
#define AP2496_DIN 0x04 // data input
|
||||
#define AP2496_DOUT 0x08 // data output
|
||||
#define AP2496_SPDIF_CS 0x10 // CS8427 chip select
|
||||
#define AP2496_CODEC_CS 0x20 // AK4528 chip select
|
||||
|
||||
//For Delta 1010 LT
|
||||
#define DELTA1010LT_CLK 0x02 // clock
|
||||
#define DELTA1010LT_DIN 0x04 // data input
|
||||
#define DELTA1010LT_DOUT 0x08 // data output
|
||||
#define DELTA1010LT_CODEC_CS_0 0x00 // AK4524 #0
|
||||
#define DELTA1010LT_CODEC_CS_1 0x10 // AK4524 #1
|
||||
#define DELTA1010LT_CODEC_CS_2 0x20 // AK4524 #2
|
||||
#define DELTA1010LT_CODEC_CS_3 0x30 // AK4524 #3
|
||||
#define DELTA1010LT_SPDIF_CS 0x40 // CS8427
|
||||
#define DELTA1010LT_CS_NONE 0x50 // All CS deselected
|
||||
|
||||
//For VX442
|
||||
#define VX442_CLK 0x02 // clock
|
||||
#define VX442_DIN 0x04 // data input
|
||||
#define VX442_DOUT 0x08 // data output
|
||||
#define VX442_SPDIF_CS 0x10 // CS8427
|
||||
#define VX442_CODEC_CS_0 0x20 // ?? #0
|
||||
#define VX442_CODEC_CS_1 0x40 // ?? #1
|
||||
|
||||
#define GPIO_I2C_DELAY 5 //Clock Delay for writing
|
||||
//I2C data throw GPIO
|
||||
|
||||
//Register definition for the AK45xx codec (xx = 24 or 28)
|
||||
#define AK45xx_CHIP_ADDRESS 0x02 //Chip address of the codec
|
||||
#define AK45xx_RESET_REGISTER 0x01
|
||||
#define AK45xx_CLOCK_FORMAT_REGISTER 0x02
|
||||
//Other register are not defined cause they are not used, I'm very lazy...
|
||||
|
||||
//Register definition for the CS84xx codec (xx = 27)
|
||||
#define CS84xx_CHIP_ADDRESS 0x10 //Chip address of the codec
|
||||
#define CS84xx_CONTROL_1_PORT_REG 0x01
|
||||
#define CS84xx_CONTROL_2_PORT_REG 0x02
|
||||
#define CS84xx_DATA_FLOW_CONTROL_REG 0x03
|
||||
#define CS84xx_CLOCK_SOURCE_REG 0x04
|
||||
#define CS84xx_SERIAL_INPUT_FORMAT_REG 0x05
|
||||
#define CS84xx_SERIAL_OUTPUT_FORMAT_REG 0x06
|
||||
|
||||
#define CS84xx_VERSION_AND_CHIP_ID 0x7F
|
||||
//Other register are not defined cause they are not used, I'm very lazy...
|
||||
|
||||
|
||||
/* A default switch for all suported product
|
||||
switch (card->product)
|
||||
{
|
||||
case ICE1712_SUBDEVICE_DELTA1010 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTADIO2496 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA66 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA44 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_AUDIOPHILE :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA410 :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_DELTA1010LT :
|
||||
break;
|
||||
case ICE1712_SUBDEVICE_VX442 :
|
||||
break;
|
||||
}
|
||||
*/
|
||||
|
||||
//This map comes from ALSA sound drivers
|
||||
#define E2PROM_MAP_SUBVENDOR_LOW 0x00
|
||||
#define E2PROM_MAP_SUBVENDOR_HIGH 0x01
|
||||
#define E2PROM_MAP_SUBDEVICE_LOW 0x02
|
||||
#define E2PROM_MAP_SUBDEVICE_HIGH 0x03
|
||||
#define E2PROM_MAP_SIZE 0x04
|
||||
#define E2PROM_MAP_VERSION 0x05
|
||||
#define E2PROM_MAP_CONFIG 0x06
|
||||
#define E2PROM_MAP_ACL 0x07
|
||||
#define E2PROM_MAP_I2S 0x08
|
||||
#define E2PROM_MAP_SPDIF 0x09
|
||||
#define E2PROM_MAP_GPIOMASK 0x0A
|
||||
#define E2PROM_MAP_GPIOSTATE 0x0B
|
||||
#define E2PROM_MAP_GPIODIR 0x0C
|
||||
#define E2PROM_MAP_AC97MAIN 0x0D
|
||||
#define E2PROM_MAP_AC97PCM 0x0F
|
||||
#define E2PROM_MAP_AC97REC 0x11
|
||||
#define E2PROM_MAP_AC97REC_SOURCE 0x13
|
||||
#define E2PROM_MAP_DAC_ID 0x14
|
||||
#define E2PROM_MAP_ADC_ID 0x18
|
||||
#define E2PROM_MAP_EXTRA 0x1C
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,167 +1,167 @@
|
||||
/*
|
||||
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
|
||||
*
|
||||
* Copyright (c) 2007, Jerome Leveque (leveque.jerome@neuf.fr)
|
||||
*
|
||||
* All rights reserved
|
||||
* Distributed under the terms of the MIT license.
|
||||
*/
|
||||
|
||||
#ifndef _ICE1712_REG_H_
|
||||
#define _ICE1712_REG_H_
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//PCI Interface and Configuration Registers (Page 3.1)
|
||||
//Table 3.1
|
||||
/*
|
||||
#define PCI_VENDOR_ID 0x00 //2 bytes
|
||||
#define PCI_DEVICE_ID 0x02 //2 bytes
|
||||
#define PCI_COMMAND 0x04 //2 bytes
|
||||
#define PCI_DEVICE_STATUS 0x06 //2 bytes
|
||||
#define PCI_REVISION_ID 0x08 //1 byte
|
||||
#define PCI_CLASS_CODE 0x0A //2 bytes
|
||||
#define PCI_LATENCY_TIMER 0x0D //1 byte
|
||||
#define PCI_HEADER_TYPE 0x0E //1 byte
|
||||
#define PCI_BIST 0x0F //1 byte
|
||||
#define PCI_CONTROLLER_BASE_AD 0x10 //4 bytes
|
||||
#define PCI_DDMA_BASE_AD 0x14 //4 bytes
|
||||
#define PCI_DMA_BASE_AD 0x18 //4 bytes
|
||||
#define PCI_MULTI_BASE_AD 0x1C //4 bytes
|
||||
#define PCI_SUB_VENDOR_ID 0x2C //2 bytes
|
||||
#define PCI_SUB_SYSTEM_ID 0x2E //2 bytes
|
||||
#define PCI_CAPABILITY_POINTER 0x34 //4 bytes
|
||||
#define PCI_INT_PIN_LINE 0x3C //2 bytes
|
||||
#define PCI_LATENCY_GRANT 0x3E //2 bytes
|
||||
#define PCI_LEGACY_AUDIO_CONTROL 0x40 //2 bytes
|
||||
#define PCI_LEGACY_CONF_CONTROL 0x42 //2 bytes
|
||||
#define PCI_HARD_CONF_CONTROL 0x60 //4 bytes
|
||||
#define PCI_CAPABILITY_ID 0x80 //1 byte
|
||||
#define PCI_NEXT_ITEM_POINTER 0x81 //1 byte
|
||||
#define PCI_POWER_CAPABILITY 0x82 //2 bytes
|
||||
#define PCI_POWER_CONTROL_STATUS 0x84 //2 bytes
|
||||
#define PCI_PMCSR_EXT_DATA 0x86 //2 bytes
|
||||
*/
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//CCSxx Controller Register Map (Page 4.3)
|
||||
//Table 4.2
|
||||
#define CCS_CONTROL_STATUS 0x00 //1 byte
|
||||
#define CCS_INTERRUPT_MASK 0x01 //1 byte
|
||||
#define CCS_INTERRUPT_STATUS 0x02 //1 byte
|
||||
#define CCS_CCI_INDEX 0x03 //1 byte
|
||||
#define CCS_CCI_DATA 0x04 //1 byte
|
||||
#define CCS_NMI_STATUS_1 0x05 //1 byte
|
||||
#define CCS_NMI_DATA 0x06 //1 byte
|
||||
#define CCS_NMI_INDEX 0x07 //1 byte
|
||||
#define CCS_CONS_AC97_INDEX 0x08 //1 byte
|
||||
#define CCS_CONS_AC97_COMMAND_STATUS 0x09 //1 byte
|
||||
#define CCS_CONS_AC97_DATA 0x0A //2 bytes
|
||||
#define CCS_MIDI_1_DATA 0x0C //1 byte
|
||||
#define CCS_MIDI_1_COMMAND_STATUS 0x0D //1 byte
|
||||
#define CCS_NMI_STATUS_2 0x0E //1 byte
|
||||
#define CCS_GAME_PORT 0x0F //1 byte
|
||||
#define CCS_I2C_DEV_ADDRESS 0x10 //1 byte
|
||||
#define CCS_I2C_BYTE_ADDRESS 0x11 //1 byte
|
||||
#define CCS_I2C_DATA 0x12 //1 byte
|
||||
#define CCS_I2C_CONTROL_STATUS 0x13 //1 byte
|
||||
#define CCS_CONS_DMA_BASE_ADDRESS 0x14 //4 bytes
|
||||
#define CCS_CONS_DMA_COUNT_ADDRESS 0x18 //2 bytes
|
||||
#define CCS_SERR_SHADOW 0x1B //1 byte
|
||||
#define CCS_MIDI_2_DATA 0x1C //1 byte
|
||||
#define CCS_MIDI_2_COMMAND_STATUS 0x1D //1 byte
|
||||
#define CCS_TIMER 0x1E //2 bytes
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Controller Indexed Register (Page 4.12)
|
||||
#define CCI_PB_TERM_COUNT_HI 0x00 //1 byte
|
||||
#define CCI_PB_TERM_COUNT_LO 0x01 //1 byte
|
||||
#define CCI_PB_CONTROL 0x02 //1 byte
|
||||
#define CCI_PB_LEFT_VOLUME 0x03 //1 byte
|
||||
#define CCI_PB_RIGHT_VOLUME 0x04 //1 byte
|
||||
#define CCI_SOFT_VOLUME 0x05 //1 byte
|
||||
#define CCI_PB_SAMPLING_RATE_LO 0x06 //1 byte
|
||||
#define CCI_PB_SAMPLING_RATE_MI 0x07 //1 byte
|
||||
#define CCI_PB_SAMPLING_RATE_HI 0x08 //1 byte
|
||||
#define CCI_REC_TERM_COUNT_HI 0x10 //1 byte
|
||||
#define CCI_REC_TERM_COUNT_LO 0x11 //1 byte
|
||||
#define CCI_REC_CONTROL 0x12 //1 byte
|
||||
#define CCI_GPIO_DATA 0x20 //1 byte
|
||||
#define CCI_GPIO_WRITE_MASK 0x21 //1 byte
|
||||
#define CCI_GPIO_DIRECTION_CONTROL 0x22 //1 byte
|
||||
#define CCI_CONS_POWER_DOWN 0x30 //1 byte
|
||||
#define CCI_MULTI_POWER_DOWN 0x31 //1 byte
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Consumer Section DMA Channel Registers (Page 4.20)
|
||||
//Table 4.4
|
||||
#define DS_DMA_INT_MASK 0x00 //2 bytes
|
||||
#define DS_DMA_INT_STATUS 0x02 //2 bytes
|
||||
#define DS_CHANNEL_DATA 0x04 //4 bytes
|
||||
#define DS_CHANNEL_INDEX 0x08 //1 byte
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Professional Multi-Track Control Registers (Page 4.24)
|
||||
//Table 4.7
|
||||
#define MT_DMA_INT_MASK_STATUS 0x00 //1 byte
|
||||
#define MT_SAMPLING_RATE_SELECT 0x01 //1 byte
|
||||
#define MT_I2S_DATA_FORMAT 0x02 //1 byte
|
||||
#define MT_PROF_AC97_INDEX 0x04 //1 byte
|
||||
#define MT_PROF_AC97_COMMAND_STATUS 0x05 //1 byte
|
||||
#define MT_PROF_AC97_DATA 0x06 //2 bytes
|
||||
#define MT_PROF_PB_DMA_BASE_ADDRESS 0x10 //4 bytes
|
||||
#define MT_PROF_PB_DMA_COUNT_ADDRESS 0x14 //2 bytes
|
||||
#define MT_PROF_PB_DMA_TERM_COUNT 0x16 //2 bytes
|
||||
#define MT_PROF_PB_CONTROL 0x18 //1 byte
|
||||
#define MT_PROF_REC_DMA_BASE_ADDRESS 0x20 //4 bytes
|
||||
#define MT_PROF_REC_DMA_COUNT_ADDRESS 0x24 //2 bytes
|
||||
#define MT_PROF_REC_DMA_TERM_COUNT 0x26 //2 bytes
|
||||
#define MT_PROF_REC_CONTROL 0x28 //1 byte
|
||||
#define MT_ROUTING_CONTROL_PSDOUT 0x30 //2 bytes
|
||||
#define MT_ROUTING_CONTROL_SPDOUT 0x32 //2 bytes
|
||||
#define MT_CAPTURED_DATA 0x34 //4 bytes
|
||||
#define MT_LR_VOLUME_CONTROL 0x38 //2 bytes
|
||||
#define MT_VOLUME_CONTROL_CHANNEL_INDEX 0x3A //1 byte
|
||||
#define MT_VOLUME_CONTROL_RATE 0x3B //1 byte
|
||||
#define MT_MIXER_MONITOR_RETURN 0x3C //1 byte
|
||||
#define MT_PEAK_METER_INDEX 0x3E //1 byte
|
||||
#define MT_PEAK_METER_DATA 0x3F //1 byte
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
#define I2C_EEPROM_ADDRESS_READ 0xA0 //1010 0000
|
||||
#define I2C_EEPROM_ADDRESS_WRITE 0xA1 //1010 0001
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
#define SPDIF_STEREO_IN 0x02 //0000 0010
|
||||
#define SPDIF_STEREO_OUT 0x01 //0000 0001
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
#endif
|
||||
/*
|
||||
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
|
||||
*
|
||||
* Copyright (c) 2007, Jerome Leveque (leveque.jerome@neuf.fr)
|
||||
*
|
||||
* All rights reserved
|
||||
* Distributed under the terms of the MIT license.
|
||||
*/
|
||||
|
||||
#ifndef _ICE1712_REG_H_
|
||||
#define _ICE1712_REG_H_
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//PCI Interface and Configuration Registers (Page 3.1)
|
||||
//Table 3.1
|
||||
/*
|
||||
#define PCI_VENDOR_ID 0x00 //2 bytes
|
||||
#define PCI_DEVICE_ID 0x02 //2 bytes
|
||||
#define PCI_COMMAND 0x04 //2 bytes
|
||||
#define PCI_DEVICE_STATUS 0x06 //2 bytes
|
||||
#define PCI_REVISION_ID 0x08 //1 byte
|
||||
#define PCI_CLASS_CODE 0x0A //2 bytes
|
||||
#define PCI_LATENCY_TIMER 0x0D //1 byte
|
||||
#define PCI_HEADER_TYPE 0x0E //1 byte
|
||||
#define PCI_BIST 0x0F //1 byte
|
||||
#define PCI_CONTROLLER_BASE_AD 0x10 //4 bytes
|
||||
#define PCI_DDMA_BASE_AD 0x14 //4 bytes
|
||||
#define PCI_DMA_BASE_AD 0x18 //4 bytes
|
||||
#define PCI_MULTI_BASE_AD 0x1C //4 bytes
|
||||
#define PCI_SUB_VENDOR_ID 0x2C //2 bytes
|
||||
#define PCI_SUB_SYSTEM_ID 0x2E //2 bytes
|
||||
#define PCI_CAPABILITY_POINTER 0x34 //4 bytes
|
||||
#define PCI_INT_PIN_LINE 0x3C //2 bytes
|
||||
#define PCI_LATENCY_GRANT 0x3E //2 bytes
|
||||
#define PCI_LEGACY_AUDIO_CONTROL 0x40 //2 bytes
|
||||
#define PCI_LEGACY_CONF_CONTROL 0x42 //2 bytes
|
||||
#define PCI_HARD_CONF_CONTROL 0x60 //4 bytes
|
||||
#define PCI_CAPABILITY_ID 0x80 //1 byte
|
||||
#define PCI_NEXT_ITEM_POINTER 0x81 //1 byte
|
||||
#define PCI_POWER_CAPABILITY 0x82 //2 bytes
|
||||
#define PCI_POWER_CONTROL_STATUS 0x84 //2 bytes
|
||||
#define PCI_PMCSR_EXT_DATA 0x86 //2 bytes
|
||||
*/
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//CCSxx Controller Register Map (Page 4.3)
|
||||
//Table 4.2
|
||||
#define CCS_CONTROL_STATUS 0x00 //1 byte
|
||||
#define CCS_INTERRUPT_MASK 0x01 //1 byte
|
||||
#define CCS_INTERRUPT_STATUS 0x02 //1 byte
|
||||
#define CCS_CCI_INDEX 0x03 //1 byte
|
||||
#define CCS_CCI_DATA 0x04 //1 byte
|
||||
#define CCS_NMI_STATUS_1 0x05 //1 byte
|
||||
#define CCS_NMI_DATA 0x06 //1 byte
|
||||
#define CCS_NMI_INDEX 0x07 //1 byte
|
||||
#define CCS_CONS_AC97_INDEX 0x08 //1 byte
|
||||
#define CCS_CONS_AC97_COMMAND_STATUS 0x09 //1 byte
|
||||
#define CCS_CONS_AC97_DATA 0x0A //2 bytes
|
||||
#define CCS_MIDI_1_DATA 0x0C //1 byte
|
||||
#define CCS_MIDI_1_COMMAND_STATUS 0x0D //1 byte
|
||||
#define CCS_NMI_STATUS_2 0x0E //1 byte
|
||||
#define CCS_GAME_PORT 0x0F //1 byte
|
||||
#define CCS_I2C_DEV_ADDRESS 0x10 //1 byte
|
||||
#define CCS_I2C_BYTE_ADDRESS 0x11 //1 byte
|
||||
#define CCS_I2C_DATA 0x12 //1 byte
|
||||
#define CCS_I2C_CONTROL_STATUS 0x13 //1 byte
|
||||
#define CCS_CONS_DMA_BASE_ADDRESS 0x14 //4 bytes
|
||||
#define CCS_CONS_DMA_COUNT_ADDRESS 0x18 //2 bytes
|
||||
#define CCS_SERR_SHADOW 0x1B //1 byte
|
||||
#define CCS_MIDI_2_DATA 0x1C //1 byte
|
||||
#define CCS_MIDI_2_COMMAND_STATUS 0x1D //1 byte
|
||||
#define CCS_TIMER 0x1E //2 bytes
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Controller Indexed Register (Page 4.12)
|
||||
#define CCI_PB_TERM_COUNT_HI 0x00 //1 byte
|
||||
#define CCI_PB_TERM_COUNT_LO 0x01 //1 byte
|
||||
#define CCI_PB_CONTROL 0x02 //1 byte
|
||||
#define CCI_PB_LEFT_VOLUME 0x03 //1 byte
|
||||
#define CCI_PB_RIGHT_VOLUME 0x04 //1 byte
|
||||
#define CCI_SOFT_VOLUME 0x05 //1 byte
|
||||
#define CCI_PB_SAMPLING_RATE_LO 0x06 //1 byte
|
||||
#define CCI_PB_SAMPLING_RATE_MI 0x07 //1 byte
|
||||
#define CCI_PB_SAMPLING_RATE_HI 0x08 //1 byte
|
||||
#define CCI_REC_TERM_COUNT_HI 0x10 //1 byte
|
||||
#define CCI_REC_TERM_COUNT_LO 0x11 //1 byte
|
||||
#define CCI_REC_CONTROL 0x12 //1 byte
|
||||
#define CCI_GPIO_DATA 0x20 //1 byte
|
||||
#define CCI_GPIO_WRITE_MASK 0x21 //1 byte
|
||||
#define CCI_GPIO_DIRECTION_CONTROL 0x22 //1 byte
|
||||
#define CCI_CONS_POWER_DOWN 0x30 //1 byte
|
||||
#define CCI_MULTI_POWER_DOWN 0x31 //1 byte
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Consumer Section DMA Channel Registers (Page 4.20)
|
||||
//Table 4.4
|
||||
#define DS_DMA_INT_MASK 0x00 //2 bytes
|
||||
#define DS_DMA_INT_STATUS 0x02 //2 bytes
|
||||
#define DS_CHANNEL_DATA 0x04 //4 bytes
|
||||
#define DS_CHANNEL_INDEX 0x08 //1 byte
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Professional Multi-Track Control Registers (Page 4.24)
|
||||
//Table 4.7
|
||||
#define MT_DMA_INT_MASK_STATUS 0x00 //1 byte
|
||||
#define MT_SAMPLING_RATE_SELECT 0x01 //1 byte
|
||||
#define MT_I2S_DATA_FORMAT 0x02 //1 byte
|
||||
#define MT_PROF_AC97_INDEX 0x04 //1 byte
|
||||
#define MT_PROF_AC97_COMMAND_STATUS 0x05 //1 byte
|
||||
#define MT_PROF_AC97_DATA 0x06 //2 bytes
|
||||
#define MT_PROF_PB_DMA_BASE_ADDRESS 0x10 //4 bytes
|
||||
#define MT_PROF_PB_DMA_COUNT_ADDRESS 0x14 //2 bytes
|
||||
#define MT_PROF_PB_DMA_TERM_COUNT 0x16 //2 bytes
|
||||
#define MT_PROF_PB_CONTROL 0x18 //1 byte
|
||||
#define MT_PROF_REC_DMA_BASE_ADDRESS 0x20 //4 bytes
|
||||
#define MT_PROF_REC_DMA_COUNT_ADDRESS 0x24 //2 bytes
|
||||
#define MT_PROF_REC_DMA_TERM_COUNT 0x26 //2 bytes
|
||||
#define MT_PROF_REC_CONTROL 0x28 //1 byte
|
||||
#define MT_ROUTING_CONTROL_PSDOUT 0x30 //2 bytes
|
||||
#define MT_ROUTING_CONTROL_SPDOUT 0x32 //2 bytes
|
||||
#define MT_CAPTURED_DATA 0x34 //4 bytes
|
||||
#define MT_LR_VOLUME_CONTROL 0x38 //2 bytes
|
||||
#define MT_VOLUME_CONTROL_CHANNEL_INDEX 0x3A //1 byte
|
||||
#define MT_VOLUME_CONTROL_RATE 0x3B //1 byte
|
||||
#define MT_MIXER_MONITOR_RETURN 0x3C //1 byte
|
||||
#define MT_PEAK_METER_INDEX 0x3E //1 byte
|
||||
#define MT_PEAK_METER_DATA 0x3F //1 byte
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
#define I2C_EEPROM_ADDRESS_READ 0xA0 //1010 0000
|
||||
#define I2C_EEPROM_ADDRESS_WRITE 0xA1 //1010 0001
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
#define SPDIF_STEREO_IN 0x02 //0000 0010
|
||||
#define SPDIF_STEREO_OUT 0x01 //0000 0001
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,108 +1,109 @@
|
||||
/*
|
||||
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
|
||||
*
|
||||
* Copyright (c) 2002, Jerome Duval (jerome.duval@free.fr)
|
||||
* Copyright (c) 2003, Marcus Overhagen (marcus@overhagen.de)
|
||||
* Copyright (c) 2007, Jerome Leveque (leveque.jerome@neuf.fr)
|
||||
*
|
||||
* All rights reserved
|
||||
* Distributed under the terms of the MIT license.
|
||||
*/
|
||||
|
||||
#ifndef _IO_H_
|
||||
#define _IO_H_
|
||||
|
||||
#include "ice1712.h"
|
||||
|
||||
#include <SupportDefs.h>
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Address are [PCI_10] + xx
|
||||
uint8 read_ccs_uint8(ice1712 *ice, int8 regno);
|
||||
uint16 read_ccs_uint16(ice1712 *ice, int8 regno);
|
||||
uint32 read_ccs_uint32(ice1712 *ice, int8 regno);
|
||||
|
||||
void write_ccs_uint8(ice1712 *ice, int8 regno, uint8 value);
|
||||
void write_ccs_uint16(ice1712 *ice, int8 regno, uint16 value);
|
||||
void write_ccs_uint32(ice1712 *ice, int8 regno, uint32 value);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
uint8 read_cci_uint8(ice1712 *ice, int8 index);
|
||||
void write_cci_uint8(ice1712 *ice, int8 index, uint8 value);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Address are [PCI_14] + xx
|
||||
uint8 read_ddma_uint8(ice1712 *ice, int8 regno);
|
||||
uint16 read_ddma_uint16(ice1712 *ice, int8 regno);
|
||||
uint32 read_ddma_uint32(ice1712 *ice, int8 regno);
|
||||
|
||||
void write_ddma_uint8(ice1712 *ice, int8 regno, uint8 value);
|
||||
void write_ddma_uint16(ice1712 *ice, int8 regno, uint16 value);
|
||||
void write_ddma_uint32(ice1712 *ice, int8 regno, uint32 value);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Address are [PCI_18] + x
|
||||
uint8 read_ds_uint8(ice1712 *ice, int8 regno);
|
||||
uint16 read_ds_uint16(ice1712 *ice, int8 regno);
|
||||
uint32 read_ds_uint32(ice1712 *ice, int8 regno);
|
||||
|
||||
void write_ds_uint8(ice1712 *ice, int8 regno, uint8 value);
|
||||
void write_ds_uint16(ice1712 *ice, int8 regno, uint16 value);
|
||||
void write_ds_uint32(ice1712 *ice, int8 regno, uint32 value);
|
||||
|
||||
typedef enum {
|
||||
DS8_REGISTER_BUFFER_0_BASE_ADDRESS = 0,
|
||||
DS8_REGISTER_BUFFER_0_BASE_COUNT,
|
||||
DS8_REGISTER_BUFFER_1_BASE_ADDRESS,
|
||||
DS8_REGISTER_BUFFER_1_BASE_COUNT,
|
||||
DS8_REGISTER_CONTROL_AND_STATUS,
|
||||
DS8_REGISTER_SAMPLING_RATE,
|
||||
DS8_REGISTER_LEFT_RIGHT_VOLUME,
|
||||
} ds8_register;
|
||||
|
||||
uint32 read_ds_channel_data(ice1712 *ice, uint8 channel, ds8_register index);
|
||||
void write_ds_channel_data(ice1712 *ice, uint8 channel, ds8_register index, uint32 data);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Address are [PCI_1C] + xx
|
||||
uint8 read_mt_uint8(ice1712 *ice, int8 regno);
|
||||
uint16 read_mt_uint16(ice1712 *ice, int8 regno);
|
||||
uint32 read_mt_uint32(ice1712 *ice, int8 regno);
|
||||
|
||||
void write_mt_uint8(ice1712 *ice, int8 regno, uint8 value);
|
||||
void write_mt_uint16(ice1712 *ice, int8 regno, uint16 value);
|
||||
void write_mt_uint32(ice1712 *ice, int8 regno, uint32 value);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
int16 read_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr);
|
||||
//return -1 if error else return an uint8
|
||||
|
||||
int16 write_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr, uint8 value);
|
||||
//return -1 if error else return 0
|
||||
|
||||
//------------------------------------------------------
|
||||
|
||||
int16 read_eeprom(ice1712 *ice, uint8 eeprom[32]);
|
||||
|
||||
//------------------------------------------------------
|
||||
|
||||
void codec_write(ice1712 *ice, uint8 reg_addr, uint8 data);
|
||||
void spdif_write(ice1712 *ice, uint8 reg_addr, uint8 data);
|
||||
void codec_write_mult(ice1712 *ice, uint8 reg_addr, uint8 datas[], uint8 size);
|
||||
void spdif_write_mult(ice1712 *ice, uint8 reg_addr, uint8 datas[], uint8 size);
|
||||
|
||||
uint8 codec_read(ice1712 *ice, uint8 reg_addr);
|
||||
uint8 spdif_read(ice1712 *ice, uint8 reg_addr);
|
||||
uint8 codec_read_mult(ice1712 *ice, uint8 reg_addr, uint8 datas[], uint8 size);
|
||||
uint8 spdif_read_mult(ice1712 *ice, uint8 reg_addr, uint8 datas[], uint8 size);
|
||||
|
||||
//------------------------------------------------------
|
||||
|
||||
uint8 read_gpio(ice1712 *ice);
|
||||
//return -1 if error else return an uint8
|
||||
|
||||
void write_gpio(ice1712 *ice, uint8 value);
|
||||
|
||||
#endif
|
||||
/*
|
||||
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
|
||||
*
|
||||
* Copyright (c) 2002, Jerome Duval (jerome.duval@free.fr)
|
||||
* Copyright (c) 2003, Marcus Overhagen (marcus@overhagen.de)
|
||||
* Copyright (c) 2007, Jerome Leveque (leveque.jerome@neuf.fr)
|
||||
*
|
||||
* All rights reserved
|
||||
* Distributed under the terms of the MIT license.
|
||||
*/
|
||||
|
||||
#ifndef _IO_H_
|
||||
#define _IO_H_
|
||||
|
||||
#include "ice1712.h"
|
||||
|
||||
#include <SupportDefs.h>
|
||||
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Address are [PCI_10] + xx
|
||||
uint8 read_ccs_uint8(ice1712 *ice, int8 regno);
|
||||
uint16 read_ccs_uint16(ice1712 *ice, int8 regno);
|
||||
uint32 read_ccs_uint32(ice1712 *ice, int8 regno);
|
||||
|
||||
void write_ccs_uint8(ice1712 *ice, int8 regno, uint8 value);
|
||||
void write_ccs_uint16(ice1712 *ice, int8 regno, uint16 value);
|
||||
void write_ccs_uint32(ice1712 *ice, int8 regno, uint32 value);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
uint8 read_cci_uint8(ice1712 *ice, int8 index);
|
||||
void write_cci_uint8(ice1712 *ice, int8 index, uint8 value);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Address are [PCI_14] + xx
|
||||
uint8 read_ddma_uint8(ice1712 *ice, int8 regno);
|
||||
uint16 read_ddma_uint16(ice1712 *ice, int8 regno);
|
||||
uint32 read_ddma_uint32(ice1712 *ice, int8 regno);
|
||||
|
||||
void write_ddma_uint8(ice1712 *ice, int8 regno, uint8 value);
|
||||
void write_ddma_uint16(ice1712 *ice, int8 regno, uint16 value);
|
||||
void write_ddma_uint32(ice1712 *ice, int8 regno, uint32 value);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Address are [PCI_18] + x
|
||||
uint8 read_ds_uint8(ice1712 *ice, int8 regno);
|
||||
uint16 read_ds_uint16(ice1712 *ice, int8 regno);
|
||||
uint32 read_ds_uint32(ice1712 *ice, int8 regno);
|
||||
|
||||
void write_ds_uint8(ice1712 *ice, int8 regno, uint8 value);
|
||||
void write_ds_uint16(ice1712 *ice, int8 regno, uint16 value);
|
||||
void write_ds_uint32(ice1712 *ice, int8 regno, uint32 value);
|
||||
|
||||
typedef enum {
|
||||
DS8_REGISTER_BUFFER_0_BASE_ADDRESS = 0,
|
||||
DS8_REGISTER_BUFFER_0_BASE_COUNT,
|
||||
DS8_REGISTER_BUFFER_1_BASE_ADDRESS,
|
||||
DS8_REGISTER_BUFFER_1_BASE_COUNT,
|
||||
DS8_REGISTER_CONTROL_AND_STATUS,
|
||||
DS8_REGISTER_SAMPLING_RATE,
|
||||
DS8_REGISTER_LEFT_RIGHT_VOLUME,
|
||||
} ds8_register;
|
||||
|
||||
uint32 read_ds_channel_data(ice1712 *ice, uint8 channel, ds8_register index);
|
||||
void write_ds_channel_data(ice1712 *ice, uint8 channel,
|
||||
ds8_register index, uint32 data);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
//Address are [PCI_1C] + xx
|
||||
uint8 read_mt_uint8(ice1712 *ice, int8 regno);
|
||||
uint16 read_mt_uint16(ice1712 *ice, int8 regno);
|
||||
uint32 read_mt_uint32(ice1712 *ice, int8 regno);
|
||||
|
||||
void write_mt_uint8(ice1712 *ice, int8 regno, uint8 value);
|
||||
void write_mt_uint16(ice1712 *ice, int8 regno, uint16 value);
|
||||
void write_mt_uint32(ice1712 *ice, int8 regno, uint32 value);
|
||||
//------------------------------------------------------
|
||||
//------------------------------------------------------
|
||||
|
||||
int16 read_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr);
|
||||
//return -1 if error else return an uint8
|
||||
|
||||
int16 write_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr, uint8 value);
|
||||
//return -1 if error else return 0
|
||||
|
||||
//------------------------------------------------------
|
||||
|
||||
int16 read_eeprom(ice1712 *ice, uint8 eeprom[32]);
|
||||
|
||||
//------------------------------------------------------
|
||||
|
||||
void codec_write(ice1712 *ice, uint8 reg_addr, uint8 data);
|
||||
void spdif_write(ice1712 *ice, uint8 reg_addr, uint8 data);
|
||||
void codec_write_mult(ice1712 *ice, uint8 reg_addr, uint8 datas[], uint8 size);
|
||||
void spdif_write_mult(ice1712 *ice, uint8 reg_addr, uint8 datas[], uint8 size);
|
||||
|
||||
uint8 codec_read(ice1712 *ice, uint8 reg_addr);
|
||||
uint8 spdif_read(ice1712 *ice, uint8 reg_addr);
|
||||
uint8 codec_read_mult(ice1712 *ice, uint8 reg_addr, uint8 datas[], uint8 size);
|
||||
uint8 spdif_read_mult(ice1712 *ice, uint8 reg_addr, uint8 datas[], uint8 size);
|
||||
|
||||
//------------------------------------------------------
|
||||
|
||||
uint8 read_gpio(ice1712 *ice);
|
||||
//return -1 if error else return an uint8
|
||||
|
||||
void write_gpio(ice1712 *ice, uint8 value);
|
||||
|
||||
#endif
|
||||
|
||||
@ -37,7 +37,7 @@ void midi_interrupt_op(int32 op, void * data)
|
||||
// set_indirect(port->card, 0x2A, 0x04, 0xff);
|
||||
// release_spinlock(&port->card->hardware);
|
||||
restore_interrupts(cp);
|
||||
|
||||
|
||||
//real code
|
||||
cp = lock();
|
||||
// emuxki_reg_write_32(&(port->card->config), EMU_INTE,
|
||||
@ -58,7 +58,7 @@ void midi_interrupt_op(int32 op, void * data)
|
||||
// decrement_interrupt_handler(port->card);
|
||||
// release_spinlock(&port->card->hardware);
|
||||
restore_interrupts(cp);
|
||||
|
||||
|
||||
//real code
|
||||
// cpu_status status;
|
||||
cp = lock();
|
||||
@ -74,8 +74,8 @@ static status_t midi_close(void *cookie);
|
||||
static status_t midi_free(void *cookie);
|
||||
static status_t midi_control(void *cookie, uint32 op, void *data, size_t len);
|
||||
static status_t midi_read(void *cookie, off_t pos, void *data, size_t *len);
|
||||
static status_t midi_write(void *cookie, off_t pos, const void *data, size_t *len);
|
||||
|
||||
static status_t midi_write(void *cookie, off_t pos, const void *data,
|
||||
size_t *len);
|
||||
|
||||
device_hooks midi_hooks = {
|
||||
&midi_open,
|
||||
@ -90,7 +90,6 @@ device_hooks midi_hooks = {
|
||||
NULL /* writev */
|
||||
};
|
||||
|
||||
|
||||
static status_t midi_open(const char * name, uint32 flags, void ** cookie)
|
||||
{
|
||||
int i, ix, used_midi = -1;
|
||||
@ -106,14 +105,16 @@ static status_t midi_open(const char * name, uint32 flags, void ** cookie)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (ix >= num_cards) {
|
||||
TRACE("bad device\n");
|
||||
return ENODEV;
|
||||
}
|
||||
|
||||
TRACE("mpu401: %p open(): %p driver: %p\n", mpu401, mpu401->open_hook, cards[ix].midi_interf[used_midi].driver);
|
||||
ret = (*mpu401->open_hook)(cards[ix].midi_interf[used_midi].driver, flags, cookie);
|
||||
TRACE("mpu401: %p open(): %p driver: %p\n", mpu401,
|
||||
mpu401->open_hook, cards[ix].midi_interf[used_midi].driver);
|
||||
ret = (*mpu401->open_hook)(cards[ix].midi_interf[used_midi].driver,
|
||||
flags, cookie);
|
||||
if (ret >= B_OK) {
|
||||
cards[ix].midi_interf[used_midi].cookie = *cookie;
|
||||
atomic_add(&cards[ix].midi_interf[used_midi].count, 1);
|
||||
@ -164,7 +165,8 @@ static status_t midi_read(void * cookie, off_t pos, void * ptr, size_t * nread)
|
||||
}
|
||||
|
||||
|
||||
static status_t midi_write(void * cookie, off_t pos, const void * ptr, size_t * nwritten)
|
||||
static status_t midi_write(void * cookie, off_t pos, const void * ptr,
|
||||
size_t * nwritten)
|
||||
{
|
||||
return (*mpu401->write_hook)(cookie, pos, ptr, nwritten);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -16,26 +16,56 @@
|
||||
|
||||
#include <hmulti_audio.h>
|
||||
|
||||
#define ICE1712_MULTI_CONTROL_FIRSTID (0x08000000)
|
||||
#define ICE1712_MULTI_CONTROL_FIRSTID (0x80000000)
|
||||
|
||||
#define ICE1712_MULTI_CONTROL_TYPE_MASK (0x70000000)
|
||||
#define ICE1712_MULTI_CONTROL_TYPE_COMBO (0x10000000)
|
||||
#define ICE1712_MULTI_CONTROL_TYPE_VOLUME (0x20000000)
|
||||
#define ICE1712_MULTI_CONTROL_TYPE_OUTPUT (0x30000000)
|
||||
#define ICE1712_MULTI_CONTROL_TYPE_OTHER4 (0x40000000)
|
||||
#define ICE1712_MULTI_CONTROL_TYPE_OTHER5 (0x50000000)
|
||||
#define ICE1712_MULTI_CONTROL_TYPE_OTHER6 (0x60000000)
|
||||
#define ICE1712_MULTI_CONTROL_TYPE_OTHER7 (0x70000000)
|
||||
|
||||
#define ICE1712_MULTI_CONTROL_CHANNEL_MASK (0x0FF00000)
|
||||
#define ICE1712_MULTI_CONTROL_INDEX_MASK (0x00000FFF)
|
||||
|
||||
#define ICE1712_MULTI_SET_CHANNEL(_c_) ((_c_ << 20) & \
|
||||
ICE1712_MULTI_CONTROL_CHANNEL_MASK)
|
||||
#define ICE1712_MULTI_GET_CHANNEL(_c_) ((_c_ & \
|
||||
ICE1712_MULTI_CONTROL_CHANNEL_MASK) >> 20)
|
||||
|
||||
#define ICE1712_MULTI_SET_INDEX(_i_) (_i_ & \
|
||||
ICE1712_MULTI_CONTROL_INDEX_MASK)
|
||||
#define ICE1712_MULTI_GET_INDEX(_i_) (_i_ & \
|
||||
ICE1712_MULTI_CONTROL_INDEX_MASK)
|
||||
|
||||
/*
|
||||
#define ICE1712_MULTI_CONTROL_VOLUME_PB (0x00010000)
|
||||
#define ICE1712_MULTI_CONTROL_VOLUME_REC (0x00020000)
|
||||
#define ICE1712_MULTI_CONTROL_MUTE (0x00040000)
|
||||
#define ICE1712_MULTI_CONTROL_MUX (0x00080000)
|
||||
#define ICE1712_MULTI_CONTROL_MASK (0x00FF0000)
|
||||
#define ICE1712_MULTI_CONTROL_CHANNEL_MASK (0x000000FF)
|
||||
*/
|
||||
|
||||
#define CONTROL_IS_MASTER (0)
|
||||
|
||||
status_t ice1712_get_description(ice1712 *card, multi_description *data);
|
||||
status_t ice1712_get_enabled_channels(ice1712 *card, multi_channel_enable *data);
|
||||
status_t ice1712_set_enabled_channels(ice1712 *card, multi_channel_enable *data);
|
||||
status_t ice1712_get_enabled_channels(ice1712 *card,
|
||||
multi_channel_enable *data);
|
||||
status_t ice1712_set_enabled_channels(ice1712 *card,
|
||||
multi_channel_enable *data);
|
||||
status_t ice1712_get_global_format(ice1712 *card, multi_format_info *data);
|
||||
status_t ice1712_set_global_format(ice1712 *card, multi_format_info *data);
|
||||
status_t ice1712_get_mix(ice1712 *card, multi_mix_value_info *data);
|
||||
status_t ice1712_set_mix(ice1712 *card, multi_mix_value_info *data);
|
||||
status_t ice1712_list_mix_channels(ice1712 *card, multi_mix_channel_info *data);
|
||||
status_t ice1712_list_mix_controls(ice1712 *card, multi_mix_control_info *data);
|
||||
status_t ice1712_list_mix_connections(ice1712 *card, multi_mix_connection_info *data);
|
||||
status_t ice1712_list_mix_channels(ice1712 *card,
|
||||
multi_mix_channel_info *data);
|
||||
status_t ice1712_list_mix_controls(ice1712 *card,
|
||||
multi_mix_control_info *data);
|
||||
status_t ice1712_list_mix_connections(ice1712 *card,
|
||||
multi_mix_connection_info *data);
|
||||
status_t ice1712_get_buffers(ice1712 *card, multi_buffer_list *data);
|
||||
status_t ice1712_buffer_exchange(ice1712 *card, multi_buffer_info *data);
|
||||
status_t ice1712_buffer_force_stop(ice1712 *card);
|
||||
|
||||
@ -76,7 +76,8 @@ alloc_mem(void **phy, void **log, size_t size, const char *name)
|
||||
*log = logadr;
|
||||
if (phy)
|
||||
*phy = (void*)(addr_t)pe.address;
|
||||
TRACE("area = %d, size = %#08X, log = %#08X, phy = %#08X\n", (int)areaid, (int)size, (int)logadr, (int)pe.address);
|
||||
TRACE("area = %d, size = %#08X, log = %#08X, phy = %#08X\n",
|
||||
(int)areaid, (int)size, (int)logadr, (int)pe.address);
|
||||
return areaid;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user