style cleanup, hopefully no functional change
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@30277 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
David McPaul
parent
8a26f35a6d
commit
3b63cb8a3a
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@ -139,58 +139,58 @@ struct cache_description {
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static void
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print_intel_cache_descriptors(enum cpu_types type, cpuid_info *info)
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{
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int i, j, max_desc;
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int i, j, maxDesc;
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uint8 cache_descriptors[15]; // Max
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uint8 cacheDescriptors[15]; // Max
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max_desc = 0;
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maxDesc = 0;
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i = 0;
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// put valid values into array
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if ((info->regs.eax & 0x80000000) == 0) {
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// eax is valid, include values
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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} else {
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i += 3;
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}
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if ((info->regs.ebx & 0x80000000) == 0) {
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// ebx is valid, include values
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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} else {
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i += 4;
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}
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if ((info->regs.edx & 0x80000000) == 0) {
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// edx is valid, include values
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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} else {
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i += 4;
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}
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if ((info->regs.ecx & 0x80000000) == 0) {
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// ecx is valid, include values
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cache_descriptors[max_desc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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cacheDescriptors[maxDesc++] = info->eax_2.cache_descriptors[i++];
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}
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putchar('\n');
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for (i = 0; i < max_desc; i++) {
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for (i = 0; i < maxDesc; i++) {
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// ignore NULL descriptors
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if (cache_descriptors[i] == 0)
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if (cacheDescriptors[i] == 0)
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continue;
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for (j = 0; sIntelCacheDescriptions[j].code; j++) {
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if (cache_descriptors[i] == sIntelCacheDescriptions[j].code) {
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if (cache_descriptors[i] == 0x40) {
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if (cacheDescriptors[i] == sIntelCacheDescriptions[j].code) {
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if (cacheDescriptors[i] == 0x40) {
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printf("\tNo integrated L%u cache\n",
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type >= B_CPU_INTEL_PENTIUM_IV
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&& (type & B_CPU_x86_VENDOR_MASK) == B_CPU_INTEL_x86 ?
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@ -203,7 +203,7 @@ print_intel_cache_descriptors(enum cpu_types type, cpuid_info *info)
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// Reached the end without finding a descriptor
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if (sIntelCacheDescriptions[j].code == 0)
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printf("\tUnknown cache descriptor 0x%02x\n", cache_descriptors[i]);
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printf("\tUnknown cache descriptor 0x%02x\n", cacheDescriptors[i]);
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}
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}
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@ -240,8 +240,8 @@ print_level2_cache(uint32 reg, const char *name)
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{
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uint32 size = (reg >> 16) & 0xffff;
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uint32 ways = (reg >> 12) & 0xf;
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uint32 lines_per_tag = (reg >> 8) & 0xf; // intel does not define this
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uint32 linesize = reg & 0xff;
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uint32 linesPerTag = (reg >> 8) & 0xf; // intel does not define this
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uint32 lineSize = reg & 0xff;
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printf("\t%s: %lu KB, ", name, size);
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if (ways == 0xf)
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@ -250,7 +250,7 @@ print_level2_cache(uint32 reg, const char *name)
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printf("direct-mapped, ");
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else
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printf("%lu-way set associative, ", 1UL << (ways / 2));
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printf("%lu lines/tag, %lu bytes/line\n", lines_per_tag, linesize);
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printf("%lu lines/tag, %lu bytes/line\n", linesPerTag, lineSize);
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}
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@ -259,15 +259,15 @@ print_level1_cache(uint32 reg, const char *name)
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{
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uint32 size = (reg >> 24) & 0xff;
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uint32 ways = (reg >> 16) & 0xff;
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uint32 lines_per_tag = (reg >> 8) & 0xff;
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uint32 linesize = reg & 0xff;
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uint32 linesPerTag = (reg >> 8) & 0xff;
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uint32 lineSize = reg & 0xff;
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printf("\t%s: %lu KB, ", name, size);
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if (ways == 0xff)
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printf("fully associative, ");
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else
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printf("%lu-way set associative, ", ways);
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printf("%lu lines/tag, %lu bytes/line\n", lines_per_tag, linesize);
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printf("%lu lines/tag, %lu bytes/line\n", linesPerTag, lineSize);
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}
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@ -299,9 +299,9 @@ print_intel_cache_desc(int32 cpu)
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cpuid_info info;
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uint32 type;
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uint32 level;
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bool is_fully_assoc;
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uint32 linesize;
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uint32 lines_per_tag;
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bool isFullyAssoc;
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uint32 lineSize;
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uint32 linesPerTag;
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uint32 ways;
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uint32 sets;
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@ -312,10 +312,10 @@ print_intel_cache_desc(int32 cpu)
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type = info.regs.eax & 0xf;
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level = (info.regs.eax & 0x70) >> 4;
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is_fully_assoc = info.regs.eax & 0x100;
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isFullyAssoc = info.regs.eax & 0x100;
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linesize = (info.regs.ebx & 0xfff) + 1;
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lines_per_tag = ((info.regs.ebx & 0x3ff000) >> 12) + 1;
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lineSize = (info.regs.ebx & 0xfff) + 1;
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linesPerTag = ((info.regs.ebx & 0x3ff000) >> 12) + 1;
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ways = ((info.regs.ebx & 0xffc00000) >> 22) + 1;
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sets = info.regs.ecx;
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@ -329,11 +329,11 @@ print_intel_cache_desc(int32 cpu)
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default: break;
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}
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if (is_fully_assoc)
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if (isFullyAssoc)
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printf("fully associative, ");
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else
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printf("%lu-way set associative, ", ways);
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printf("%lu lines/tag, %lu bytes/line\n", lines_per_tag, linesize);
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printf("%lu lines/tag, %lu bytes/line\n", linesPerTag, lineSize);
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get_cpuid(&info, 0x80000006, cpu);
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print_level2_cache(info.regs.ecx, "L2 cache");
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