From 3b40448410fb47a6d7a6f1818fda2afe9c938153 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Revol?= Date: Fri, 27 Feb 2009 16:50:25 +0000 Subject: [PATCH] added cache/TLB descriptors from Intel Application Note 485. Patch by Christian Packmann. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@29337 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/bin/sysinfo.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/src/bin/sysinfo.c b/src/bin/sysinfo.c index 0eb85aa3ff..97ecdfb528 100644 --- a/src/bin/sysinfo.c +++ b/src/bin/sysinfo.c @@ -27,20 +27,28 @@ struct cache_description { {0x02, "Instruction TLB: 4M-byte pages, fully associative, 2 entries"}, {0x03, "Data TLB: 4k-byte pages, 4-way set associative, 64 entries"}, {0x04, "Data TLB: 4M-byte pages, 4-way set associative, 8 entries"}, + {0x05, "Data TLB: 4M-byte pages, 4-way set associative, 32 entries"}, {0x06, "L1 inst cache: 8 KB, 4-way set associative, 32 bytes/line"}, {0x08, "L1 inst cache: 16 KB, 4-way set associative, 32 bytes/line"}, {0x0A, "L1 data cache: 8 KB, 2-way set associative, 32 bytes/line"}, {0x0C, "L1 data cache: 16 KB, 4-way set associative, 32 bytes/line"}, + {0x0D, "L1 data cache: 16 KB, 4-way set associative, 64-bytes/line, ECC"}, {0x10, /* IA-64 */ "L1 data cache: 16 KB, 4-way set associative, 32 bytes/line"}, {0x15, /* IA-64 */ "L1 inst cache: 16 KB, 4-way set associative, 32 bytes/line"}, {0x1A, /* IA-64 */ "L2 cache: 96 KB, 6-way set associative, 64 bytes/line"}, + {0x21, "L2 cache: 256 KB (MLC), 8-way set associative, 64-bytes/line"}, {0x22, "L3 cache: 512 KB, 4-way set associative (!), 64 bytes/line, dual-sectored"}, {0x23, "L3 cache: 1 MB, 8-way set associative, 64 bytes/line, dual-sectored"}, {0x25, "L3 cache: 2 MB, 8-way set associative, 64 bytes/line, dual-sectored"}, {0x29, "L3 cache: 4 MB, 8-way set associative, 64 bytes/line, dual-sectored"}, + {0x2c, "L1 data cache: 32 KB, 8-way set associative, 64 bytes/line"}, + {0x30, "L1 inst cache: 32 KB, 8-way set associative, 64 bytes/line"}, {0x39, "L2 cache: 128 KB, 4-way set associative, 64 bytes/line, sectored"}, + {0x3A, "L2 cache: 192 KB, 4-way set associative, 64 bytes/line, sectored"}, {0x3B, "L2 cache: 128 KB, 2-way set associative, 64 bytes/line, sectored"}, {0x3C, "L2 cache: 256 KB, 4-way set associative, 64 bytes/line, sectored"}, + {0x3D, "L2 cache: 384 KB, 6-way set associative, 64 bytes/line, sectored"}, + {0x3E, "L2 cache: 512 KB, 4-way set associative, 64 bytes/line, sectored"}, {0x40, NULL /*"No integrated L2 cache (P6 core) or L3 cache (P4 core)"*/}, // this one is separately handled {0x41, "L2 cache: 128 KB, 4-way set associative, 32 bytes/line"}, @@ -48,9 +56,22 @@ struct cache_description { {0x43, "L2 cache: 512 KB, 4-way set associative, 32 bytes/line"}, {0x44, "L2 cache: 1024 KB, 4-way set associative, 32 bytes/line"}, {0x45, "L2 cache: 2048 KB, 4-way set associative, 32 bytes/line"}, + {0x46, "L3 cache: 4096 KB, 4-way set associative, 64 bytes/line"}, + {0x47, "L3 cache: 8192 KB, 8-way set associative, 64 bytes/line"}, + {0x48, "L2 cache: 3072 KB, 12-way set associative, 64 bytes/line, unified on-die"}, + // 0x49 requires special handling, either 4M L3 (Xeon MP, 0F06; otherwise 4M L2 + {0x4A, "L3 cache: 6144 KB, 12-way set associative, 64 bytes/line"}, + {0x4B, "L3 cache: 8192 KB, 16-way set associative, 64 bytes/line"}, + {0x4C, "L3 cache: 12288 KB, 12-way set associative, 64 bytes/line"}, + {0x4D, "L3 cache: 16384 KB, 16-way set associative, 64 bytes/line"}, + {0x4E, "L2 cache: 6144 KB, 24-way set associative, 64 bytes/line"}, {0x50, "Inst TLB: 4K/4M/2M-bytes pages, fully associative, 64 entries"}, {0x51, "Inst TLB: 4K/4M/2M-bytes pages, fully associative, 128 entries"}, {0x52, "Inst TLB: 4K/4M/2M-bytes pages, fully associative, 256 entries"}, + {0x55, "Inst TLB: 2M/4M-bytes pages, fully associative, 7 entries"}, + {0x56, "L1 Data TLB: 4M-bytes pages, 4-way set associative, 16 entries"}, + {0x57, "L1 Data TLB: 4K-bytes pages, 4-way set associative, 16 entries"}, + {0x5A, "Data TLB: 2M/4M-bytes pages, 4-way set associative, 32 entries"}, {0x5B, "Data TLB: 4K/4M-bytes pages, fully associative, 64 entries"}, {0x5C, "Data TLB: 4K/4M-bytes pages, fully associative, 128 entries"}, {0x5D, "Data TLB: 4K/4M-bytes pages, fully associative, 256 entries"}, @@ -84,6 +105,28 @@ struct cache_description { {0x80, /* Cyrix specific */ "L1 cache: 16 KB, 4-way set associative, 16 bytes/line"}, // {0x82, "Cyrix specific: ???"}, // {0x84, "Cyrix specific: ???"}, + {0xB0, "Inst TLB: 4K-bytes pages, 4-way set associative, 128 entries"}, + {0xB1, "Inst TLB: 2M-bytes pages, 4-way set associative, 8 entries OR 4M, 4-way, 4 entries"}, + // Intel doesn't give any details how to determine which of the two options is the case + // as per Intel Application Note 485, November 2008. + {0xB2, "Inst TLB: 4K-bytes pages, 4-way set associative, 64 entries"}, + {0xB3, "Data TLB: 4K-bytes pages, 4-way set associative, 128 entries"}, + {0xB4, "Data TLB: 4K-bytes pages, 4-way set associative, 256 entries"}, + {0xCA, "Shared 2nd-level TLB: 4K, 4-way set associative, 512 entries"}, + {0xD0, "L3 cache: 512 KB, 4-way set associative, 64-bytes/line"}, + {0xD1, "L3 cache: 1024 KB, 4-way set associative, 64-bytes/line"}, + {0xD2, "L3 cache: 2048 KB, 4-way set associative, 64-bytes/line"}, + {0xD6, "L3 cache: 1024 KB, 8-way set associative, 64-bytes/line"}, + {0xD7, "L3 cache: 2048 KB, 8-way set associative, 64-bytes/line"}, + {0xD8, "L3 cache: 4096 KB, 8-way set associative, 64-bytes/line"}, + {0xDC, "L3 cache: 2048 KB, 12-way set associative, 64-bytes/line"}, + {0xDD, "L3 cache: 4096 KB, 12-way set associative, 64-bytes/line"}, + {0xDE, "L3 cache: 8192 KB, 12-way set associative, 64-bytes/line"}, + {0xE2, "L3 cache: 2048 KB, 16-way set associative, 64-bytes/line"}, + {0xE3, "L3 cache: 4096 KB, 16-way set associative, 64-bytes/line"}, + {0xE4, "L3 cache: 8192 KB, 16-way set associative, 64-bytes/line"}, + {0xF0, "64-byte Prefetching"}, + {0xF1, "128-byte Prefetching"}, {0, NULL} };