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* More or less completely rewrote the AGP bus manager.

Browse Source 
* It now also serves as a generic GART manager and accepts bus modules as well
  as custom modules of graphics drivers if they want to (could be used for the
  Radeon PCI GART stuff, for example).
* Implemented GART support module for Intel i965 and G33 chipsets (the other
  Intel chips will come later).
* Renamed agp bus manager to agp_gart to reflect its new functionality (even
  though the AGP functionality is already outdated (due to PCIe), the GART
  stuff remains current).
* Adapted existing users of the AGP bus manager to the API changes.
* Not very well tested yet...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@23754 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler 2008-01-26 22:18:52 +00:00
parent d75c88206e
commit 3adccb1935
21 changed files with 1906 additions and 1112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
build/jam/HaikuImage
View File

@ -125,7 +125,7 @@ BEOS_ADD_ONS_DRIVERS_NET = $(X86_ONLY)3com etherpci $(X86_ONLY)ipro1000
;
#BEOS_ADD_ONS_DRIVERS_ACPI = $(X86_ONLY)acpi_button ;
BEOS_ADD_ONS_BUS_MANAGERS = pci $(X86_ONLY)ps2 $(X86_ONLY)isa ide scsi
config_manager $(X86_ONLY)agp usb firewire
config_manager agp_gart usb firewire
;
BEOS_ADD_ONS_FILE_SYSTEMS = bfs cdda fat googlefs iso9660 nfs ;
@ -133,6 +133,8 @@ BEOS_ADD_ONS_FILE_SYSTEMS = bfs cdda fat googlefs iso9660 nfs ;
# modules
AddFilesToHaikuImage beos system add-ons kernel bus_managers
: $(BEOS_ADD_ONS_BUS_MANAGERS) ;
AddFilesToHaikuImage beos system add-ons kernel busses agp_gart
: <agp_gart>intel ;
AddFilesToHaikuImage beos system add-ons kernel busses ide
: generic_ide_pci $(X86_ONLY)ide_isa silicon_image_3112 legacy_sata ;
AddFilesToHaikuImage beos system add-ons kernel busses scsi

185
headers/private/graphics/AGP.h
View File

@ -1,108 +1,123 @@
/*******************************************************************************
/
/ File: AGP.h
/
/ Description: Interface to the AGP bus and driver.
/ For more information, see "AGP interface specification", Revision 2.0 and 3.0,
/ Intel Corporation, 1998-2002.
/
/ Rudolf Cornelissen 6/2004-7/2004.
/
*******************************************************************************/
#if !defined(_AGP_H_)
/*
* Copyright 2004-2008, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _AGP_H_
#define _AGP_H_
#include <bus_manager.h>
#ifdef __cplusplus
extern "C" {
#endif
/* -----
agp device info
----- */
typedef struct agp_info {
ushort vendor_id; /* vendor id */
ushort device_id; /* device id */
uchar bus; /* bus number */
uchar device; /* device number on bus */
uchar function; /* function number in device */
uchar class_sub; /* specific device function */
uchar class_base; /* device type (display vs host bridge) */
struct
{
uint32 agp_cap_id; /* AGP capability register as defined in the AGP standard */
uint32 agp_stat; /* AGP STATUS register as defined in the AGP standard */
uint32 agp_cmd; /* AGP COMMAND register as defined in the AGP standard */
ushort vendor_id; /* vendor id */
ushort device_id; /* device id */
uchar bus; /* bus number */
uchar device; /* device number on bus */
uchar function; /* function number in device */
uchar class_sub; /* specific device function */
uchar class_base; /* device type (display vs host bridge) */
struct {
uint32 capability_id; /* AGP capability register as defined in the AGP standard */
uint32 status; /* AGP STATUS register as defined in the AGP standard */
uint32 command; /* AGP COMMAND register as defined in the AGP standard */
} interface;
status_t status; /* B_OK if usable, B_ERROR if device did not respond
* according to the AGP standard */
} agp_info;
typedef struct agp_module_info agp_module_info;
typedef struct aperture_info {
addr_t physical_base;
addr_t base;
size_t size;
size_t reserved_size;
} aperture_info;
struct agp_module_info {
bus_manager_info binfo;
long (*get_nth_agp_info) (
long index, /* index into agp device table */
agp_info *info /* caller-supplied buffer for info */
);
void (*enable_agp) (
uint32 *command /* max. mode to set */
);
//fixme: GART and APERTURE stuff is lacking for now, add here...
/* flags for allocate_memory */
enum {
B_APERTURE_NON_RESERVED = 0x01,
B_APERTURE_NEED_PHYSICAL = 0x02,
};
#define B_AGP_MODULE_NAME "bus_managers/agp/v0"
typedef int32 aperture_id;
typedef struct gart_bus_module_info gart_bus_module_info;
typedef struct agp_gart_module_info {
bus_manager_info info;
/* ---
value for the AGP_id field in the agp_cap_id register
--- */
#define AGP_id 0x02 /* AGP device identification */
// AGP functionality
status_t (*get_nth_agp_info)(uint32 index, agp_info *info);
status_t (*acquire_agp)(void);
void (*release_agp)(void);
uint32 (*set_agp_mode)(uint32 command);
// GART functionality
aperture_id (*map_aperture)(uint8 bus, uint8 device, uint8 function,
size_t size, addr_t *_apertureBase);
aperture_id (*map_custom_aperture)(gart_bus_module_info *module,
addr_t *_apertureBase);
status_t (*unmap_aperture)(aperture_id id);
status_t (*get_aperture_info)(aperture_id id, aperture_info *info);
/* ---
masks for capability ID register bits
--- */
#define AGP_id_mask 0x000000ff /* AGP capability identification, contains value 0x02 for AGP device */
#define AGP_next_ptr 0x0000ff00 /* pointer to next item in PCI capabilities list, contains 0x00 if this is last item */
#define AGP_next_ptr_shift 8
#define AGP_rev_minor 0x000f0000 /* AGP Revision minor number reported */
#define AGP_rev_minor_shift 16
#define AGP_rev_major 0x00f00000 /* AGP Revision major number reported */
#define AGP_rev_major_shift 20
status_t (*allocate_memory)(aperture_id id, size_t size,
size_t alignment, uint32 flags, addr_t *_apertureBase,
addr_t *_physicalBase);
status_t (*deallocate_memory)(aperture_id id, addr_t apertureBase);
status_t (*reserve_aperture)(aperture_id id, size_t size,
addr_t *_apertureBase);
status_t (*unreserve_aperture)(aperture_id id, addr_t apertureBase);
status_t (*bind_aperture)(aperture_id id, area_id area, addr_t base,
size_t size, size_t alignment, bool physical,
addr_t reservedBase, addr_t *_apertureBase);
status_t (*unbind_aperture)(aperture_id id, addr_t apertureBase);
} agp_gart_module_info;
#define B_AGP_GART_MODULE_NAME "bus_managers/agp_gart/v0"
/* ---
masks for status and command register bits
--- */
#define AGP_2_1x 0x00000001 /* AGP Revision 2.0 1x speed transfer mode */
#define AGP_2_2x 0x00000002 /* AGP Revision 2.0 2x speed transfer mode */
#define AGP_2_4x 0x00000004 /* AGP Revision 2.0 4x speed transfer mode */
#define AGP_3_4x 0x00000001 /* AGP Revision 3.0 4x speed transfer mode */
#define AGP_3_8x 0x00000002 /* AGP Revision 3.0 8x speed transfer mode */
#define AGP_rates 0x00000007 /* mask for supported rates info */
#define AGP_rate_rev 0x00000008 /* 0 if AGP Revision 2.0 or earlier rate scheme, 1 if AGP Revision 3.0 rate scheme */
#define AGP_FW 0x00000010 /* 1 if fastwrite transfers supported */
#define AGP_4G 0x00000020 /* 1 if adresses above 4G bytes supported */
#define AGP_SBA 0x00000200 /* 1 if sideband adressing supported */
#define AGP_RQ 0xff000000 /* max. number of enqueued AGP command requests supported, minus one */
#define AGP_RQ_shift 24
struct agp_gart_for_bus_module_info {
module_info info;
};
#define B_AGP_GART_FOR_BUS_MODULE_NAME "bus_managers/agp_gart/bus/v0"
/* ---
masks for command register bits
--- */
#define AGP_enable 0x00000100 /* set to 1 if AGP should be enabled */
struct agp_gart_bus_module_info {
module_info info;
// TODO: add some stuff for non-generic AGP support as well
#ifdef __cplusplus
}
#endif
status_t (*create_aperture)(uint8 bus, uint8 device, uint8 function,
size_t size, void **_aperture);
void (*delete_aperture)(void *aperture);
#endif
status_t (*get_aperture_info)(void *aperture, aperture_info *info);
status_t (*set_aperture_size)(void *aperture, size_t size);
status_t (*bind_page)(void *aperture, uint32 offset,
addr_t physicalAddress);
status_t (*unbind_page)(void *aperture, uint32 offset);
void (*flush_tlbs)(void *aperture);
};
/* defines for capability ID register bits */
#define AGP_REV_MINOR 0x000f0000 /* AGP Revision minor number reported */
#define AGP_REV_MINOR_SHIFT 16
#define AGP_REV_MAJOR 0x00f00000 /* AGP Revision major number reported */
#define AGP_REV_MAJOR_SHIFT 20
/* defines for status and command register bits */
#define AGP_2_1x 0x00000001 /* AGP Revision 2.0 1x speed transfer mode */
#define AGP_2_2x 0x00000002 /* AGP Revision 2.0 2x speed transfer mode */
#define AGP_2_4x 0x00000004 /* AGP Revision 2.0 4x speed transfer mode */
#define AGP_3_4x 0x00000001 /* AGP Revision 3.0 4x speed transfer mode */
#define AGP_3_8x 0x00000002 /* AGP Revision 3.0 8x speed transfer mode */
#define AGP_RATE_MASK 0x00000007 /* mask for supported rates info */
#define AGP_3_MODE 0x00000008 /* 0 if AGP Revision 2.0 or earlier rate scheme,
* 1 if AGP Revision 3.0 rate scheme */
#define AGP_FAST_WRITE 0x00000010 /* 1 if fast write transfers supported */
#define AGP_ABOVE_4G 0x00000020 /* 1 if adresses above 4G bytes supported */
#define AGP_SBA 0x00000200 /* 1 if side band adressing supported */
#define AGP_REQUEST 0xff000000 /* max. number of enqueued AGP command requests
* supported, minus one */
#define AGP_REQUEST_SHIFT 24
/* masks for command register bits */
#define AGP_ENABLE 0x00000100 /* set to 1 if AGP should be enabled */
#endif /* _AGP_H_ */

102
src/add-ons/accelerants/nvidia/engine/nv_agp.c
View File

@ -10,7 +10,9 @@
static void nv_agp_list_info(agp_info ai);
static void nv_agp_list_active(uint32 cmd);
status_t nv_agp_setup(bool enable_agp)
status_t
nv_agp_setup(bool enable_agp)
{
nv_nth_agp_info nai;
nv_cmd_agp nca;
@ -24,8 +26,7 @@ status_t nv_agp_setup(bool enable_agp)
/* first try to enable FW support on our card if user requested this
* ('unsupported' tweak!)
* This has no effect on PCI cards. */
if (si->settings.unhide_fw)
{
if (si->settings.unhide_fw) {
uint32 reg;
LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", NV_REG32(NV32_NVSTRAPINFO2)));
@ -43,15 +44,13 @@ status_t nv_agp_setup(bool enable_agp)
nca.magic = nai.magic = NV_PRIVATE_DATA_MAGIC;
/* contact driver and get a pointer to the registers and shared data */
for (index = 0; index < 8; index++)
{
for (index = 0; index < 8; index++) {
/* get nth AGP device info */
nai.index = index;
ioctl(fd, NV_GET_NTH_AGP_INFO, &nai, sizeof(nai));
/* abort if no agp busmanager found */
if (!nai.agp_bus)
{
if (!nai.agp_bus) {
LOG(4,("AGP: no AGP busmanager found.\n"));
/* don't touch AGP command register, we don't know what has been setup:
* touching it anyway might 'hang' the graphics card! */
@ -60,8 +59,7 @@ status_t nv_agp_setup(bool enable_agp)
}
/* exit if we didn't get device info for this index */
if (!nai.exist)
{
if (!nai.exist) {
if (index != 0)
LOG(4,("AGP: end of AGP capable devices list.\n"));
else
@ -72,12 +70,11 @@ status_t nv_agp_setup(bool enable_agp)
LOG(4,("AGP: AGP capable device #%d:\n", (index + 1)));
/* see if we are this one */
if ((nai.agpi.device_id == si->device_id) &&
(nai.agpi.vendor_id == si->vendor_id) &&
(nai.agpi.bus == si->bus) &&
(nai.agpi.device == si->device) &&
(nai.agpi.function == si->function))
{
if (nai.agpi.device_id == si->device_id
&& nai.agpi.vendor_id == si->vendor_id
&& nai.agpi.bus == si->bus
&& nai.agpi.device == si->device
&& nai.agpi.function == si->function) {
LOG(4,("AGP: (this is the device this accelerant controls)\n"));
agp = true;
/* remember our info */
@ -95,8 +92,7 @@ status_t nv_agp_setup(bool enable_agp)
* AGP type cards as nVidia PCI cards still have AGP registers that pretend to
* support AGP.
* We rely on the AGP busmanager to iterate trough this list for us. */
if (!agp)
{
if (!agp) {
LOG(4,("AGP: the graphicscard this accelerant controls is PCI type.\n"));
/* make sure card is set for PCI access */
@ -105,8 +101,7 @@ status_t nv_agp_setup(bool enable_agp)
return B_ERROR;
}
if (si->settings.force_pci || !enable_agp)
{
if (si->settings.force_pci || !enable_agp) {
/* set PCI mode if specified by user in nv.settings */
if (enable_agp)
LOG(4,("AGP: forcing PCI mode (specified in nv.settings)\n"));
@ -117,31 +112,33 @@ status_t nv_agp_setup(bool enable_agp)
* (the AGP speed scheme is of no consequence now) */
nca.cmd = 0x00000000;
ioctl(fd, NV_ENABLE_AGP, &nca, sizeof(nca));
}
else
{
} else {
/* activate AGP mode */
LOG(4,("AGP: activating AGP mode...\n"));
/* let the AGP busmanager worry about what mode to set.. */
nca.cmd = 0xfffffff7;
/* ..but we do need to select the right speed scheme fetched from our card */
if (nv_ai.interface.agp_stat & AGP_rate_rev) nca.cmd |= AGP_rate_rev;
if (nv_ai.interface.status & AGP_3_MODE)
nca.cmd |= AGP_3_MODE;
ioctl(fd, NV_ENABLE_AGP, &nca, sizeof(nca));
/* tell the engine in may use AGP transfers if AGP is up and running */
if (nca.cmd & AGP_enable) si->engine.agp_mode = true;
if (nca.cmd & AGP_ENABLE)
si->engine.agp_mode = true;
}
/* list mode now activated,
* make sure we have the correct speed scheme for logging */
nv_agp_list_active(nca.cmd | (nv_ai.interface.agp_stat & AGP_rate_rev));
nv_agp_list_active(nca.cmd | (nv_ai.interface.status & AGP_3_MODE));
/* extra check */
LOG(4,("AGP: graphics card AGPCMD register readback $%08x\n", CFGR(AGPCMD)));
return B_OK;
}
static void nv_agp_list_info(agp_info ai)
static void
nv_agp_list_info(agp_info ai)
{
/*
list device
@ -158,45 +155,46 @@ static void nv_agp_list_info(agp_info ai)
list capabilities
*/
LOG(4,("AGP: this device supports AGP specification %d.%d;\n",
((ai.interface.agp_cap_id & AGP_rev_major) >> AGP_rev_major_shift),
((ai.interface.agp_cap_id & AGP_rev_minor) >> AGP_rev_minor_shift)));
((ai.interface.capability_id & AGP_REV_MAJOR) >> AGP_REV_MAJOR_SHIFT),
((ai.interface.capability_id & AGP_REV_MINOR) >> AGP_REV_MINOR_SHIFT)));
/* the AGP devices determine AGP speed scheme version used on power-up/reset */
if (!(ai.interface.agp_stat & AGP_rate_rev))
{
if (!(ai.interface.status & AGP_3_MODE)) {
/* AGP 2.0 scheme applies */
if (ai.interface.agp_stat & AGP_2_1x)
if (ai.interface.status & AGP_2_1x)
LOG(4,("AGP: AGP 2.0 1x mode is available\n"));
if (ai.interface.agp_stat & AGP_2_2x)
if (ai.interface.status & AGP_2_2x)
LOG(4,("AGP: AGP 2.0 2x mode is available\n"));
if (ai.interface.agp_stat & AGP_2_4x)
if (ai.interface.status & AGP_2_4x)
LOG(4,("AGP: AGP 2.0 4x mode is available\n"));
}
else
{
} else {
/* AGP 3.0 scheme applies */
if (ai.interface.agp_stat & AGP_3_4x)
if (ai.interface.status & AGP_3_4x)
LOG(4,("AGP: AGP 3.0 4x mode is available\n"));
if (ai.interface.agp_stat & AGP_3_8x)
if (ai.interface.status & AGP_3_8x)
LOG(4,("AGP: AGP 3.0 8x mode is available\n"));
}
if (ai.interface.agp_stat & AGP_FW) LOG(4,("AGP: fastwrite transfers are supported\n"));
if (ai.interface.agp_stat & AGP_SBA) LOG(4,("AGP: sideband adressing is supported\n"));
if (ai.interface.status & AGP_FAST_WRITE)
LOG(4,("AGP: fastwrite transfers are supported\n"));
if (ai.interface.status & AGP_SBA)
LOG(4,("AGP: sideband adressing is supported\n"));
LOG(4,("AGP: %d queued AGP requests can be handled.\n",
(((ai.interface.agp_stat & AGP_RQ) >> AGP_RQ_shift) + 1)));
(((ai.interface.status & AGP_REQUEST) >> AGP_REQUEST_SHIFT) + 1)));
/*
list current settings,
make sure we have the correct speed scheme for logging
*/
nv_agp_list_active(ai.interface.agp_cmd | (ai.interface.agp_stat & AGP_rate_rev));
nv_agp_list_active(ai.interface.command
| (ai.interface.status & AGP_3_MODE));
}
static void nv_agp_list_active(uint32 cmd)
static void
nv_agp_list_active(uint32 cmd)
{
LOG(4,("AGP: listing settings now in use:\n"));
if (!(cmd & AGP_rate_rev))
{
if (!(cmd & AGP_3_MODE)) {
/* AGP 2.0 scheme applies */
if (cmd & AGP_2_1x)
LOG(4,("AGP: AGP 2.0 1x mode is set\n"));
@ -204,20 +202,20 @@ static void nv_agp_list_active(uint32 cmd)
LOG(4,("AGP: AGP 2.0 2x mode is set\n"));
if (cmd & AGP_2_4x)
LOG(4,("AGP: AGP 2.0 4x mode is set\n"));
}
else
{
} else {
/* AGP 3.0 scheme applies */
if (cmd & AGP_3_4x)
LOG(4,("AGP: AGP 3.0 4x mode is set\n"));
if (cmd & AGP_3_8x)
LOG(4,("AGP: AGP 3.0 8x mode is set\n"));
}
if (cmd & AGP_FW) LOG(4,("AGP: fastwrite transfers are enabled\n"));
if (cmd & AGP_SBA) LOG(4,("AGP: sideband adressing is enabled\n"));
if (cmd & AGP_FAST_WRITE)
LOG(4,("AGP: fastwrite transfers are enabled\n"));
if (cmd & AGP_SBA)
LOG(4,("AGP: sideband adressing is enabled\n"));
LOG(4,("AGP: max. AGP queued request depth is set to %d\n",
(((cmd & AGP_RQ) >> AGP_RQ_shift) + 1)));
if (cmd & AGP_enable)
(((cmd & AGP_REQUEST) >> AGP_REQUEST_SHIFT) + 1)));
if (cmd & AGP_ENABLE)
LOG(4,("AGP: the AGP interface is enabled.\n"));
else
LOG(4,("AGP: the AGP interface is disabled.\n"));

144
src/add-ons/accelerants/via/engine/agp.c
View File

@ -7,10 +7,9 @@
#include <unistd.h>
#include "std.h"
static void eng_agp_list_info(agp_info ai);
static void eng_agp_list_active(uint32 cmd);
status_t eng_agp_setup(void)
status_t
eng_agp_setup(void)
{
eng_nth_agp_info nai;
eng_cmd_agp nca;
@ -18,37 +17,17 @@ status_t eng_agp_setup(void)
agp_info eng_ai;
bool agp = false;
/* first try to enable FW support on our card if user requested this
* ('unsupported' tweak!)
* This has no effect on PCI cards. */
// if (si->settings.unhide_fw)
// {
// uint32 reg;
// LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2)));
// LOG(4, ("AGP: attempting to enable fastwrite support..\n"));
/* 'force' FW support */
// reg = (ENG_REG32(RG32_NVSTRAPINFO2) & ~0x00000800);
/* enable strapinfo overwrite */
// ENG_REG32(RG32_NVSTRAPINFO2) = (reg | 0x80000000);
// LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2)));
// }
/* set the magic number so the via kerneldriver knows we're for real */
nca.magic = nai.magic = VIA_PRIVATE_DATA_MAGIC;
/* contact driver and get a pointer to the registers and shared data */
for (index = 0; index < 8; index++)
{
for (index = 0; index < 8; index++) {
/* get nth AGP device info */
nai.index = index;
ioctl(fd, ENG_GET_NTH_AGP_INFO, &nai, sizeof(nai));
/* abort if no agp busmanager found */
if (!nai.agp_bus)
{
if (!nai.agp_bus) {
LOG(4,("AGP: no AGP busmanager found.\n"));
/* don't touch AGP command register, we don't know what has been setup:
* touching it anyway might 'hang' the graphics card! */
@ -57,8 +36,7 @@ status_t eng_agp_setup(void)
}
/* exit if we didn't get device info for this index */
if (!nai.exist)
{
if (!nai.exist) {
if (index != 0)
LOG(4,("AGP: end of AGP capable devices list.\n"));
else
@ -69,20 +47,16 @@ status_t eng_agp_setup(void)
LOG(4,("AGP: AGP capable device #%d:\n", (index + 1)));
/* see if we are this one */
if ((nai.agpi.device_id == si->device_id) &&
(nai.agpi.vendor_id == si->vendor_id) &&
(nai.agpi.bus == si->bus) &&
(nai.agpi.device == si->device) &&
(nai.agpi.function == si->function))
{
if (nai.agpi.device_id == si->device_id
&& nai.agpi.vendor_id == si->vendor_id
&& nai.agpi.bus == si->bus
&& nai.agpi.device == si->device
&& nai.agpi.function == si->function) {
LOG(4,("AGP: (this is the device this accelerant controls)\n"));
agp = true;
/* remember our info */
eng_ai = nai.agpi;
}
/* log capabilities */
eng_agp_list_info(nai.agpi);
}
/* if our card is not an AGP type, abort here */
@ -92,8 +66,7 @@ status_t eng_agp_setup(void)
* AGP type cards as PCI cards still might have AGP registers that pretend to
* support AGP.
* We rely on the AGP busmanager to iterate trough this list for us. */
if (!agp)
{
if (!agp) {
LOG(4,("AGP: the graphicscard this accelerant controls is PCI type.\n"));
/* make sure card is set for PCI access */
@ -102,8 +75,7 @@ status_t eng_agp_setup(void)
return B_ERROR;
}
if (si->settings.force_pci)
{
if (si->settings.force_pci) {
/* set PCI mode if specified by user in skel.settings */
LOG(4,("AGP: forcing PCI mode (specified in via.settings)\n"));
@ -111,106 +83,20 @@ status_t eng_agp_setup(void)
* (the AGP speed scheme is of no consequence now) */
nca.cmd = 0x00000000;
ioctl(fd, ENG_ENABLE_AGP, &nca, sizeof(nca));
}
else
{
} else {
/* activate AGP mode */
LOG(4,("AGP: activating AGP mode...\n"));
/* let the AGP busmanager worry about what mode to set.. */
nca.cmd = 0xfffffff7;
/* ..but we do need to select the right speed scheme fetched from our card */
if (eng_ai.interface.agp_stat & AGP_rate_rev) nca.cmd |= AGP_rate_rev;
if (eng_ai.interface.status & AGP_3_MODE)
nca.cmd |= AGP_3_MODE;
ioctl(fd, ENG_ENABLE_AGP, &nca, sizeof(nca));
}
/* list mode now activated,
* make sure we have the correct speed scheme for logging */
eng_agp_list_active(nca.cmd | (eng_ai.interface.agp_stat & AGP_rate_rev));
/* extra check */
// LOG(4,("AGP: graphics card AGPCMD register readback $%08x\n", CFGR(AGPCMD)));
return B_OK;
}
static void eng_agp_list_info(agp_info ai)
{
/*
list device
*/
if (ai.class_base == PCI_display)
LOG(4,("AGP: device is a graphicscard, subclass ID is $%02x\n", ai.class_sub));
else
LOG(4,("AGP: device is a hostbridge, subclass ID is $%02x\n", ai.class_sub));
LOG(4,("AGP: vendor ID $%04x\n", ai.vendor_id));
LOG(4,("AGP: device ID $%04x\n", ai.device_id));
LOG(4,("AGP: bus %d, device %d, function %d\n", ai.bus, ai.device, ai.function));
/*
list capabilities
*/
LOG(4,("AGP: this device supports AGP specification %d.%d;\n",
((ai.interface.agp_cap_id & AGP_rev_major) >> AGP_rev_major_shift),
((ai.interface.agp_cap_id & AGP_rev_minor) >> AGP_rev_minor_shift)));
/* the AGP devices determine AGP speed scheme version used on power-up/reset */
if (!(ai.interface.agp_stat & AGP_rate_rev))
{
/* AGP 2.0 scheme applies */
if (ai.interface.agp_stat & AGP_2_1x)
LOG(4,("AGP: AGP 2.0 1x mode is available\n"));
if (ai.interface.agp_stat & AGP_2_2x)
LOG(4,("AGP: AGP 2.0 2x mode is available\n"));
if (ai.interface.agp_stat & AGP_2_4x)
LOG(4,("AGP: AGP 2.0 4x mode is available\n"));
}
else
{
/* AGP 3.0 scheme applies */
if (ai.interface.agp_stat & AGP_3_4x)
LOG(4,("AGP: AGP 3.0 4x mode is available\n"));
if (ai.interface.agp_stat & AGP_3_8x)
LOG(4,("AGP: AGP 3.0 8x mode is available\n"));
}
if (ai.interface.agp_stat & AGP_FW) LOG(4,("AGP: fastwrite transfers are supported\n"));
if (ai.interface.agp_stat & AGP_SBA) LOG(4,("AGP: sideband adressing is supported\n"));
LOG(4,("AGP: %d queued AGP requests can be handled.\n",
(((ai.interface.agp_stat & AGP_RQ) >> AGP_RQ_shift) + 1)));
/*
list current settings,
make sure we have the correct speed scheme for logging
*/
eng_agp_list_active(ai.interface.agp_cmd | (ai.interface.agp_stat & AGP_rate_rev));
}
static void eng_agp_list_active(uint32 cmd)
{
LOG(4,("AGP: listing settings now in use:\n"));
if (!(cmd & AGP_rate_rev))
{
/* AGP 2.0 scheme applies */
if (cmd & AGP_2_1x)
LOG(4,("AGP: AGP 2.0 1x mode is set\n"));
if (cmd & AGP_2_2x)
LOG(4,("AGP: AGP 2.0 2x mode is set\n"));
if (cmd & AGP_2_4x)
LOG(4,("AGP: AGP 2.0 4x mode is set\n"));
}
else
{
/* AGP 3.0 scheme applies */
if (cmd & AGP_3_4x)
LOG(4,("AGP: AGP 3.0 4x mode is set\n"));
if (cmd & AGP_3_8x)
LOG(4,("AGP: AGP 3.0 8x mode is set\n"));
}
if (cmd & AGP_FW) LOG(4,("AGP: fastwrite transfers are enabled\n"));
if (cmd & AGP_SBA) LOG(4,("AGP: sideband adressing is enabled\n"));
LOG(4,("AGP: max. AGP queued request depth is set to %d\n",
(((cmd & AGP_RQ) >> AGP_RQ_shift) + 1)));
if (cmd & AGP_enable)
LOG(4,("AGP: the AGP interface is enabled.\n"));
else
LOG(4,("AGP: the AGP interface is disabled.\n"));
}

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src/add-ons/kernel/bus_managers/agp/Jamfile
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@ -1,23 +1,13 @@
SubDir HAIKU_TOP src add-ons kernel bus_managers agp ;
SetSubDirSupportedPlatformsBeOSCompatible ;
SubDirC++Flags -fno-rtti ;
UsePrivateHeaders graphics ;
UsePrivateHeaders [ FDirName kernel boot platform $(TARGET_BOOT_PLATFORM) ] ;
UsePrivateHeaders [ FDirName kernel arch $(TARGET_ARCH) ] ;
UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
UsePrivateHeaders graphics kernel ;
Package haiku-agp :
README.html
UPDATE.html
;
Package haiku-agp :
agp :
boot home config add-ons kernel bus_managers ;
Package haiku-agp :
agp.settings :
boot home config settings kernel drivers ;
KernelAddon agp :
KernelAddon agp_gart :
agp.cpp
module.cpp
;

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src/add-ons/kernel/bus_managers/agp/README.html
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<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
<meta name="GENERATOR" content="The DarkSite">
<title>Readme for the AGP busmanager module</title>
</head>
<body>
<h2 align="center">AGP busmanager module</h2></align><br><br>
<hr>
<h3><strong>NOTE PLEASE:</strong><br>
You use this software at your own risk! Although I don't expect it to damage your PC, videocard or Monitor, I cannot guarantee this!</h3>
<hr>
<h2>Supported devices:</h2>
<ul>
<li>all 'PCI-class' host bridges with AGP interface;
<li>all 'PCI-class' graphics cards with AGP interface.
</ul>
<br>
<hr>
<h2>Features:</h2>
<ul>
<li>Can enable AGP transfers including SBA (sideband adressing);
<li>Sets up AGP maximum request depth.
<li>Can enable PCI FW (fastwrites);
</ul>
<strong>Known limitations:</strong>
<ul>
<li>No GART and AGP aperture support (yet);
<li>No AGP3.0 specific feature support (yet), such as 'asynchronous request size', 'calibration cycle' and 'isochronous transfers'. The registers and register-fields for these features are currently programmed to default 'safe' modes or disabled on power-up.
</ul>
<br>
<hr>
<h2>Installation:</h2>
This module will install in the user part of the BeOS, so not in the system part where the official modules are.<br>
BeOS first checks (during boot) if there are 'user-addons' that should be loaded for a device. If not, it loads it's own add-ons (if any). You can select if this module should be loaded by hitting the spacebar as soon as the BeOS 'icons' screen appears. If you select <strong>disable user addons</strong> the system will not load it or other 'user-addons'. If you don't do anything, the system will load the AGP busmanager module if requested by a driver.<br>
<br>
<strong>Note:</strong> This might turn out to be handy if you run into trouble upon testing the module, or if you are 'tweaking' the agp.settings file...<br>
<br><br>
<strong>actual INSTALLATION:</strong><br>
<br>
Doubleclick on the install.sh file and follow the instructions. You have to reboot in order to use the AGP busmanager module. Make sure you read the <strong>Settings</strong> information below before you do that...<br>
<br>
<br>
<strong>alternate INSTALLATION method:</strong><br>
<br>
Unzip the zip file that contains the module to the root folder. Now reboot and you should be using it if requested by a driver.<br>
<br>
<br>
<strong>DE-INSTALLATION:</strong><br>
<br>
Currently there's no uninstall script included. Just do it manually:<br>
<br>
Delete the <strong>agp</strong> file in <strong>home/config/add-ons/kernel/bus_managers/</strong><br>
Delete the <strong>agp.settings</strong> file in <strong>home/config/settings/kernel/drivers/</strong><br>
<br>
You have to reboot in order to apply the original configuration.<br>
<br>
<br>
<hr>
<a name="settings"></a><h2>Settings:</h2><br>
Please read this information carefully *before* installing and using the AGP busmanager module. It might spare you some trouble afterwards..<br>
<p>The module uses a file named <strong>agp.settings</strong> to determine how to setup your AGP bus(es). After installation this file will be located at <strong>home/config/settings/kernel/drivers/</strong>. You shouldn't touch this file unless your system becomes unstable with the AGP mode active. It has a default configuration for maximum effect, but you might have to scale back a little if your system gives trouble... Anyway, read the nifty details below.<br>
<br>
<strong>Note:</strong> The module only reads this file during it's initialisation. This means that you have to reboot in order to let changes take effect.<br>
<strong>Note also:</strong> A graphicsdriver may or may not further reduce the mode that gets setup by the AGP busmanager. See the graphicsdriver documentation for more info on this.<br>
<br>
<br>
<br>
<strong>agp.settings module configuration:</strong><br>
<ul>
<li><strong>max_speed:</strong> (disabled by default)<br>
This option enables you to set a maximum speed that may be setup by the module, instead of the maximum your system reports being capable of. Valid values are 1,2,4 and 8. If a value makes no sense (because the settings file contains an illegal value, or the hardware uses a speed-scheme that's not capable of setting a specific requested max. speed) the module will take the next logical lower one: PCI mode being the lowest speed setting (which is what you were using before you installed this module).<br>
This option is disabled by default (preceded by a '#').<br>
<li><strong>block_agp:</strong> (set to 'false' by default)<br>
If set to 'true' this option blocks use of AGP transfers entirely including PCI fastwrites: so fallback to standard 'old-fashioned' PCI mode.
<li><strong>block_sba:</strong> (set to 'false' by default)<br>
If set to 'true' this option blocks use of sideband adressing if at least one of the devices on the bus is pre-AGP3.0. Sideband adressing speeds up AGP transfers a bit because it's a seperate (low-speed) communications 'channel' that's used alongside the main transfer channel concurrently. So this enables 'full-duplex' communications, while disabling SBA forces the hardware to use 'half-duplex' communications. SBA is a requirement for AGP3 compliance, so if AGP3 is in effect, this setting is ignored.
<li><strong>block_fw:</strong> (set to 'true' by default)<br>
If set to 'true' this option blocks use of PCI fastwrites. PCI fastwrites work in the same speed AGP transfers work. This means PCI fastwrites are faster in AGP4x mode than they are in AGP2x mode (for instance). PCI fastwrites are used whenever the system (CPU) initiates transfers to the graphicscard, while 'standard PCI' or AGP transfers are used if the graphicscard's acceleration engine (GPU) initiates transfers to or from the system respectively.<br>
This means that PCI FW is the only AGP 'feature' that has an effect on the graphics speed on BeOS as it is currently, except for users of the nVidia driver(s). The use of AGP transfers require graphicsdriver support, which is built-in inside the 2D and 3D nVidia drivers. Note please that PCI fastwrites might still be used for texture loading for accelerated 3D...<br>
<strong>Note:</strong><br>
PCI FW support was first introduced with the AGP2.0 specification: that is, devices that support upto and including AGP4X mode are candidates to have this feature.
</ul>
<hr>
<br>
<a href="mailto:info.be-hold@inter.nl.net">Rudolf Cornelissen.</a>
<p>(Page last updated on April 11, 2006)</p>
</body>
</html>

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<html>
<head>
<title>Changes</title>
</head>
<body>
<p><h2>Changes done for each module version:</h2></p>
<p><h1>agp_module 0.02 (Rudolf)</h1></p>
<ul>
<li>Reversed order of programming devices when AGP mode is requested to be disabled. The order of programming devices now adheres to the official AGP specification (missed this item before). This fixes potential coldstart trouble on nVidia cards at least (confirmed a GeForce 4 MX4000);
<li>Modified agp.setting for blocking PCI fastwrites (block_fw) to be set to true by default: Fastwrites tend to create trouble on some systems outthere (most notably systems with ATI graphics cards).
</ul>
<p><h1>agp_module 0.01 (Rudolf)</h1></p>
<ul>
<li>Initial release.
</ul>
<p><h1>Still todo:</h1></p>
<ul>
<li>a lot, in due time ;-)
</ul>
</p>
</body>
</html>

1553
src/add-ons/kernel/bus_managers/agp/agp.cpp
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src/add-ons/kernel/bus_managers/agp/agp.h
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#if !defined(AGP_PROTO_H)
#define AGP_PROTO_H
#include <KernelExport.h>
#include <PCI.h>
#include "AGP.h"
#define AGP_DEBUG
#ifdef AGP_DEBUG
#define TRACE dprintf
#else
#define TRACE silent
#endif
void silent(const char *, ... );
status_t init(void);
void uninit(void);
void enable_agp (uint32 *command);
long get_nth_agp_info (long index, agp_info *info);
#endif

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src/add-ons/kernel/bus_managers/agp/agp.settings
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# Settings file for the agp busmanager
#
# This file should be moved to the directory
# ~/config/settings/kernel/drivers/
#
#modifying the settings below will restrict the busmanager in autoselecting the best mode useable:
#max_speed 2 # max AGP speed that may be used (valid are 1,2,4 or 8)
block_agp false # if true blocks use of AGP entirely: so fallback to PCI mode
block_sba false # if true blocks use of 'sideband adressing' if possible
block_fw true # if true blocks use of 'fastwrites'

66
src/add-ons/kernel/bus_managers/agp/module.cpp
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/*
* Copyright (c) 2003-2004, Niels S. Reedijk,
* Rudolf Cornelissen
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "agp.h"
//void function for debug messages if logging disabled
void silent(const char *, ... ) {}
static int32
bus_std_ops(int32 op, ...)
{
switch(op) {
case B_MODULE_INIT:
TRACE("agp_man: bus module V0.02: init\n");
if (init() != B_OK)
return ENODEV;
break;
case B_MODULE_UNINIT:
TRACE("agp_man: bus module V0.02: uninit\n");
uninit();
break;
default:
return EINVAL;
}
return B_OK;
}
static struct agp_module_info sAGPModuleInfo = {
{
{
B_AGP_MODULE_NAME,
B_KEEP_LOADED, // Keep loaded, even if no driver requires it
bus_std_ops
},
NULL // the rescan function
},
get_nth_agp_info,
enable_agp
};
module_info *modules[] = {
(module_info *)&sAGPModuleInfo,
NULL
};

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@ -1,5 +1,6 @@
SubDir HAIKU_TOP src add-ons kernel busses ;
SubInclude HAIKU_TOP src add-ons kernel busses agp_gart ;
SubInclude HAIKU_TOP src add-ons kernel busses ide ;
SubInclude HAIKU_TOP src add-ons kernel busses scsi ;
SubInclude HAIKU_TOP src add-ons kernel busses usb ;

20
src/add-ons/kernel/busses/agp_gart/Jamfile Normal file
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SubDir HAIKU_TOP src add-ons kernel busses agp_gart ;
SetSubDirSupportedPlatformsBeOSCompatible ;
SubDirC++Flags -fno-rtti ;
UsePrivateHeaders [ FDirName kernel arch $(TARGET_ARCH) ] ;
UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
UsePrivateHeaders [ FDirName graphics common ] ;
UsePrivateHeaders drivers graphics kernel ;
KernelAddon <agp_gart>intel :
intel_gart.cpp
kernel_cpp.cpp
;
SEARCH on [ FGristFiles
kernel_cpp.cpp
] = [ FDirName $(HAIKU_TOP) src system kernel util ] ;

486
src/add-ons/kernel/busses/agp_gart/intel_gart.cpp Normal file
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/*
* Copyright 2008, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#include <AreaKeeper.h>
#include <intel_extreme.h>
#include <stdlib.h>
#include <AGP.h>
#include <KernelExport.h>
#include <PCI.h>
#define TRACE_INTEL
#ifdef TRACE_INTEL
# define TRACE(x...) dprintf("\33[33magp-intel:\33[0m " x)
#else
# define TRACE(x...) ;
#endif
#ifndef __HAIKU__
# define B_KERNEL_READ_AREA 0
# define B_KERNEL_WRITE_AREA 0
#endif
/* read and write to PCI config space */
#define get_pci_config(info, offset, size) \
(sPCI->read_pci_config((info).bus, (info).device, (info).function, \
(offset), (size)))
#define set_pci_config(info, offset, size, value) \
(sPCI->write_pci_config((info).bus, (info).device, (info).function, \
(offset), (size), (value)))
#define write32(address, data) \
(*((volatile uint32 *)(address)) = (data))
#define read32(address) \
(*((volatile uint32 *)(address)))
const struct supported_device {
uint32 bridge_id;
uint32 display_id;
uint32 type;
const char *name;
} kSupportedDevices[] = {
{0x29b0, 0x29b2, INTEL_TYPE_G33, "G33"},
{0x29c0, 0x29c2, INTEL_TYPE_G33, "Q35"},
{0x29d0, 0x29d2, INTEL_TYPE_G33, "Q33"},
};
struct intel_info {
pci_info bridge;
pci_info display;
uint32 type;
uint32 *gtt_base;
addr_t gtt_physical_base;
area_id gtt_area;
size_t gtt_entries;
size_t gtt_stolen_entries;
uint32 *registers;
area_id registers_area;
addr_t aperture_base;
addr_t aperture_physical_base;
area_id aperture_area;
size_t aperture_size;
size_t aperture_stolen_size;
addr_t scratch_page;
area_id scratch_area;
};
static intel_info sInfo;
static pci_module_info *sPCI;
static bool
has_display_device(pci_info &info, uint32 deviceID)
{
for (uint32 index = 0; sPCI->get_nth_pci_info(index, &info) == B_OK;
index++) {
if (info.vendor_id != VENDOR_ID_INTEL
|| info.device_id != deviceID
|| info.class_base != PCI_display)
continue;
return true;
}
return false;
}
static void
determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
{
// read stolen memory from the PCI configuration of the PCI bridge
uint16 memoryConfig = get_pci_config(info.bridge,
INTEL_GRAPHICS_MEMORY_CONTROL, 2);
size_t memorySize = 1 << 20; // 1 MB
gttSize = 0;
stolenSize = 0;
if (info.type == INTEL_TYPE_965) {
switch (memoryConfig & i965_GTT_MASK) {
case i965_GTT_128K:
gttSize = 128 << 10;
break;
case i965_GTT_256K:
gttSize = 256 << 10;
break;
case i965_GTT_512K:
gttSize = 512 << 10;
break;
}
} else if (info.type == INTEL_TYPE_G33) {
switch (memoryConfig & G33_GTT_MASK) {
case G33_GTT_1M:
gttSize = 1 << 20;
break;
case G33_GTT_2M:
gttSize = 2 << 20;
break;
}
} else {
#if 0
// older models have the GTT as large as their frame buffer mapping
// TODO: check if the i9xx version works with the i8xx chips as well
size_t frameBufferSize = 0;
if ((info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_8xx) {
if ((info.device_type & INTEL_TYPE_83x) != 0
&& (memoryConfig & MEMORY_MASK) == i830_FRAME_BUFFER_64M)
frameBufferSize = 64 << 20;
else
frameBufferSize = 128 << 20;
} else if ((info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx)
frameBufferSize = info.pci->u.h0.base_register_sizes[2];
gttSize = frameBufferSize / 1024;
#endif
}
#if 0
// TODO: test with different models!
if (info.device_type == (INTEL_TYPE_8xx | INTEL_TYPE_83x)) {
switch (memoryConfig & STOLEN_MEMORY_MASK) {
case i830_LOCAL_MEMORY_ONLY:
// TODO: determine its size!
break;
case i830_STOLEN_512K:
memorySize >>= 1;
break;
case i830_STOLEN_8M:
memorySize *= 8;
break;
}
} else if (info.device_type == (INTEL_TYPE_8xx | INTEL_TYPE_85x)
|| (info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx)
#endif
{
switch (memoryConfig & STOLEN_MEMORY_MASK) {
case i855_STOLEN_MEMORY_4M:
memorySize *= 4;
break;
case i855_STOLEN_MEMORY_8M:
memorySize *= 8;
break;
case i855_STOLEN_MEMORY_16M:
memorySize *= 16;
break;
case i855_STOLEN_MEMORY_32M:
memorySize *= 32;
break;
case i855_STOLEN_MEMORY_48M:
memorySize *= 48;
break;
case i855_STOLEN_MEMORY_64M:
memorySize *= 64;
break;
case i855_STOLEN_MEMORY_128M:
memorySize *= 128;
break;
case i855_STOLEN_MEMORY_256M:
memorySize *= 256;
break;
}
}
stolenSize = memorySize - gttSize - 4096;
}
static void
set_gtt_entry(intel_info &info, uint32 offset, addr_t physicalAddress)
{
write32(info.gtt_base + (offset >> GTT_PAGE_SHIFT),
(uint32)physicalAddress | GTT_ENTRY_VALID);
}
static void
intel_unmap(intel_info &info)
{
delete_area(info.registers_area);
delete_area(info.gtt_area);
delete_area(info.scratch_area);
delete_area(info.aperture_area);
info.aperture_size = 0;
}
static status_t
intel_map(intel_info &info)
{
info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4);
size_t gttSize, stolenSize;
determine_memory_sizes(info, gttSize, stolenSize);
info.gtt_entries = gttSize / 4096;
info.gtt_stolen_entries = stolenSize / 4096;
dprintf("GTT base %lx, size %lu, entries %lu, stolen %lu\n", info.gtt_physical_base,
gttSize, info.gtt_entries, stolenSize);
int fbIndex = 0;
int mmioIndex = 1;
if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
// for some reason Intel saw the need to change the order of the mappings
// with the introduction of the i9xx family
mmioIndex = 0;
fbIndex = 2;
}
AreaKeeper gttMapper;
info.gtt_area = gttMapper.Map("intel GMCH gtt",
(void *)info.gtt_physical_base, gttSize, B_ANY_KERNEL_ADDRESS,
B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void **)&info.gtt_base);
if (gttMapper.InitCheck() < B_OK) {
dprintf("agp_intel: could not map GTT!\n");
return info.gtt_area;
}
AreaKeeper mmioMapper;
info.registers_area = mmioMapper.Map("intel GMCH mmio",
(void *)info.display.u.h0.base_registers[mmioIndex],
info.display.u.h0.base_register_sizes[mmioIndex], B_ANY_KERNEL_ADDRESS,
B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void **)&info.registers);
if (mmioMapper.InitCheck() < B_OK) {
dprintf("agp_intel: could not map memory I/O!\n");
return info.registers_area;
}
void *scratchAddress;
AreaKeeper scratchCreator;
info.scratch_area = scratchCreator.Create("intel GMCH scratch",
&scratchAddress, B_ANY_KERNEL_ADDRESS, B_PAGE_SIZE, B_FULL_LOCK,
B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA);
if (scratchCreator.InitCheck() < B_OK) {
dprintf("agp_intel: could not create scratch page!\n");
return info.scratch_area;
}
physical_entry entry;
if (get_memory_map(scratchAddress, B_PAGE_SIZE, &entry, 1) != B_OK)
return B_ERROR;
info.aperture_physical_base = info.display.u.h0.base_registers[fbIndex];
info.aperture_stolen_size = stolenSize;
if (info.aperture_size == 0)
info.aperture_size = info.display.u.h0.base_register_sizes[0];
AreaKeeper apertureMapper;
info.aperture_area = apertureMapper.Map("intel graphics aperture",
(void *)info.aperture_physical_base, info.aperture_size,
B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
B_READ_AREA | B_WRITE_AREA, (void **)&info.aperture_base);
if (apertureMapper.InitCheck() < B_OK) {
// try again without write combining
dprintf(DEVICE_NAME ": enabling write combined mode failed.\n");
info.aperture_area = apertureMapper.Map("intel graphics aperture",
(void *)info.aperture_physical_base, info.aperture_size,
B_ANY_KERNEL_BLOCK_ADDRESS, B_READ_AREA | B_WRITE_AREA,
(void **)&info.aperture_base);
}
if (apertureMapper.InitCheck() < B_OK) {
dprintf(DEVICE_NAME ": could not map graphics aperture!\n");
return info.aperture_area;
}
info.scratch_page = (addr_t)entry.address;
gttMapper.Detach();
mmioMapper.Detach();
scratchCreator.Detach();
apertureMapper.Detach();
return B_OK;
}
// #pragma mark - module interface
status_t
intel_create_aperture(uint8 bus, uint8 device, uint8 function, size_t size,
void **_aperture)
{
// TODO: we currently only support a single AGP bridge!
if ((bus != sInfo.bridge.bus || device != sInfo.bridge.device
|| function != sInfo.bridge.function)
&& (bus != sInfo.display.bus || device != sInfo.display.device
|| function != sInfo.display.function))
return B_BAD_VALUE;
sInfo.aperture_size = size;
if (intel_map(sInfo) < B_OK)
return B_ERROR;
uint16 gmchControl = get_pci_config(sInfo.bridge,
INTEL_GRAPHICS_MEMORY_CONTROL, 2) | MEMORY_CONTROL_ENABLED;
set_pci_config(sInfo.bridge, INTEL_GRAPHICS_MEMORY_CONTROL, 2, gmchControl);
write32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL,
sInfo.gtt_physical_base | PAGE_TABLE_ENABLED);
read32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL);
if (sInfo.scratch_page != 0) {
for (size_t i = sInfo.gtt_stolen_entries; i < sInfo.gtt_entries; i++) {
set_gtt_entry(sInfo, i << GTT_PAGE_SHIFT, sInfo.scratch_page);
}
read32(sInfo.gtt_base + sInfo.gtt_entries - 1);
}
asm("wbinvd;");
*_aperture = NULL;
return B_OK;
}
void
intel_delete_aperture(void *aperture)
{
intel_unmap(sInfo);
}
static status_t
intel_get_aperture_info(void *aperture, aperture_info *info)
{
if (info == NULL)
return B_BAD_VALUE;
info->base = sInfo.aperture_base;
info->physical_base = sInfo.aperture_physical_base;
info->size = sInfo.aperture_size;
info->reserved_size = sInfo.aperture_stolen_size;
return B_OK;
}
status_t
intel_set_aperture_size(void *aperture, size_t size)
{
return B_ERROR;
}
static status_t
intel_bind_page(void *aperture, uint32 offset, addr_t physicalAddress)
{
set_gtt_entry(sInfo, offset << GTT_PAGE_SHIFT, physicalAddress);
return B_OK;
}
static status_t
intel_unbind_page(void *aperture, uint32 offset)
{
if (sInfo.scratch_page != 0)
set_gtt_entry(sInfo, offset << GTT_PAGE_SHIFT, sInfo.scratch_page);
return B_OK;
}
void
intel_flush_tlbs(void *aperture)
{
read32(sInfo.gtt_base + sInfo.gtt_entries - 1);
asm("wbinvd;");
}
// #pragma mark -
static status_t
intel_init()
{
TRACE("bus manager init\n");
if (get_module(B_PCI_MODULE_NAME, (module_info **)&sPCI) != B_OK)
return B_ERROR;
bool found = false;
for (uint32 index = 0; sPCI->get_nth_pci_info(index, &sInfo.bridge) == B_OK;
index++) {
if (sInfo.bridge.vendor_id != VENDOR_ID_INTEL
|| sInfo.bridge.class_base != PCI_bridge)
continue;
// check device
for (uint32 i = 0; i < sizeof(kSupportedDevices)
/ sizeof(kSupportedDevices[0]); i++) {
if (sInfo.bridge.device_id == kSupportedDevices[i].bridge_id) {
sInfo.type = kSupportedDevices[i].type;
found = has_display_device(sInfo.display,
kSupportedDevices[i].display_id);
break;
}
}
if (found)
break;
}
if (!found)
return ENODEV;
TRACE("found intel bridge\n");
return B_OK;
}
static void
intel_uninit()
{
}
static int32
intel_std_ops(int32 op, ...)
{
switch (op) {
case B_MODULE_INIT:
return intel_init();
case B_MODULE_UNINIT:
intel_uninit();
return B_OK;
}
return B_BAD_VALUE;
}
static struct agp_gart_bus_module_info sIntelModuleInfo = {
{
"busses/agp_gart/intel/v0",
0,
intel_std_ops
},
intel_create_aperture,
intel_delete_aperture,
intel_get_aperture_info,
intel_set_aperture_size,
intel_bind_page,
intel_unbind_page,
intel_flush_tlbs
};
module_info *modules[] = {
(module_info *)&sIntelModuleInfo,
NULL
};

8
src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
View File

@ -59,7 +59,7 @@ int32 api_version = B_CUR_DRIVER_API_VERSION;
char *gDeviceNames[MAX_CARDS + 1];
intel_info *gDeviceInfo[MAX_CARDS];
pci_module_info *gPCI;
agp_module_info *gGART;
agp_gart_module_info *gGART;
lock gLock;
@ -138,7 +138,7 @@ init_driver(void)
return status;
}
get_module(B_AGP_MODULE_NAME, (module_info **)&gGART);
get_module(B_AGP_GART_MODULE_NAME, (module_info **)&gGART);
// find devices
@ -193,7 +193,7 @@ init_driver(void)
if (found == 0) {
uninit_lock(&gLock);
if (gGART != NULL)
put_module(B_AGP_MODULE_NAME);
put_module(B_AGP_GART_MODULE_NAME);
put_module(B_PCI_MODULE_NAME);
return ENODEV;
}
@ -217,7 +217,7 @@ uninit_driver(void)
}
if (gGART != NULL)
put_module(B_AGP_MODULE_NAME);
put_module(B_AGP_GART_MODULE_NAME);
put_module(B_PCI_MODULE_NAME);
}

8
src/add-ons/kernel/drivers/graphics/nvidia/driver.c
View File

@ -76,7 +76,7 @@ static int32 nv_interrupt(void *data);
static DeviceData *pd;
static isa_module_info *isa_bus = NULL;
static pci_module_info *pci_bus = NULL;
static agp_module_info *agp_bus = NULL;
static agp_gart_module_info *agp_bus = NULL;
static device_hooks graphics_device_hooks = {
open_hook,
close_hook,
@ -1257,7 +1257,7 @@ control_hook(void* dev, uint32 msg, void *buf, size_t len)
if (nca->magic == NV_PRIVATE_DATA_MAGIC) {
if (agp_bus) {
nca->agp_bus = true;
(*agp_bus->enable_agp)(&(nca->cmd));
nca->cmd = agp_bus->set_agp_mode(nca->cmd);
} else {
nca->agp_bus = false;
nca->cmd = 0;
@ -1476,7 +1476,7 @@ init_driver(void)
}
/* get a handle for the agp bus if it exists */
get_module(B_AGP_MODULE_NAME, (module_info **)&agp_bus);
get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus);
/* driver private data */
pd = (DeviceData *)calloc(1, sizeof(DeviceData));
@ -1528,6 +1528,6 @@ uninit_driver(void)
/* put the agp module away if it's there */
if (agp_bus)
put_module(B_AGP_MODULE_NAME);
put_module(B_AGP_GART_MODULE_NAME);
}

110
src/add-ons/kernel/drivers/graphics/radeon/agp.c
View File

@ -1,14 +1,11 @@
/*
Copyright (c) 2002, Thomas Kurschel
Part of Radeon kernel driver
AGP fix. Some motherboard BIOSes enable FastWrite even
though the graphics card doesn't support it. Here, we'll
fix that (hopefully it is generic enough).
updated to use AGP_BUS mananager
*/
@ -17,8 +14,10 @@
static void agp_list_info(agp_info ai);
static void agp_list_active(uint32 cmd);
// fix invalid AGP settings
void Radeon_Set_AGP( device_info *di, bool enable_agp )
//! fix invalid AGP settings
void
Radeon_Set_AGP(device_info *di, bool enable_agp)
{
uint8 agp_index = 0;
agp_info nth_agp_info;
@ -26,34 +25,29 @@ void Radeon_Set_AGP( device_info *di, bool enable_agp )
uint32 agp_cmd;
/* abort if no agp busmanager found */
if (!agp_bus)
{
if (!sAGP) {
SHOW_INFO0(1, "Busmanager not installed.\nWarning Card May hang if AGP Fastwrites are Enabled." );
return;
}
/* contact driver and get a pointer to the registers and shared data */
/* get nth AGP device info */
while((*agp_bus->get_nth_agp_info)(agp_index, &nth_agp_info) == B_NO_ERROR) {
while (sAGP->get_nth_agp_info(agp_index, &nth_agp_info) == B_OK) {
/* see if we are this one */
if ((nth_agp_info.device_id == di->pcii.device_id) &&
(nth_agp_info.vendor_id == di->pcii.vendor_id) &&
(nth_agp_info.bus == di->pcii.bus) &&
(nth_agp_info.device == di->pcii.device) &&
(nth_agp_info.function == di->pcii.function))
{
if (nth_agp_info.device_id == di->pcii.device_id
&& nth_agp_info.vendor_id == di->pcii.vendor_id
&& nth_agp_info.bus == di->pcii.bus
&& nth_agp_info.device == di->pcii.device
&& nth_agp_info.function == di->pcii.function) {
SHOW_INFO0(1, "Found AGP capable device" );
found = true;
/* remember our info */
di->agpi = nth_agp_info;
/* log capabilities */
agp_list_info(nth_agp_info);
break;
}
agp_index++;
@ -69,37 +63,33 @@ void Radeon_Set_AGP( device_info *di, bool enable_agp )
}
if (di->settings.force_pci | !enable_agp) {
SHOW_INFO0(1, "Disabling AGP mode...");
/* we want zero agp features enabled */
agp_cmd = 0;
/* write the stuff */
(*agp_bus->enable_agp)(&agp_cmd);
agp_cmd = sAGP->set_agp_mode(0);
} else {
/* activate AGP mode */
SHOW_INFO0(1, "Activating AGP mode...");
agp_cmd = 0xfffffff7;
/* set agp 3 speed bit is agp is v3 */
if (nth_agp_info.interface.agp_stat & AGP_rate_rev) agp_cmd |= AGP_rate_rev;
if ((nth_agp_info.interface.status & AGP_3_MODE) != 0)
agp_cmd |= AGP_3_MODE;
/* we want to perma disable fastwrites as they're evil, evil i say */
agp_cmd &= ~AGP_FW;
agp_cmd &= ~AGP_FAST_WRITE;
/* write the stuff */
(*agp_bus->enable_agp)(&agp_cmd);
agp_cmd = sAGP->set_agp_mode(agp_cmd);
}
/* list mode now activated,
* make sure we have the correct speed scheme for logging */
agp_list_active(nth_agp_info.interface.agp_cmd |
(nth_agp_info.interface.agp_stat & AGP_rate_rev));
agp_list_active(agp_cmd | (nth_agp_info.interface.status & AGP_3_MODE));
}
static void agp_list_info(agp_info ai)
static void
agp_list_info(agp_info ai)
{
/*
list device
@ -118,46 +108,47 @@ static void agp_list_info(agp_info ai)
list capabilities
*/
SHOW_INFO(4, "This device supports AGP specification %ld.%ld;",
((ai.interface.agp_cap_id & AGP_rev_major) >> AGP_rev_major_shift),
((ai.interface.agp_cap_id & AGP_rev_minor) >> AGP_rev_minor_shift));
((ai.interface.capability_id & AGP_REV_MAJOR) >> AGP_REV_MAJOR_SHIFT),
((ai.interface.capability_id & AGP_REV_MINOR) >> AGP_REV_MINOR_SHIFT));
/* the AGP devices determine AGP speed scheme version used on power-up/reset */
if (!(ai.interface.agp_stat & AGP_rate_rev))
{
if ((ai.interface.status & AGP_3_MODE) == 0) {
/* AGP 2.0 scheme applies */
if (ai.interface.agp_stat & AGP_2_1x)
if (ai.interface.status & AGP_2_1x)
SHOW_INFO0(4, "AGP 2.0 1x mode is available");
if (ai.interface.agp_stat & AGP_2_2x)
if (ai.interface.status & AGP_2_2x)
SHOW_INFO0(4, "AGP 2.0 2x mode is available");
if (ai.interface.agp_stat & AGP_2_4x)
if (ai.interface.status & AGP_2_4x)
SHOW_INFO0(41, "AGP 2.0 4x mode is available");
}
else
{
} else {
/* AGP 3.0 scheme applies */
if (ai.interface.agp_stat & AGP_3_4x)
if (ai.interface.status & AGP_3_4x)
SHOW_INFO0(4, "AGP 3.0 4x mode is available");
if (ai.interface.agp_stat & AGP_3_8x)
if (ai.interface.status & AGP_3_8x)
SHOW_INFO0(4, "AGP 3.0 8x mode is available");
}
if (ai.interface.agp_stat & AGP_FW) SHOW_INFO0(4, "Fastwrite transfers are supported");
if (ai.interface.agp_stat & AGP_SBA) SHOW_INFO0(4, "Sideband adressing is supported");
if (ai.interface.status & AGP_FAST_WRITE)
SHOW_INFO0(4, "Fast write transfers are supported");
if (ai.interface.status & AGP_SBA)
SHOW_INFO0(4, "Sideband adressing is supported");
SHOW_INFO(1, "%ld queued AGP requests can be handled.",
((ai.interface.agp_stat & AGP_RQ) >> AGP_RQ_shift) + 1);
((ai.interface.status & AGP_REQUEST) >> AGP_REQUEST_SHIFT) + 1);
/*
list current settings,
make sure we have the correct speed scheme for logging
*/
agp_list_active(ai.interface.agp_cmd | (ai.interface.agp_stat & AGP_rate_rev));
agp_list_active(ai.interface.command | (ai.interface.status & AGP_3_MODE));
}
static void agp_list_active(uint32 cmd)
static void
agp_list_active(uint32 cmd)
{
SHOW_INFO0(4, "listing settings now in use:");
if (!(cmd & AGP_rate_rev)) {
if ((cmd & AGP_3_MODE) == 0) {
/* AGP 2.0 scheme applies */
if (cmd & AGP_2_1x)
SHOW_INFO0(2,"AGP 2.0 1x mode is set");
@ -173,17 +164,18 @@ static void agp_list_active(uint32 cmd)
SHOW_INFO0(2,"AGP 3.0 8x mode is set");
}
if (cmd & AGP_FW) {
SHOW_INFO0(2, "Fastwrite transfers are enabled");
if (cmd & AGP_FAST_WRITE) {
SHOW_INFO0(2, "Fast write transfers are enabled");
} else {
SHOW_INFO0(2, "Fastwrite transfers are disabled");
SHOW_INFO0(2, "Fast write transfers are disabled");
}
if (cmd & AGP_SBA) SHOW_INFO0(4, "Sideband adressing is enabled");
if (cmd & AGP_SBA)
SHOW_INFO0(4, "Sideband adressing is enabled");
SHOW_INFO(4, "Max. AGP queued request depth is set to %ld",
(((cmd & AGP_RQ) >> AGP_RQ_shift) + 1));
if (cmd & AGP_enable)
(((cmd & AGP_REQUEST) >> AGP_REQUEST_SHIFT) + 1));
if (cmd & AGP_ENABLE)
SHOW_INFO0(2, "The AGP interface is enabled.");
else
SHOW_INFO0(2, "The AGP interface is disabled.");

146
src/add-ons/kernel/drivers/graphics/radeon/driver.c
View File

@ -1,9 +1,7 @@
/*
Copyright (c) 2002, Thomas Kurschel
Part of Radeon kernel driver
DevFS interface
*/
@ -24,12 +22,12 @@
int32 api_version = 2;
static status_t open_hook( const char *name, uint32 flags, void **cookie );
static status_t close_hook( void *dev );
static status_t free_hook( void *dev );
static status_t read_hook( void *dev, off_t pos, void *buf, size_t *len );
static status_t write_hook( void *dev, off_t pos, const void *buf, size_t *len );
static status_t control_hook( void *dev, uint32 msg, void *buf, size_t len );
static status_t open_hook(const char *name, uint32 flags, void **cookie);
static status_t close_hook(void *dev);
static status_t free_hook(void *dev);
static status_t read_hook(void *dev, off_t pos, void *buf, size_t *len);
static status_t write_hook(void *dev, off_t pos, const void *buf, size_t *len);
static status_t control_hook(void *dev, uint32 msg, void *buf, size_t len);
static device_hooks graphics_device_hooks = {
@ -61,10 +59,10 @@ radeon_settings def_settings = { // see comments in radeon.settings
radeon_settings current_settings;
static void GetDriverSettings(void)
static void
GetDriverSettings(void)
{
void *settings_handle = NULL;
void *settings_handle = NULL;
SHOW_FLOW0( 1, "" );
@ -129,118 +127,125 @@ static void GetDriverSettings(void)
}
}
// public function: check whether there is *any* supported hardware
status_t init_hardware( void )
// #pragma mark - driver API
status_t
init_hardware(void)
{
SHOW_INFO0( 0, RADEON_DRIVER_VERSION );
if( Radeon_CardDetect() == B_OK )
SHOW_INFO0(0, RADEON_DRIVER_VERSION);
if (Radeon_CardDetect() == B_OK)
return B_OK;
else
return B_ERROR;
return B_ERROR;
}
// public function: init driver
status_t init_driver( void )
status_t
init_driver(void)
{
SHOW_FLOW0( 3, "" );
if( get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK )
SHOW_FLOW0(3, "");
if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK)
return B_ERROR;
/* get a handle for the agp bus if it exists */
get_module(B_AGP_MODULE_NAME, (module_info **)&agp_bus);
get_module(B_AGP_GART_MODULE_NAME, (module_info **)&sAGP);
/* driver private data */
devices = (radeon_devices *)calloc( 1, sizeof( radeon_devices ));
if( devices == NULL ) {
devices = (radeon_devices *)calloc(1, sizeof(radeon_devices));
if (devices == NULL) {
put_module(B_PCI_MODULE_NAME);
if (agp_bus != NULL)
put_module(B_AGP_MODULE_NAME);
if (sAGP != NULL)
put_module(B_AGP_GART_MODULE_NAME);
return B_ERROR;
}
(void)INIT_BEN( devices->kernel, "Radeon Kernel" );
(void)INIT_BEN(devices->kernel, "Radeon Kernel");
GetDriverSettings();
Radeon_ProbeDevices();
return B_OK;
}
// public function: uninit driver
void uninit_driver( void )
void
uninit_driver(void)
{
SHOW_FLOW0( 3, "" );
DELETE_BEN( devices->kernel );
free( devices );
SHOW_FLOW0(3, "");
DELETE_BEN(devices->kernel);
free(devices);
devices = NULL;
put_module( B_PCI_MODULE_NAME );
/* put the agp module away if it's there */
if (agp_bus)
put_module(B_AGP_MODULE_NAME);
put_module(B_PCI_MODULE_NAME);
if (sAGP)
put_module(B_AGP_GART_MODULE_NAME);
}
// public function: return list of device names
const char **publish_devices( void )
const char **
publish_devices(void)
{
return (const char **)devices->device_names;
}
// public function: find hooks for specific device given its name
device_hooks *find_device( const char *name )
device_hooks *
find_device(const char *name)
{
uint32 index;
// probably, we could always return standard hooks
for( index = 0; devices->device_names[index]; ++index ) {
if( strcmp( name, devices->device_names[index] ) == 0 )
for (index = 0; devices->device_names[index]; ++index) {
if (strcmp(name, devices->device_names[index]) == 0)
return &graphics_device_hooks;
}
return NULL;
}
// public function: open device
static status_t open_hook( const char *name, uint32 flags, void **cookie )
// #pragma mark - device API
static status_t
open_hook(const char *name, uint32 flags, void **cookie)
{
int32 index = 0;
device_info *di;
status_t result = B_OK;
status_t result = B_OK;
SHOW_FLOW( 3, "name=%s, flags=%ld, cookie=0x%08lx", name, flags, (uint32)cookie );
// find device info
while( devices->device_names[index] &&
strcmp(name, devices->device_names[index] ) != 0 )
while (devices->device_names[index]
&& strcmp(name, devices->device_names[index]) != 0) {
index++;
}
di = &(devices->di[index/2]);
di = &(devices->di[index / 2]);
ACQUIRE_BEN( devices->kernel );
ACQUIRE_BEN(devices->kernel);
if( !di->is_open )
result = Radeon_FirstOpen( di );
if (!di->is_open)
result = Radeon_FirstOpen(di);
if( result == B_OK ) {
if (result == B_OK) {
di->is_open++;
*cookie = di;
}
RELEASE_BEN( devices->kernel );
SHOW_FLOW( 3, "returning 0x%08lx", result );
RELEASE_BEN(devices->kernel);
SHOW_FLOW(3, "returning 0x%08lx", result);
return result;
}
// public function: read from device (denied)
static status_t read_hook( void *dev, off_t pos, void *buf, size_t *len )
static status_t
read_hook(void *dev, off_t pos, void *buf, size_t *len)
{
*len = 0;
return B_NOT_ALLOWED;
@ -248,22 +253,23 @@ static status_t read_hook( void *dev, off_t pos, void *buf, size_t *len )
// public function: write to device (denied)
static status_t write_hook( void *dev, off_t pos, const void *buf, size_t *len )
static status_t
write_hook(void *dev, off_t pos, const void *buf, size_t *len)
{
*len = 0;
return B_NOT_ALLOWED;
}
// public function: close device (ignored, wait for free_hook instead)
static status_t close_hook( void *dev )
static status_t
close_hook(void *dev)
{
return B_NO_ERROR;
}
// public function: free device
static status_t free_hook( void *dev )
static status_t
free_hook(void *dev)
{
device_info *di = (device_info *)dev;
@ -289,8 +295,8 @@ static status_t free_hook( void *dev )
}
// public function: ioctl
static status_t control_hook( void *dev, uint32 msg, void *buf, size_t len )
static status_t
control_hook(void *dev, uint32 msg, void *buf, size_t len)
{
device_info *di = (device_info *)dev;
status_t result = B_DEV_INVALID_IOCTL;

4
src/add-ons/kernel/drivers/graphics/radeon/global_data.c
View File

@ -1,9 +1,7 @@
/*
Copyright (c) 2002, Thomas Kurschel
Part of Radeon kernel driver
Global variables
*/
@ -16,4 +14,4 @@ int debug_level_error = 4;
radeon_devices *devices;
pci_module_info *pci_bus;
agp_module_info *agp_bus;
agp_gart_module_info *sAGP;

2
src/add-ons/kernel/drivers/graphics/radeon/radeon_driver.h
View File

@ -176,7 +176,7 @@ typedef struct {
extern pci_module_info *pci_bus;
extern agp_module_info *agp_bus;
extern agp_gart_module_info *sAGP;
extern radeon_devices *devices;

11
src/add-ons/kernel/drivers/graphics/via/driver.c
View File

@ -81,7 +81,7 @@ static int32 eng_interrupt(void *data);
static DeviceData *pd;
static isa_module_info *isa_bus = NULL;
static pci_module_info *pci_bus = NULL;
static agp_module_info *agp_bus = NULL;
static agp_gart_module_info *agp_bus = NULL;
static device_hooks graphics_device_hooks = {
open_hook,
close_hook,
@ -102,6 +102,7 @@ static uint16 via_device_list[] = {
0x3108, /* K8M800 Unichrome Pro (unknown chiptype) */
0x3122, /* CLE266 Unichrome Pro (CLE3122) */
0x3205, /* KM400 Unichrome (VT3205) */
// 0x3344, /* P4M800 Pro (VT3344) */
0x7205, /* KM400 Unichrome (VT7205) */
0
};
@ -279,13 +280,13 @@ init_driver(void) {
}
/* get a handle for the agp bus if it exists */
get_module(B_AGP_MODULE_NAME, (module_info **)&agp_bus);
get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus);
/* driver private data */
pd = (DeviceData *)calloc(1, sizeof(DeviceData));
if (!pd) {
if (agp_bus)
put_module(B_AGP_MODULE_NAME);
put_module(B_AGP_GART_MODULE_NAME);
put_module(B_ISA_MODULE_NAME);
put_module(B_PCI_MODULE_NAME);
return B_ERROR;
@ -328,7 +329,7 @@ void uninit_driver(void) {
/* put the agp module away if it's there */
if (agp_bus)
put_module(B_AGP_MODULE_NAME);
put_module(B_AGP_GART_MODULE_NAME);
}
static status_t map_device(device_info *di)
@ -900,7 +901,7 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) {
if (nca->magic == VIA_PRIVATE_DATA_MAGIC) {
if (agp_bus) {
nca->agp_bus = true;
(*agp_bus->enable_agp)(&(nca->cmd));
nca->cmd = agp_bus->set_agp_mode(nca->cmd);
} else {
nca->agp_bus = false;
nca->cmd = 0;