radeon_hd: handle 64-bit PCI BARs
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7a5f5dc504
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39dae8ee4e
@ -154,10 +154,10 @@ radeon_get_rom_size(uint8* rom, size_t romSize)
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static status_t
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mapAtomBIOS(radeon_info &info, uint32 romBase, uint32 romSize,
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mapAtomBIOS(radeon_info &info, phys_addr_t romBase, uint32 romSize,
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bool findROMlength = false)
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{
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TRACE("%s: seeking AtomBIOS @ 0x%" B_PRIX32 " [size: 0x%" B_PRIX32 "]\n",
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TRACE("%s: seeking AtomBIOS @ 0x%" B_PRIXPHYSADDR " [size: 0x%" B_PRIX32 "]\n",
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__func__, romBase, romSize);
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uint8* rom;
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@ -168,7 +168,7 @@ mapAtomBIOS(radeon_info &info, uint32 romBase, uint32 romSize,
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(void**)&rom);
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if (testArea < 0) {
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ERROR("%s: couldn't map potential rom @ 0x%" B_PRIX32
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ERROR("%s: couldn't map potential rom @ 0x%" B_PRIXPHYSADDR
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"\n", __func__, romBase);
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return B_NO_MEMORY;
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}
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@ -176,7 +176,7 @@ mapAtomBIOS(radeon_info &info, uint32 romBase, uint32 romSize,
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// check for valid BIOS signature
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if (rom[0] != 0x55 || rom[1] != 0xAA) {
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uint16 id = rom[0] + (rom[1] << 8);
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TRACE("%s: BIOS signature incorrect @ 0x%" B_PRIX32 " (%X)\n",
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TRACE("%s: BIOS signature incorrect @ 0x%" B_PRIXPHYSADDR " (%X)\n",
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__func__, romBase, id);
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delete_area(testArea);
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return B_ERROR;
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@ -190,7 +190,7 @@ mapAtomBIOS(radeon_info &info, uint32 romBase, uint32 romSize,
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if (romValid == false) {
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// FAIL : a PCI VGA bios but not AtomBIOS
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uint16 id = rom[0] + (rom[1] << 8);
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TRACE("%s: not AtomBIOS rom at 0x%" B_PRIX32 "(%X)\n",
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TRACE("%s: not AtomBIOS rom at 0x%" B_PRIXPHYSADDR "(%X)\n",
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__func__, romBase, id);
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delete_area(testArea);
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return B_ERROR;
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@ -243,7 +243,7 @@ radeon_hd_getbios(radeon_info &info)
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{
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TRACE("card(%" B_PRId32 "): %s: called\n", info.id, __func__);
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uint32 romBase = 0;
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phys_addr_t romBase = 0;
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uint32 romSize = 0;
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uint32 romMethod = 0;
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@ -261,6 +261,10 @@ radeon_hd_getbios(radeon_info &info)
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// On post, the bios puts a copy of the IGP
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// AtomBIOS at the start of the video ram
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romBase = info.pci->u.h0.base_registers[PCI_BAR_FB];
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if ((info.pci->u.h0.base_register_flags[PCI_BAR_FB] & PCI_address_type)
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== PCI_address_type_64) {
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romBase |= (uint64)info.pci->u.h0.base_registers[PCI_BAR_FB + 1] << 32;
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}
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romSize = 256 * 1024;
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if (romBase == 0 || romSize == 0) {
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@ -299,11 +303,11 @@ radeon_hd_getbios(radeon_info &info)
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if (mapResult == B_OK) {
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ERROR("%s: AtomBIOS found using active method %" B_PRIu32
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" at 0x%" B_PRIX32 "\n", __func__, romMethod, romBase);
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" at 0x%" B_PRIXPHYSADDR "\n", __func__, romMethod, romBase);
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break;
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} else {
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ERROR("%s: AtomBIOS not found using active method %" B_PRIu32
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" at 0x%" B_PRIX32 "\n", __func__, romMethod, romBase);
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" at 0x%" B_PRIXPHYSADDR "\n", __func__, romMethod, romBase);
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}
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}
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@ -680,13 +684,18 @@ radeon_hd_init(radeon_info &info)
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sharedCreator.Detach();
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// *** Map Memory mapped IO
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AreaKeeper mmioMapper;
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const uint32 pciBarMmio = radeon_hd_pci_bar_mmio(info.chipsetID);
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info.registers_area = mmioMapper.Map("radeon hd mmio",
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info.pci->u.h0.base_registers[pciBarMmio],
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info.pci->u.h0.base_register_sizes[pciBarMmio],
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B_ANY_KERNEL_ADDRESS,
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B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_CLONEABLE_AREA,
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phys_addr_t addr = info.pci->u.h0.base_registers[pciBarMmio];
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uint64 mmioSize = info.pci->u.h0.base_register_sizes[pciBarMmio];
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if (pciBarMmio < 5
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&& (info.pci->u.h0.base_register_flags[pciBarMmio] & PCI_address_type) == PCI_address_type_64) {
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addr |= (uint64)info.pci->u.h0.base_registers[pciBarMmio + 1] << 32;
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mmioSize |= (uint64)info.pci->u.h0.base_register_sizes[pciBarMmio + 1] << 32;
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}
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AreaKeeper mmioMapper;
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info.registers_area = mmioMapper.Map("radeon hd mmio", addr, mmioSize,
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B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_CLONEABLE_AREA,
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(void**)&info.registers);
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if (mmioMapper.InitCheck() < B_OK) {
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ERROR("%s: card (%" B_PRId32 "): couldn't map memory I/O!\n",
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