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Added VIA Rhine driver from FreeBSD 6.2 unchanged. It does not work yet, though, because of problems

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with the MII bus support in the compatibility layer.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22811 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler 2007-11-03 12:07:26 +00:00
parent 6b26fa1e80
commit 38d3e0e20c
12 changed files with 3555 additions and 0 deletions
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2
src/add-ons/kernel/drivers/network/via-rhine/Jamfile
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@ -43,3 +43,5 @@ HaikuInstallRelSymLink install-networking : /boot/home/config/add-ons/kernel/dri
installed-symlink
;
SubInclude HAIKU_TOP src add-ons kernel drivers network via-rhine dev ;
SubInclude HAIKU_TOP src add-ons kernel drivers network via-rhine pci ;

3
src/add-ons/kernel/drivers/network/via-rhine/dev/Jamfile Normal file
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@ -0,0 +1,3 @@
SubDir HAIKU_TOP src add-ons kernel drivers network via-rhine dev ;
SubInclude HAIKU_TOP src add-ons kernel drivers network via-rhine dev mii ;

16
src/add-ons/kernel/drivers/network/via-rhine/dev/mii/Jamfile Normal file
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@ -0,0 +1,16 @@
SubDir HAIKU_TOP src add-ons kernel drivers network via-rhine dev mii ;
UsePrivateHeaders kernel net ;
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
KernelStaticLibrary via_rhine_mii.a
:
ciphy.c
ukphy.c
ukphy_subr.c
;

435
src/add-ons/kernel/drivers/network/via-rhine/dev/mii/ciphy.c Normal file
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@ -0,0 +1,435 @@
/*-
* Copyright (c) 2004
* Bill Paul <wpaul@windriver.com>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp $
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp $");
/*
* Driver for the Cicada CS8201 10/100/1000 copper PHY.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/socket.h>
#include <sys/bus.h>
#include <machine/clock.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include "miidevs.h"
#include <dev/mii/ciphyreg.h>
#include "miibus_if.h"
#include <machine/bus.h>
/*
#include <dev/vge/if_vgereg.h>
*/
static int ciphy_probe(device_t);
static int ciphy_attach(device_t);
static device_method_t ciphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, ciphy_probe),
DEVMETHOD(device_attach, ciphy_attach),
DEVMETHOD(device_detach, mii_phy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t ciphy_devclass;
static driver_t ciphy_driver = {
"ciphy",
ciphy_methods,
sizeof(struct mii_softc)
};
DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
static int ciphy_service(struct mii_softc *, struct mii_data *, int);
static void ciphy_status(struct mii_softc *);
static void ciphy_reset(struct mii_softc *);
static void ciphy_fixup(struct mii_softc *);
static int
ciphy_probe(dev)
device_t dev;
{
struct mii_attach_args *ma;
ma = device_get_ivars(dev);
device_printf(dev, "OUI: %x\n", MII_OUI(ma->mii_id1, ma->mii_id2));
device_printf(dev, "MODEL: %x\n", MII_MODEL(ma->mii_id2));
if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201) {
device_set_desc(dev, MII_STR_CICADA_CS8201);
return(0);
}
if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201A) {
device_set_desc(dev, MII_STR_CICADA_CS8201A);
return(0);
}
if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201B) {
device_set_desc(dev, MII_STR_CICADA_CS8201B);
return(0);
}
return(ENXIO);
}
static int
ciphy_attach(dev)
device_t dev;
{
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = device_get_softc(sc->mii_dev);
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = ciphy_service;
sc->mii_pdata = mii;
sc->mii_flags |= MIIF_NOISOLATE;
mii->mii_instance++;
ciphy_reset(sc);
sc->mii_capabilities =
PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
if (sc->mii_capabilities & BMSR_EXTSTAT)
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
device_printf(dev, " ");
mii_phy_add_media(sc);
printf("\n");
MIIBUS_MEDIAINIT(sc->mii_dev);
return(0);
}
static int
ciphy_service(sc, mii, cmd)
struct mii_softc *sc;
struct mii_data *mii;
int cmd;
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int reg, speed, gig;
switch (cmd) {
case MII_POLLSTAT:
/*
* If we're not polling our PHY instance, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
break;
case MII_MEDIACHG:
/*
* If the media indicates a different PHY instance,
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
reg = PHY_READ(sc, MII_BMCR);
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
return (0);
}
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
ciphy_fixup(sc); /* XXX hardware bug work-around */
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
#ifdef foo
/*
* If we're already in auto mode, just return.
*/
if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
return (0);
#endif
(void) mii_phy_auto(sc);
break;
case IFM_1000_T:
speed = CIPHY_S1000;
goto setit;
case IFM_100_TX:
speed = CIPHY_S100;
goto setit;
case IFM_10_T:
speed = CIPHY_S10;
setit:
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
speed |= CIPHY_BMCR_FDX;
gig = CIPHY_1000CTL_AFD;
} else {
gig = CIPHY_1000CTL_AHD;
}
PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
break;
PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
PHY_WRITE(sc, CIPHY_MII_BMCR,
speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
/*
* When setting the link manually, one side must
* be the master and the other the slave. However
* ifmedia doesn't give us a good way to specify
* this, so we fake it by using one of the LINK
* flags. If LINK0 is set, we program the PHY to
* be a master, otherwise it's a slave.
*/
if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
PHY_WRITE(sc, CIPHY_MII_1000CTL,
gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
} else {
PHY_WRITE(sc, CIPHY_MII_1000CTL,
gig|CIPHY_1000CTL_MSE);
}
break;
case IFM_NONE:
PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
break;
case IFM_100_T4:
default:
return (EINVAL);
}
break;
case MII_TICK:
/*
* If we're not currently selected, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
/*
* Is the interface even up?
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return (0);
/*
* Only used for autonegotiation.
*/
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
break;
/*
* Check to see if we have link. If we do, we don't
* need to restart the autonegotiation process. Read
* the BMSR twice in case it's latched.
*/
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
if (reg & BMSR_LINK)
break;
/*
* Only retry autonegotiation every 5 seconds.
*/
if (++sc->mii_ticks <= 5/*10*/)
break;
sc->mii_ticks = 0;
mii_phy_auto(sc);
return (0);
}
/* Update the media status. */
ciphy_status(sc);
/*
* Callback if something changed. Note that we need to poke
* apply fixups for certain PHY revs.
*/
if (sc->mii_media_active != mii->mii_media_active ||
sc->mii_media_status != mii->mii_media_status ||
cmd == MII_MEDIACHG) {
ciphy_fixup(sc);
}
mii_phy_update(sc, cmd);
return (0);
}
static void
ciphy_status(sc)
struct mii_softc *sc;
{
struct mii_data *mii = sc->mii_pdata;
int bmsr, bmcr;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
if (bmsr & BMSR_LINK)
mii->mii_media_status |= IFM_ACTIVE;
bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
if (bmcr & CIPHY_BMCR_LOOP)
mii->mii_media_active |= IFM_LOOP;
if (bmcr & CIPHY_BMCR_AUTOEN) {
if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
/* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
return;
}
}
bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
switch (bmsr & CIPHY_AUXCSR_SPEED) {
case CIPHY_SPEED10:
mii->mii_media_active |= IFM_10_T;
break;
case CIPHY_SPEED100:
mii->mii_media_active |= IFM_100_TX;
break;
case CIPHY_SPEED1000:
mii->mii_media_active |= IFM_1000_T;
break;
default:
device_printf(sc->mii_dev, "unknown PHY speed %x\n",
bmsr & CIPHY_AUXCSR_SPEED);
break;
}
if (bmsr & CIPHY_AUXCSR_FDX)
mii->mii_media_active |= IFM_FDX;
return;
}
static void
ciphy_reset(struct mii_softc *sc)
{
mii_phy_reset(sc);
DELAY(1000);
return;
}
#define PHY_SETBIT(x, y, z) \
PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
#define PHY_CLRBIT(x, y, z) \
PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
static void
ciphy_fixup(struct mii_softc *sc)
{
uint16_t model;
uint16_t status, speed;
model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
status = PHY_READ(sc, CIPHY_MII_AUXCSR);
speed = status & CIPHY_AUXCSR_SPEED;
switch (model) {
case MII_MODEL_CICADA_CS8201:
/* Turn off "aux mode" (whatever that means) */
PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
/*
* Work around speed polling bug in VT3119/VT3216
* when using MII in full duplex mode.
*/
if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
(status & CIPHY_AUXCSR_FDX)) {
PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
} else {
PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
}
/* Enable link/activity LED blink. */
PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
break;
case MII_MODEL_CICADA_CS8201A:
case MII_MODEL_CICADA_CS8201B:
/*
* Work around speed polling bug in VT3119/VT3216
* when using MII in full duplex mode.
*/
if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
(status & CIPHY_AUXCSR_FDX)) {
PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
} else {
PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
}
break;
default:
device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
model);
break;
}
return;
}

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src/add-ons/kernel/drivers/network/via-rhine/dev/mii/ciphyreg.h Normal file
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@ -0,0 +1,351 @@
/*-
* Copyright (c) 2004
* Bill Paul <wpaul@windriver.com>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/mii/ciphyreg.h,v 1.2 2005/01/06 01:42:55 imp Exp $
*/
#ifndef _DEV_MII_CIPHYREG_H_
#define _DEV_MII_CIPHYREG_H_
/*
* Register definitions for the Cicada CS8201 10/100/1000 gigE copper
* PHY, embedded within the VIA Networks VT6122 controller.
*/
/* Command register */
#define CIPHY_MII_BMCR 0x00
#define CIPHY_BMCR_RESET 0x8000
#define CIPHY_BMCR_LOOP 0x4000
#define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
#define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
#define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
#define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
#define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
#define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
#define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
#define CIPHY_S1000 CIPHY_BMCR_SPD1 /* 1000mbps */
#define CIPHY_S100 CIPHY_BMCR_SPD0 /* 100mpbs */
#define CIPHY_S10 0 /* 10mbps */
/* Status register */
#define CIPHY_MII_BMSR 0x01
#define CIPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
#define CIPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
#define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
#define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
#define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
#define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
#define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
#define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
#define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
#define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
#define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
#define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
#define CIPHY_BMSR_LINK 0x0004 /* Link status */
#define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */
#define CIPHY_BMSR_EXT 0x0001 /* Extended capability */
/* PHY ID registers */
#define CIPHY_MII_PHYIDR1 0x02
#define CIPHY_MII_PHYIDR2 0x03
/* Autoneg advertisement */
#define CIPHY_MII_ANAR 0x04
#define CIPHY_ANAR_NP 0x8000 /* Next page */
#define CIPHY_ANAR_RF 0x2000 /* Remote fault */
#define CIPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
#define CIPHY_ANAR_PC 0x0400 /* Pause capable */
#define CIPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */
#define CIPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
#define CIPHY_ANAR_TX 0x0080 /* local device supports 100bTx */
#define CIPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */
#define CIPHY_ANAR_10 0x0020 /* local device supports 10bT */
#define CIPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
/* Autoneg link partner ability */
#define CIPHY_MII_ANLPAR 0x05
#define CIPHY_ANLPAR_NP 0x8000 /* Next page */
#define CIPHY_ANLPAR_ACK 0x4000 /* link partner acknowledge */
#define CIPHY_ANLPAR_RF 0x2000 /* Remote fault */
#define CIPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
#define CIPHY_ANLPAR_PC 0x0400 /* Pause capable */
#define CIPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
#define CIPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
#define CIPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */
#define CIPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
#define CIPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */
#define CIPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
#define CIPHY_SEL_TYPE 0x0001 /* ethernet */
/* Antoneg expansion register */
#define CIPHY_MII_ANER 0x06
#define CIPHY_ANER_PDF 0x0010 /* Parallel detection fault */
#define CIPHY_ANER_LPNP 0x0008 /* Link partner can next page */
#define CIPHY_ANER_NP 0x0004 /* Local PHY can next page */
#define CIPHY_ANER_RX 0x0002 /* Next page received */
#define CIPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
/* Autoneg next page transmit regisyer */
#define CIPHY_MII_NEXTP 0x07
#define CIPHY_NEXTP_MOREP 0x8000 /* More pages to follow */
#define CIPHY_NEXTP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
#define CIPHY_NEXTP_ACK2 0x1000 /* MAC acknowledge */
#define CIPHY_NEXTP_TOGGLE 0x0800 /* Toggle */
#define CIPHY_NEXTP_CODE 0x07FF /* Code bits */
/* Autoneg link partner next page receive register */
#define CIPHY_MII_NEXTP_LP 0x08
#define CIPHY_NEXTPLP_MOREP 0x8000 /* More pages to follow */
#define CIPHY_NEXTPLP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
#define CIPHY_NEXTPLP_ACK2 0x1000 /* MAC acknowledge */
#define CIPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */
#define CIPHY_NEXTPLP_CODE 0x07FF /* Code bits */
/* 1000BT control register */
#define CIPHY_MII_1000CTL 0x09
#define CIPHY_1000CTL_TST 0xE000 /* test modes */
#define CIPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */
#define CIPHY_1000CTL_MSC 0x0800 /* Master/Slave select */
#define CIPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
#define CIPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
#define CIPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
#define CIPHY_TEST_TX_JITTER 0x2000
#define CIPHY_TEST_TX_JITTER_MASTER_MODE 0x4000
#define CIPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000
#define CIPHY_TEST_TX_DISTORTION 0x8000
/* 1000BT status register */
#define CIPHY_MII_1000STS 0x0A
#define CIPHY_1000STS_MSF 0x8000 /* Master/slave fault */
#define CIPHY_1000STS_MSR 0x4000 /* Master/slave result */
#define CIPHY_1000STS_LRS 0x2000 /* Local receiver status */
#define CIPHY_1000STS_RRS 0x1000 /* Remote receiver status */
#define CIPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
#define CIPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
#define CIPHY_1000STS_IEC 0x00FF /* Idle error count */
#define CIPHY_MII_EXTSTS 0x0F /* Extended status */
#define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
#define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
#define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
#define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
/* 1000BT status extension register #1 */
#define CIPHY_MII_1000STS1 0x0F
#define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */
#define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */
#define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */
#define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */
/* Vendor-specific PHY registers */
/* 100baseTX status extention register */
#define CIPHY_MII_100STS 0x10
#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */
#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */
#define CIPHY_100STS_DISC 0x2000 /* disconnect state */
#define CIPHY_100STS_LINK 0x1000 /* current link state */
#define CIPHY_100STS_RXERR 0x0800 /* receive error detected */
#define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */
#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */
#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */
/* 1000BT status extention register #2 */
#define CIPHY_MII_1000STS2 0x11
#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */
#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */
#define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */
#define CIPHY_1000STS2_LINK 0x1000 /* current link state */
#define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */
#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */
#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */
#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */
#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */
#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */
/* Bypass control register */
#define CIPHY_MII_BYPASS 0x12
#define CIPHY_BYPASS_TX 0x8000 /* transmit disable */
#define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */
#define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */
#define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */
#define CIPHY_BYPASS_PCSRX 0x0800 /* bypass PCS receive */
#define CIPHY_BYPASS_PCSTX 0x0400 /* bypass PCS transmit */
#define CIPHY_BYPASS_LFI 0x0200 /* bypass LFI timer */
#define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */
#define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */
#define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */
#define CIPHY_BYPASS_PAIRSWAP 0x0020 /* disable automatic pair swap */
#define CIPHY_BYPASS_POLARITY 0x0010 /* disable polarity correction */
#define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */
#define CIPHY_BYPASS_PULSE 0x0004 /* disable pulse shaping filter */
#define CIPHY_BYPASS_1000BNP 0x0002 /* disable 1000BT next page exchange */
/* RX error count register */
#define CIPHY_MII_RXERR 0x13
/* False carrier sense count register */
#define CIPHY_MII_FCSERR 0x14
/* Ddisconnect error counter */
#define CIPHY_MII_DISCERR 0x15
/* 10baseT control/status register */
#define CIPHY_MII_10BTCSR 0x16
#define CIPHY_10BTCSR_DLIT 0x8000 /* Disable data link integrity test */
#define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */
#define CIPHY_10BTCSR_ECHO 0x2000 /* Disable echo mode */
#define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */
#define CIPHY_10BTCSR_SQUENCH 0x0C00 /* Squelch control */
#define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */
#define CIPHY_10BTCSR_DISC 0x0080 /* Disconnect status */
#define CIPHY_10BTCSR_LINK 0x0040 /* current link state */
#define CIPHY_10BTCSR_ITRIM 0x0038 /* current reference trim */
#define CIPHY_10BTCSR_CSR 0x0006 /* CSR behavior control */
#define CIPHY_SQUELCH_300MV 0x0000
#define CIPHY_SQUELCH_197MV 0x0400
#define CIPHY_SQUELCH_450MV 0x0800
#define CIPHY_SQUELCH_RSVD 0x0C00
#define CIPHY_ITRIM_PLUS2 0x0000
#define CIPHY_ITRIM_PLUS4 0x0008
#define CIPHY_ITRIM_PLUS6 0x0010
#define CIPHY_ITRIM_PLUS6_ 0x0018
#define CIPHY_ITRIM_MINUS4 0x0020
#define CIPHY_ITRIM_MINUS4_ 0x0028
#define CIPHY_ITRIM_MINUS2 0x0030
#define CIPHY_ITRIM_ZERO 0x0038
/* Extended PHY control register #1 */
#define CIPHY_MII_ECTL1 0x17
#define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */
/* Extended PHY control register #2 */
#define CIPHY_MII_ECTL2 0x18
#define CIPHY_ECTL2_ERATE 0xE000 /* 10/1000 edge rate control */
#define CIPHY_ECTL2_VTRIM 0x1C00 /* voltage reference trim */
#define CIPHY_ECTL2_CABLELEN 0x000E /* Cable quality/length */
#define CIPHY_ECTL2_ANALOGLOOP 0x0001 /* 1000BT analog loopback */
#define CIPHY_CABLELEN_0TO10M 0x0000
#define CIPHY_CABLELEN_10TO20M 0x0002
#define CIPHY_CABLELEN_20TO40M 0x0004
#define CIPHY_CABLELEN_40TO80M 0x0006
#define CIPHY_CABLELEN_80TO100M 0x0008
#define CIPHY_CABLELEN_100TO140M 0x000A
#define CIPHY_CABLELEN_140TO180M 0x000C
#define CIPHY_CABLELEN_OVER180M 0x000E
/* Interrupt mask register */
#define CIPHY_MII_IMR 0x19
#define CIPHY_IMR_PINENABLE 0x8000 /* Interrupt pin enable */
#define CIPHY_IMR_SPEED 0x4000 /* speed changed event */
#define CIPHY_IMR_LINK 0x2000 /* link change/ActiPHY event */
#define CIPHY_IMR_DPX 0x1000 /* duplex change event */
#define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */
#define CIPHY_IMR_ANEGDONE 0x0400 /* autoneg done event */
#define CIPHY_IMR_NPRX 0x0200 /* page received event */
#define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */
#define CIPHY_IMR_LOCKERR 0x0080 /* descrambler lock lost event */
#define CIPHY_IMR_XOVER 0x0040 /* MDI crossover change event */
#define CIPHY_IMR_POLARITY 0x0020 /* polarity change event */
#define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */
#define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */
#define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */
#define CIPHY_IMR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
#define CIPHY_IMR_RXERR 0x0001 /* RX error event */
/* Interrupt status register */
#define CIPHY_MII_ISR 0x1A
#define CIPHY_ISR_IPENDING 0x8000 /* Interrupt is pending */
#define CIPHY_ISR_SPEED 0x4000 /* speed changed event */
#define CIPHY_ISR_LINK 0x2000 /* link change/ActiPHY event */
#define CIPHY_ISR_DPX 0x1000 /* duplex change event */
#define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */
#define CIPHY_ISR_ANEGDONE 0x0400 /* autoneg done event */
#define CIPHY_ISR_NPRX 0x0200 /* page received event */
#define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */
#define CIPHY_ISR_LOCKERR 0x0080 /* descrambler lock lost event */
#define CIPHY_ISR_XOVER 0x0040 /* MDI crossover change event */
#define CIPHY_ISR_POLARITY 0x0020 /* polarity change event */
#define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */
#define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */
#define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */
#define CIPHY_ISR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
#define CIPHY_ISR_RXERR 0x0001 /* RX error event */
/* LED control register */
#define CIPHY_MII_LED 0x1B
#define CIPHY_LED_LINK10FORCE 0x8000 /* Force on link10 LED */
#define CIPHY_LED_LINK10DIS 0x4000 /* Disable link10 LED */
#define CIPHY_LED_LINK100FORCE 0x2000 /* Force on link10 LED */
#define CIPHY_LED_LINK100DIS 0x1000 /* Disable link100 LED */
#define CIPHY_LED_LINK1000FORCE 0x0800 /* Force on link1000 LED */
#define CIPHY_LED_LINK1000DIS 0x0400 /* Disable link1000 LED */
#define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */
#define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */
#define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */
#define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */
#define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */
#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */
#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */
/* Auxilliary control and status register */
#define CIPHY_MII_AUXCSR 0x1C
#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */
#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */
#define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */
#define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */
#define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */
#define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */
#define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */
#define CIPHY_AUXCSR_DPOLARITY 0x0100 /* polarity inversion pair D */
#define CIPHY_AUXCSR_FDX 0x0020 /* duplex 1=full, 0=half */
#define CIPHY_AUXCSR_SPEED 0x0018 /* speed */
#define CIPHY_AUXCSR_MDPPS 0x0004 /* No idea, not documented */
#define CIPHY_AUXCSR_STICKYREST 0x0002 /* reset clears sticky bits */
#define CIPHY_SPEED10 0x0000
#define CIPHY_SPEED100 0x0008
#define CIPHY_SPEED1000 0x0010
/* Delay skew status register */
#define CIPHY_MII_DSKEW 0x1D
#define CIPHY_DSKEW_PAIRA 0x7000 /* Pair A skew in symbol times */
#define CIPHY_DSKEW_PAIRB 0x0700 /* Pair B skew in symbol times */
#define CIPHY_DSKEW_PAIRC 0x0070 /* Pair C skew in symbol times */
#define CIPHY_DSKEW_PAIRD 0x0007 /* Pair D skew in symbol times */
#endif /* _DEV_CIPHY_MIIREG_H_ */

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src/add-ons/kernel/drivers/network/via-rhine/dev/mii/miidevs.h Normal file
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/*
* Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _FBSD_MII_DEVS_H
#define _FBSD_MII_DEVS_H
#define MII_OUI_CICADA 0x0003f1
#define MII_MODEL_CICADA_CS8201 0x0001
#define MII_MODEL_CICADA_CS8201A 0x0020
#define MII_MODEL_CICADA_CS8201B 0x0021
#define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY"
#define MII_STR_CICADA_CS8201A MII_STR_CICADA_CS8201
#define MII_STR_CICADA_CS8201B MII_STR_CICADA_CS8201
#endif /* _FBSD_MII_DEVS_H */

227
src/add-ons/kernel/drivers/network/via-rhine/dev/mii/ukphy.c Normal file
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/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */
/*-
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center, and by Frank van der Linden.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Manuel Bouyer.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.17 2005/01/06 01:42:56 imp Exp $");
/*
* driver for generic unknown PHYs
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/errno.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <net/if.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include "miibus_if.h"
static int ukphy_probe(device_t);
static int ukphy_attach(device_t);
static device_method_t ukphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, ukphy_probe),
DEVMETHOD(device_attach, ukphy_attach),
DEVMETHOD(device_detach, mii_phy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t ukphy_devclass;
static driver_t ukphy_driver = {
"ukphy",
ukphy_methods,
sizeof(struct mii_softc)
};
DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0);
static int ukphy_service(struct mii_softc *, struct mii_data *, int);
static int
ukphy_probe(dev)
device_t dev;
{
/*
* We know something is here, so always match at a low priority.
*/
device_set_desc(dev, "Generic IEEE 802.3u media interface");
return (-100);
}
static int
ukphy_attach(dev)
device_t dev;
{
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = device_get_softc(sc->mii_dev);
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
if (bootverbose)
device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
MII_OUI(ma->mii_id1, ma->mii_id2),
MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2));
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = ukphy_service;
sc->mii_pdata = mii;
mii->mii_instance++;
sc->mii_flags |= MIIF_NOISOLATE;
mii_phy_reset(sc);
sc->mii_capabilities =
PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
if (sc->mii_capabilities & BMSR_EXTSTAT)
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
device_printf(dev, " ");
mii_phy_add_media(sc);
printf("\n");
MIIBUS_MEDIAINIT(sc->mii_dev);
mii_phy_setmedia(sc);
return(0);
}
static int
ukphy_service(sc, mii, cmd)
struct mii_softc *sc;
struct mii_data *mii;
int cmd;
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int reg;
switch (cmd) {
case MII_POLLSTAT:
/*
* If we're not polling our PHY instance, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
break;
case MII_MEDIACHG:
/*
* If the media indicates a different PHY instance,
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
reg = PHY_READ(sc, MII_BMCR);
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
return (0);
}
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
mii_phy_setmedia(sc);
break;
case MII_TICK:
/*
* If we're not currently selected, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
if (mii_phy_tick(sc) == EJUSTRETURN)
return (0);
break;
}
/* Update the media status. */
ukphy_status(sc);
/* Callback if something changed. */
mii_phy_update(sc, cmd);
return (0);
}

129
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/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center, and by Frank van der Linden.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.8.8.1 2006/07/19 04:40:26 yongari Exp $");
/*
* Subroutines shared by the ukphy driver and other PHY drivers.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/socket.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <net/if.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include "miibus_if.h"
/*
* Media status subroutine. If a PHY driver does media detection simply
* by decoding the NWay autonegotiation, use this routine.
*/
void
ukphy_status(struct mii_softc *phy)
{
struct mii_data *mii = phy->mii_pdata;
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int bmsr, bmcr, anlpar, gtcr, gtsr;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
if (bmsr & BMSR_LINK)
mii->mii_media_status |= IFM_ACTIVE;
bmcr = PHY_READ(phy, MII_BMCR);
if (bmcr & BMCR_ISO) {
mii->mii_media_active |= IFM_NONE;
mii->mii_media_status = 0;
return;
}
if (bmcr & BMCR_LOOP)
mii->mii_media_active |= IFM_LOOP;
if (bmcr & BMCR_AUTOEN) {
/*
* NWay autonegotiation takes the highest-order common
* bit of the ANAR and ANLPAR (i.e. best media advertised
* both by us and our link partner).
*/
if ((bmsr & BMSR_ACOMP) == 0) {
/* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
return;
}
anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
(phy->mii_extcapabilities &
(EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) {
gtcr = PHY_READ(phy, MII_100T2CR);
gtsr = PHY_READ(phy, MII_100T2SR);
} else
gtcr = gtsr = 0;
if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX))
mii->mii_media_active |= IFM_1000_T|IFM_FDX;
else if ((gtcr & GTCR_ADV_1000THDX) &&
(gtsr & GTSR_LP_1000THDX))
mii->mii_media_active |= IFM_1000_T;
else if (anlpar & ANLPAR_T4)
mii->mii_media_active |= IFM_100_T4;
else if (anlpar & ANLPAR_TX_FD)
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
else if (anlpar & ANLPAR_TX)
mii->mii_media_active |= IFM_100_TX;
else if (anlpar & ANLPAR_10_FD)
mii->mii_media_active |= IFM_10_T|IFM_FDX;
else if (anlpar & ANLPAR_10)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_NONE;
} else
mii->mii_media_active = ife->ifm_media;
}

17
src/add-ons/kernel/drivers/network/via-rhine/pci/Jamfile Normal file
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SubDir HAIKU_TOP src add-ons kernel drivers network via-rhine pci ;
SubDirCcFlags -Wall ;
UsePrivateHeaders kernel net ;
UseHeaders [ FDirName $(SUBDIR) .. ] : true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
KernelAddon via_rhine :
if_vr.c
glue.c
: libfreebsd_network.a via_rhine_mii.a
;

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src/add-ons/kernel/drivers/network/via-rhine/pci/glue.c Normal file
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/*
* Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#include <sys/bus.h>
#include "if_vrreg.h"
HAIKU_FBSD_DRIVER_GLUE(via_rhine, vr, pci);
HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_SWI_TASKQUEUE);
extern driver_t *DRIVER_MODULE_NAME(ciphy, miibus);
extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus);
driver_t *
__haiku_select_miibus_driver(device_t dev)
{
driver_t *drivers[] = {
DRIVER_MODULE_NAME(ciphy, miibus),
DRIVER_MODULE_NAME(ukphy, miibus)
};
return __haiku_probe_miibus(dev, drivers, 2);
}
int
__haiku_disable_interrupts(device_t dev)
{
struct vr_softc *sc = device_get_softc(dev);
if (CSR_READ_2(sc, VR_ISR) == 0)
return 0;
CSR_WRITE_2(sc, VR_IMR, 0x0000);
return 1;
}
void
__haiku_reenable_interrupts(device_t dev)
{
struct vr_softc *sc = device_get_softc(dev);
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
}

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src/add-ons/kernel/drivers/network/via-rhine/pci/if_vr.c Normal file
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src/add-ons/kernel/drivers/network/via-rhine/pci/if_vrreg.h Normal file
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/*-
* Copyright (c) 1997, 1998
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD: src/sys/pci/if_vrreg.h,v 1.22.2.1 2005/11/08 16:05:56 jhb Exp $
*/
/*
* Rhine register definitions.
*/
#define VR_PAR0 0x00 /* node address 0 to 4 */
#define VR_PAR1 0x04 /* node address 2 to 6 */
#define VR_RXCFG 0x06 /* receiver config register */
#define VR_TXCFG 0x07 /* transmit config register */
#define VR_COMMAND 0x08 /* command register */
#define VR_ISR 0x0C /* interrupt/status register */
#define VR_IMR 0x0E /* interrupt mask register */
#define VR_MAR0 0x10 /* multicast hash 0 */
#define VR_MAR1 0x14 /* multicast hash 1 */
#define VR_RXADDR 0x18 /* rx descriptor list start addr */
#define VR_TXADDR 0x1C /* tx descriptor list start addr */
#define VR_CURRXDESC0 0x20
#define VR_CURRXDESC1 0x24
#define VR_CURRXDESC2 0x28
#define VR_CURRXDESC3 0x2C
#define VR_NEXTRXDESC0 0x30
#define VR_NEXTRXDESC1 0x34
#define VR_NEXTRXDESC2 0x38
#define VR_NEXTRXDESC3 0x3C
#define VR_CURTXDESC0 0x40
#define VR_CURTXDESC1 0x44
#define VR_CURTXDESC2 0x48
#define VR_CURTXDESC3 0x4C
#define VR_NEXTTXDESC0 0x50
#define VR_NEXTTXDESC1 0x54
#define VR_NEXTTXDESC2 0x58
#define VR_NEXTTXDESC3 0x5C
#define VR_CURRXDMA 0x60 /* current RX DMA address */
#define VR_CURTXDMA 0x64 /* current TX DMA address */
#define VR_TALLYCNT 0x68 /* tally counter test register */
#define VR_PHYADDR 0x6C
#define VR_MIISTAT 0x6D
#define VR_BCR0 0x6E
#define VR_BCR1 0x6F
#define VR_MIICMD 0x70
#define VR_MIIADDR 0x71
#define VR_MIIDATA 0x72
#define VR_EECSR 0x74
#define VR_TEST 0x75
#define VR_GPIO 0x76
#define VR_CONFIG 0x78
#define VR_MPA_CNT 0x7C
#define VR_CRC_CNT 0x7E
#define VR_STICKHW 0x83
/* Misc Registers */
#define VR_MISC_CR1 0x81
#define VR_MISCCR1_FORSRST 0x40
/*
* RX config bits.
*/
#define VR_RXCFG_RX_ERRPKTS 0x01
#define VR_RXCFG_RX_RUNT 0x02
#define VR_RXCFG_RX_MULTI 0x04
#define VR_RXCFG_RX_BROAD 0x08
#define VR_RXCFG_RX_PROMISC 0x10
#define VR_RXCFG_RX_THRESH 0xE0
#define VR_RXTHRESH_32BYTES 0x00
#define VR_RXTHRESH_64BYTES 0x20
#define VR_RXTHRESH_128BYTES 0x40
#define VR_RXTHRESH_256BYTES 0x60
#define VR_RXTHRESH_512BYTES 0x80
#define VR_RXTHRESH_768BYTES 0xA0
#define VR_RXTHRESH_1024BYTES 0xC0
#define VR_RXTHRESH_STORENFWD 0xE0
/*
* TX config bits.
*/
#define VR_TXCFG_RSVD0 0x01
#define VR_TXCFG_LOOPBKMODE 0x06
#define VR_TXCFG_BACKOFF 0x08
#define VR_TXCFG_RSVD1 0x10
#define VR_TXCFG_TX_THRESH 0xE0
#define VR_TXTHRESH_32BYTES 0x00
#define VR_TXTHRESH_64BYTES 0x20
#define VR_TXTHRESH_128BYTES 0x40
#define VR_TXTHRESH_256BYTES 0x60
#define VR_TXTHRESH_512BYTES 0x80
#define VR_TXTHRESH_768BYTES 0xA0
#define VR_TXTHRESH_1024BYTES 0xC0
#define VR_TXTHRESH_STORENFWD 0xE0
/*
* Command register bits.
*/
#define VR_CMD_INIT 0x0001
#define VR_CMD_START 0x0002
#define VR_CMD_STOP 0x0004
#define VR_CMD_RX_ON 0x0008
#define VR_CMD_TX_ON 0x0010
#define VR_CMD_TX_GO 0x0020
#define VR_CMD_RX_GO 0x0040
#define VR_CMD_RSVD 0x0080
#define VR_CMD_RX_EARLY 0x0100
#define VR_CMD_TX_EARLY 0x0200
#define VR_CMD_FULLDUPLEX 0x0400
#define VR_CMD_TX_NOPOLL 0x0800
#define VR_CMD_RESET 0x8000
/*
* Interrupt status bits.
*/
#define VR_ISR_RX_OK 0x0001 /* packet rx ok */
#define VR_ISR_TX_OK 0x0002 /* packet tx ok */
#define VR_ISR_RX_ERR 0x0004 /* packet rx with err */
#define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
#define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
#define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */
#define VR_ISR_BUSERR 0x0040 /* PCI bus error */
#define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */
#define VR_ISR_RX_EARLY 0x0100 /* rx early */
#define VR_ISR_LINKSTAT 0x0200 /* MII status change */
#define VR_ISR_ETI 0x0200 /* Tx early (3043/3071) */
#define VR_ISR_UDFI 0x0200 /* Tx FIFO underflow (3065) */
#define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */
#define VR_ISR_RX_DROPPED 0x0800
#define VR_ISR_RX_NOBUF2 0x1000
#define VR_ISR_TX_ABRT2 0x2000
#define VR_ISR_LINKSTAT2 0x4000
#define VR_ISR_MAGICPACKET 0x8000
/*
* Interrupt mask bits.
*/
#define VR_IMR_RX_OK 0x0001 /* packet rx ok */
#define VR_IMR_TX_OK 0x0002 /* packet tx ok */
#define VR_IMR_RX_ERR 0x0004 /* packet rx with err */
#define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
#define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
#define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */
#define VR_IMR_BUSERR 0x0040 /* PCI bus error */
#define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */
#define VR_IMR_RX_EARLY 0x0100 /* rx early */
#define VR_IMR_LINKSTAT 0x0200 /* MII status change */
#define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */
#define VR_IMR_RX_DROPPED 0x0800
#define VR_IMR_RX_NOBUF2 0x1000
#define VR_IMR_TX_ABRT2 0x2000
#define VR_IMR_LINKSTAT2 0x4000
#define VR_IMR_MAGICPACKET 0x8000
#define VR_INTRS \
(VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \
VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \
VR_IMR_RX_ERR|VR_ISR_RX_DROPPED)
/*
* MII status register.
*/
#define VR_MIISTAT_SPEED 0x01
#define VR_MIISTAT_LINKFAULT 0x02
#define VR_MIISTAT_MGTREADERR 0x04
#define VR_MIISTAT_MIIERR 0x08
#define VR_MIISTAT_PHYOPT 0x10
#define VR_MIISTAT_MDC_SPEED 0x20
#define VR_MIISTAT_RSVD 0x40
#define VR_MIISTAT_GPIO1POLL 0x80
/*
* MII command register bits.
*/
#define VR_MIICMD_CLK 0x01
#define VR_MIICMD_DATAOUT 0x02
#define VR_MIICMD_DATAIN 0x04
#define VR_MIICMD_DIR 0x08
#define VR_MIICMD_DIRECTPGM 0x10
#define VR_MIICMD_WRITE_ENB 0x20
#define VR_MIICMD_READ_ENB 0x40
#define VR_MIICMD_AUTOPOLL 0x80
/*
* EEPROM control bits.
*/
#define VR_EECSR_DATAIN 0x01 /* data out */
#define VR_EECSR_DATAOUT 0x02 /* data in */
#define VR_EECSR_CLK 0x04 /* clock */
#define VR_EECSR_CS 0x08 /* chip select */
#define VR_EECSR_DPM 0x10
#define VR_EECSR_LOAD 0x20
#define VR_EECSR_EMBP 0x40
#define VR_EECSR_EEPR 0x80
#define VR_EECMD_WRITE 0x140
#define VR_EECMD_READ 0x180
#define VR_EECMD_ERASE 0x1c0
/*
* Test register bits.
*/
#define VR_TEST_TEST0 0x01
#define VR_TEST_TEST1 0x02
#define VR_TEST_TEST2 0x04
#define VR_TEST_TSTUD 0x08
#define VR_TEST_TSTOV 0x10
#define VR_TEST_BKOFF 0x20
#define VR_TEST_FCOL 0x40
#define VR_TEST_HBDES 0x80
/*
* Config register bits.
*/
#define VR_CFG_GPIO2OUTENB 0x00000001
#define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */
#define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */
#define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */
#define VR_CFG_MIIOPT 0x00000010
#define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */
#define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */
#define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */
#define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */
#define VR_CFG_MRREADWAIT 0x00000200
#define VR_CFG_MRWRITEWAIT 0x00000400
#define VR_CFG_RX_ARB 0x00000800
#define VR_CFG_TX_ARB 0x00001000
#define VR_CFG_READMULTI 0x00002000
#define VR_CFG_TX_PACE 0x00004000
#define VR_CFG_TX_QDIS 0x00008000
#define VR_CFG_ROMSEL0 0x00010000
#define VR_CFG_ROMSEL1 0x00020000
#define VR_CFG_ROMSEL2 0x00040000
#define VR_CFG_ROMTIMESEL 0x00080000
#define VR_CFG_RSVD0 0x00100000
#define VR_CFG_ROMDLY 0x00200000
#define VR_CFG_ROMOPT 0x00400000
#define VR_CFG_RSVD1 0x00800000
#define VR_CFG_BACKOFFOPT 0x01000000
#define VR_CFG_BACKOFFMOD 0x02000000
#define VR_CFG_CAPEFFECT 0x04000000
#define VR_CFG_BACKOFFRAND 0x08000000
#define VR_CFG_MAGICKPACKET 0x10000000
#define VR_CFG_PCIREADLINE 0x20000000
#define VR_CFG_DIAG 0x40000000
#define VR_CFG_GPIOEN 0x80000000
/* Sticky HW bits */
#define VR_STICKHW_DS0 0x01
#define VR_STICKHW_DS1 0x02
#define VR_STICKHW_WOL_ENB 0x04
#define VR_STICKHW_WOL_STS 0x08
#define VR_STICKHW_LEGWOL_ENB 0x80
/*
* BCR0 register bits. (At least for the VT6102 chip.)
*/
#define VR_BCR0_DMA_LENGTH 0x07
#define VR_BCR0_DMA_32BYTES 0x00
#define VR_BCR0_DMA_64BYTES 0x01
#define VR_BCR0_DMA_128BYTES 0x02
#define VR_BCR0_DMA_256BYTES 0x03
#define VR_BCR0_DMA_512BYTES 0x04
#define VR_BCR0_DMA_1024BYTES 0x05
#define VR_BCR0_DMA_STORENFWD 0x07
#define VR_BCR0_RX_THRESH 0x38
#define VR_BCR0_RXTHRESHCFG 0x00
#define VR_BCR0_RXTHRESH64BYTES 0x08
#define VR_BCR0_RXTHRESH128BYTES 0x10
#define VR_BCR0_RXTHRESH256BYTES 0x18
#define VR_BCR0_RXTHRESH512BYTES 0x20
#define VR_BCR0_RXTHRESH1024BYTES 0x28
#define VR_BCR0_RXTHRESHSTORENFWD 0x38
#define VR_BCR0_EXTLED 0x40
#define VR_BCR0_MED2 0x80
/*
* BCR1 register bits. (At least for the VT6102 chip.)
*/
#define VR_BCR1_POT0 0x01
#define VR_BCR1_POT1 0x02
#define VR_BCR1_POT2 0x04
#define VR_BCR1_TX_THRESH 0x38
#define VR_BCR1_TXTHRESHCFG 0x00
#define VR_BCR1_TXTHRESH64BYTES 0x08
#define VR_BCR1_TXTHRESH128BYTES 0x10
#define VR_BCR1_TXTHRESH256BYTES 0x18
#define VR_BCR1_TXTHRESH512BYTES 0x20
#define VR_BCR1_TXTHRESH1024BYTES 0x28
#define VR_BCR1_TXTHRESHSTORENFWD 0x38
/*
* Rhine TX/RX list structure.
*/
struct vr_desc {
u_int32_t vr_status;
u_int32_t vr_ctl;
u_int32_t vr_ptr1;
u_int32_t vr_ptr2;
};
#define vr_data vr_ptr1
#define vr_next vr_ptr2
#define VR_RXSTAT_RXERR 0x00000001
#define VR_RXSTAT_CRCERR 0x00000002
#define VR_RXSTAT_FRAMEALIGNERR 0x00000004
#define VR_RXSTAT_FIFOOFLOW 0x00000008
#define VR_RXSTAT_GIANT 0x00000010
#define VR_RXSTAT_RUNT 0x00000020
#define VR_RXSTAT_BUSERR 0x00000040
#define VR_RXSTAT_BUFFERR 0x00000080
#define VR_RXSTAT_LASTFRAG 0x00000100
#define VR_RXSTAT_FIRSTFRAG 0x00000200
#define VR_RXSTAT_RLINK 0x00000400
#define VR_RXSTAT_RX_PHYS 0x00000800
#define VR_RXSTAT_RX_BROAD 0x00001000
#define VR_RXSTAT_RX_MULTI 0x00002000
#define VR_RXSTAT_RX_OK 0x00004000
#define VR_RXSTAT_RXLEN 0x07FF0000
#define VR_RXSTAT_RXLEN_EXT 0x78000000
#define VR_RXSTAT_OWN 0x80000000
#define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16)
#define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN)
#define VR_RXCTL_BUFLEN 0x000007FF
#define VR_RXCTL_BUFLEN_EXT 0x00007800
#define VR_RXCTL_CHAIN 0x00008000
#define VR_RXCTL_RX_INTR 0x00800000
#define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR)
#define VR_TXSTAT_DEFER 0x00000001
#define VR_TXSTAT_UNDERRUN 0x00000002
#define VR_TXSTAT_COLLCNT 0x00000078
#define VR_TXSTAT_SQE 0x00000080
#define VR_TXSTAT_ABRT 0x00000100
#define VR_TXSTAT_LATECOLL 0x00000200
#define VR_TXSTAT_CARRLOST 0x00000400
#define VR_TXSTAT_UDF 0x00000800
#define VR_TXSTAT_BUSERR 0x00002000
#define VR_TXSTAT_JABTIMEO 0x00004000
#define VR_TXSTAT_ERRSUM 0x00008000
#define VR_TXSTAT_OWN 0x80000000
#define VR_TXCTL_BUFLEN 0x000007FF
#define VR_TXCTL_BUFLEN_EXT 0x00007800
#define VR_TXCTL_TLINK 0x00008000
#define VR_TXCTL_FIRSTFRAG 0x00200000
#define VR_TXCTL_LASTFRAG 0x00400000
#define VR_TXCTL_FINT 0x00800000
#define VR_MAXFRAGS 16
#define VR_RX_LIST_CNT 64
#define VR_TX_LIST_CNT 128
#define VR_MIN_FRAMELEN 60
#define VR_FRAMELEN 1536
#define VR_RXLEN 1520
#define VR_TXOWN(x) x->vr_ptr->vr_status
struct vr_list_data {
struct vr_desc vr_rx_list[VR_RX_LIST_CNT];
struct vr_desc vr_tx_list[VR_TX_LIST_CNT];
};
struct vr_chain {
struct vr_desc *vr_ptr;
struct mbuf *vr_mbuf;
struct vr_chain *vr_nextdesc;
};
struct vr_chain_onefrag {
struct vr_desc *vr_ptr;
struct mbuf *vr_mbuf;
struct vr_chain_onefrag *vr_nextdesc;
};
struct vr_chain_data {
struct vr_chain_onefrag vr_rx_chain[VR_RX_LIST_CNT];
struct vr_chain vr_tx_chain[VR_TX_LIST_CNT];
struct vr_chain_onefrag *vr_rx_head;
struct vr_chain *vr_tx_cons;
struct vr_chain *vr_tx_prod;
};
struct vr_type {
u_int16_t vr_vid;
u_int16_t vr_did;
char *vr_name;
};
struct vr_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define VR_MII_STARTDELIM 0x01
#define VR_MII_READOP 0x02
#define VR_MII_WRITEOP 0x01
#define VR_MII_TURNAROUND 0x02
#define VR_FLAG_FORCEDELAY 1
#define VR_FLAG_SCHEDDELAY 2
#define VR_FLAG_DELAYTIMEO 3
struct vr_softc {
struct ifnet *vr_ifp; /* interface info */
bus_space_handle_t vr_bhandle; /* bus space handle */
bus_space_tag_t vr_btag; /* bus space tag */
struct resource *vr_res;
struct resource *vr_irq;
void *vr_intrhand;
device_t vr_miibus;
struct vr_type *vr_info; /* Rhine adapter info */
u_int8_t vr_type;
u_int8_t vr_revid; /* Rhine chip revision */
u_int8_t vr_flags; /* See VR_F_* below */
struct vr_list_data *vr_ldata;
struct vr_chain_data vr_cdata;
struct callout vr_stat_callout;
struct mtx vr_mtx;
int suspended; /* if 1, sleeping/detaching */
#ifdef DEVICE_POLLING
int rxcycles;
#endif
};
#define VR_F_RESTART 0x01 /* Restart unit on next tick */
#define VR_LOCK(_sc) mtx_lock(&(_sc)->vr_mtx)
#define VR_UNLOCK(_sc) mtx_unlock(&(_sc)->vr_mtx)
#define VR_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vr_mtx, MA_OWNED)
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg)
#define VR_TIMEOUT 1000
#define ETHER_ALIGN 2
/*
* General constants that are fun to know.
*
* VIA vendor ID
*/
#define VIA_VENDORID 0x1106
/*
* VIA Rhine device IDs.
*/
#define VIA_DEVICEID_RHINE 0x3043
#define VIA_DEVICEID_RHINE_II 0x6100
#define VIA_DEVICEID_RHINE_II_2 0x3065
#define VIA_DEVICEID_RHINE_III 0x3106
#define VIA_DEVICEID_RHINE_III_M 0x3053
/*
* Delta Electronics device ID.
*/
#define DELTA_VENDORID 0x1500
/*
* Delta device IDs.
*/
#define DELTA_DEVICEID_RHINE_II 0x1320
/*
* Addtron vendor ID.
*/
#define ADDTRON_VENDORID 0x4033
/*
* Addtron device IDs.
*/
#define ADDTRON_DEVICEID_RHINE_II 0x1320
/*
* VIA Rhine revision IDs
*/
#define REV_ID_VT3043_E 0x04
#define REV_ID_VT3071_A 0x20
#define REV_ID_VT3071_B 0x21
#define REV_ID_VT3065_A 0x40
#define REV_ID_VT3065_B 0x41
#define REV_ID_VT3065_C 0x42
#define REV_ID_VT6102_APOLLO 0x74
#define REV_ID_VT3106 0x80
#define REV_ID_VT3106_J 0x80 /* 0x80-0x8F */
#define REV_ID_VT3106_S 0x90 /* 0x90-0xA0 */
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define VR_PCI_VENDOR_ID 0x00
#define VR_PCI_DEVICE_ID 0x02
#define VR_PCI_COMMAND 0x04
#define VR_PCI_STATUS 0x06
#define VR_PCI_REVID 0x08
#define VR_PCI_CLASSCODE 0x09
#define VR_PCI_LATENCY_TIMER 0x0D
#define VR_PCI_HEADER_TYPE 0x0E
#define VR_PCI_LOIO 0x10
#define VR_PCI_LOMEM 0x14
#define VR_PCI_BIOSROM 0x30
#define VR_PCI_INTLINE 0x3C
#define VR_PCI_INTPIN 0x3D
#define VR_PCI_MINGNT 0x3E
#define VR_PCI_MINLAT 0x0F
#define VR_PCI_RESETOPT 0x48
#define VR_PCI_EEPROM_DATA 0x4C
#define VR_PCI_MODE 0x50
#define VR_MODE3_MIION 0x04
/* power management registers */
#define VR_PCI_CAPID 0xDC /* 8 bits */
#define VR_PCI_NEXTPTR 0xDD /* 8 bits */
#define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */
#define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
#define VR_PSTATE_MASK 0x0003
#define VR_PSTATE_D0 0x0000
#define VR_PSTATE_D1 0x0002
#define VR_PSTATE_D2 0x0002
#define VR_PSTATE_D3 0x0003
#define VR_PME_EN 0x0010
#define VR_PME_STATUS 0x8000
#ifdef __alpha__
#undef vtophys
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
#endif