diff --git a/headers/private/graphics/nvidia/nv_macros.h b/headers/private/graphics/nvidia/nv_macros.h
index 7065ba03f6..c68877c233 100644
--- a/headers/private/graphics/nvidia/nv_macros.h
+++ b/headers/private/graphics/nvidia/nv_macros.h
@@ -611,6 +611,9 @@
#define NV32_CURCONF 0x00600810
#define NV32_PANEL_PWR 0x0060081c
#define NV32_FUNCSEL 0x00600860
+#define NV32_NV4E_I2CBUS_0 0x00600870
+#define NV32_NV4E_I2CBUS_1 0x00600874
+#define NV32_NV4E_I2CBUS_2 0x00600850
/* secondary head */
#define NV8_ATTR2INDW 0x006033c0
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c
index b16aa486f1..6072f5baa0 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_general.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c
@@ -92,7 +92,7 @@ status_t nv_general_powerup()
{
status_t status;
- LOG(1,("POWERUP: Haiku nVidia Accelerant 1.11 running.\n"));
+ LOG(1,("POWERUP: Haiku nVidia Accelerant 1.12 running.\n"));
/* log VBLANK INT usability status */
if (si->ps.int_assigned)
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_i2c.c b/src/add-ons/accelerants/nvidia/engine/nv_i2c.c
index 0393230f87..752d17806d 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_i2c.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_i2c.c
@@ -2,7 +2,7 @@
* i2c interface.
* Bus should be run at max. 100kHz: see original Philips I2C specification
*
- * Rudolf Cornelissen 12/2002-10/2009
+ * Rudolf Cornelissen 12/2002-4/2021
*/
#define MODULE_BIT 0x00004000
@@ -46,73 +46,144 @@ static void i2c_select_bus_set(bool set)
static void OutSCL(uint8 BusNR, bool Bit)
{
uint8 data;
+ uint32 data32;
- switch (BusNR) {
- case 0:
- data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01;
- if (Bit)
- CRTCW(WR_I2CBUS_0, (data | 0x20));
- else
- CRTCW(WR_I2CBUS_0, (data & ~0x20));
- break;
- case 1:
- data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01;
- if (Bit)
- CRTCW(WR_I2CBUS_1, (data | 0x20));
- else
- CRTCW(WR_I2CBUS_1, (data & ~0x20));
- break;
- case 2:
- data = (CRTCR(WR_I2CBUS_2) & 0xf0) | 0x01;
- if (Bit)
- CRTCW(WR_I2CBUS_2, (data | 0x20));
- else
- CRTCW(WR_I2CBUS_2, (data & ~0x20));
- break;
+ if ((CFGR(DEVID) & 0xfff0ffff) == 0x024010de) {
+ /* C51 chipset */
+ switch (BusNR) {
+ case 0:
+ data32 = NV_REG32(NV32_NV4E_I2CBUS_0) & ~0x2f;
+ if (Bit)
+ NV_REG32(NV32_NV4E_I2CBUS_0) = data32 | 0x21;
+ else
+ NV_REG32(NV32_NV4E_I2CBUS_0) = data32 | 0x01;
+ break;
+ case 1:
+ data32 = NV_REG32(NV32_NV4E_I2CBUS_1) & ~0x2f;
+ if (Bit)
+ NV_REG32(NV32_NV4E_I2CBUS_1) = data32 | 0x21;
+ else
+ NV_REG32(NV32_NV4E_I2CBUS_1) = data32 | 0x01;
+ break;
+ case 2:
+ data32 = NV_REG32(NV32_NV4E_I2CBUS_2) & ~0x2f;
+ if (Bit)
+ NV_REG32(NV32_NV4E_I2CBUS_2) = data32 | 0x21;
+ else
+ NV_REG32(NV32_NV4E_I2CBUS_2) = data32 | 0x01;
+ break;
+ }
+ } else {
+ switch (BusNR) {
+ case 0:
+ data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01;
+ if (Bit)
+ CRTCW(WR_I2CBUS_0, (data | 0x20));
+ else
+ CRTCW(WR_I2CBUS_0, (data & ~0x20));
+ break;
+ case 1:
+ data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01;
+ if (Bit)
+ CRTCW(WR_I2CBUS_1, (data | 0x20));
+ else
+ CRTCW(WR_I2CBUS_1, (data & ~0x20));
+ break;
+ case 2:
+ data = (CRTCR(WR_I2CBUS_2) & 0xf0) | 0x01;
+ if (Bit)
+ CRTCW(WR_I2CBUS_2, (data | 0x20));
+ else
+ CRTCW(WR_I2CBUS_2, (data & ~0x20));
+ break;
+ }
}
}
static void OutSDA(uint8 BusNR, bool Bit)
{
uint8 data;
+ uint32 data32;
- switch (BusNR) {
- case 0:
- data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01;
- if (Bit)
- CRTCW(WR_I2CBUS_0, (data | 0x10));
- else
- CRTCW(WR_I2CBUS_0, (data & ~0x10));
- break;
- case 1:
- data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01;
- if (Bit)
- CRTCW(WR_I2CBUS_1, (data | 0x10));
- else
- CRTCW(WR_I2CBUS_1, (data & ~0x10));
- break;
- case 2:
- data = (CRTCR(WR_I2CBUS_2) & 0xf0) | 0x01;
- if (Bit)
- CRTCW(WR_I2CBUS_2, (data | 0x10));
- else
- CRTCW(WR_I2CBUS_2, (data & ~0x10));
- break;
+ if ((CFGR(DEVID) & 0xfff0ffff) == 0x024010de) {
+ /* C51 chipset */
+ switch (BusNR) {
+ case 0:
+ data32 = NV_REG32(NV32_NV4E_I2CBUS_0) & ~0x1f;
+ if (Bit)
+ NV_REG32(NV32_NV4E_I2CBUS_0) = data32 | 0x11;
+ else
+ NV_REG32(NV32_NV4E_I2CBUS_0) = data32 | 0x01;
+ break;
+ case 1:
+ data32 = NV_REG32(NV32_NV4E_I2CBUS_1) & ~0x1f;
+ if (Bit)
+ NV_REG32(NV32_NV4E_I2CBUS_1) = data32 | 0x11;
+ else
+ NV_REG32(NV32_NV4E_I2CBUS_1) = data32 | 0x01;
+ break;
+ case 2:
+ data32 = NV_REG32(NV32_NV4E_I2CBUS_2) & ~0x1f;
+ if (Bit)
+ NV_REG32(NV32_NV4E_I2CBUS_2) = data32 | 0x11;
+ else
+ NV_REG32(NV32_NV4E_I2CBUS_2) = data32 | 0x01;
+ break;
+ }
+ } else {
+ switch (BusNR) {
+ case 0:
+ data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01;
+ if (Bit)
+ CRTCW(WR_I2CBUS_0, (data | 0x10));
+ else
+ CRTCW(WR_I2CBUS_0, (data & ~0x10));
+ break;
+ case 1:
+ data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01;
+ if (Bit)
+ CRTCW(WR_I2CBUS_1, (data | 0x10));
+ else
+ CRTCW(WR_I2CBUS_1, (data & ~0x10));
+ break;
+ case 2:
+ data = (CRTCR(WR_I2CBUS_2) & 0xf0) | 0x01;
+ if (Bit)
+ CRTCW(WR_I2CBUS_2, (data | 0x10));
+ else
+ CRTCW(WR_I2CBUS_2, (data & ~0x10));
+ break;
+ }
}
}
static bool InSCL(uint8 BusNR)
{
- switch (BusNR) {
- case 0:
- if ((CRTCR(RD_I2CBUS_0) & 0x04)) return true;
- break;
- case 1:
- if ((CRTCR(RD_I2CBUS_1) & 0x04)) return true;
- break;
- case 2:
- if ((CRTCR(RD_I2CBUS_2) & 0x04)) return true;
- break;
+ if ((CFGR(DEVID) & 0xfff0ffff) == 0x024010de) {
+ /* C51 chipset */
+ switch (BusNR) {
+ case 0:
+ if (NV_REG32(NV32_NV4E_I2CBUS_0) & 0x00040000) return true;
+ break;
+ case 1:
+ if (NV_REG32(NV32_NV4E_I2CBUS_1) & 0x00040000) return true;
+ break;
+ case 2:
+ if (NV_REG32(NV32_NV4E_I2CBUS_2) & 0x00040000) return true;
+ break;
+ }
+ } else {
+ switch (BusNR) {
+ case 0:
+ if ((CRTCR(RD_I2CBUS_0) & 0x04)) return true;
+ break;
+ case 1:
+ if ((CRTCR(RD_I2CBUS_1) & 0x04)) return true;
+ break;
+ case 2:
+ if ((CRTCR(RD_I2CBUS_2) & 0x04)) return true;
+ break;
+ }
}
return false;
@@ -120,16 +191,31 @@ static bool InSCL(uint8 BusNR)
static bool InSDA(uint8 BusNR)
{
- switch (BusNR) {
- case 0:
- if ((CRTCR(RD_I2CBUS_0) & 0x08)) return true;
- break;
- case 1:
- if ((CRTCR(RD_I2CBUS_1) & 0x08)) return true;
- break;
- case 2:
- if ((CRTCR(RD_I2CBUS_2) & 0x08)) return true;
- break;
+ if ((CFGR(DEVID) & 0xfff0ffff) == 0x024010de) {
+ /* C51 chipset */
+ switch (BusNR) {
+ case 0:
+ if (NV_REG32(NV32_NV4E_I2CBUS_0) & 0x00080000) return true;
+ break;
+ case 1:
+ if (NV_REG32(NV32_NV4E_I2CBUS_1) & 0x00080000) return true;
+ break;
+ case 2:
+ if (NV_REG32(NV32_NV4E_I2CBUS_2) & 0x00080000) return true;
+ break;
+ }
+ } else {
+ switch (BusNR) {
+ case 0:
+ if ((CRTCR(RD_I2CBUS_0) & 0x08)) return true;
+ break;
+ case 1:
+ if ((CRTCR(RD_I2CBUS_1) & 0x08)) return true;
+ break;
+ case 2:
+ if ((CRTCR(RD_I2CBUS_2) & 0x08)) return true;
+ break;
+ }
}
return false;
diff --git a/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html b/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html
index c9cca3f4d9..d5839b8696 100644
--- a/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html
+++ b/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html
@@ -4,11 +4,12 @@
Changes done for each driverversion:
-head (Haiku repository 1.11, Rudolf)
+head (Haiku repository 1.12, Rudolf)
- Fixed driver trouble on several Geforce 6000-6200 cards and maybe even more where the refreshrate was not properly calculated causing things like only displaying a part of the screen, a wobbly screen, no screen at all or just displaying at a too low rate. In cases where the GPU and/or RAM PLL is programmed on cards (depending on the nvidia.settings file) this might also solve random 'noise' or flickering across the entire screen(s). It turns out some newer supported cards outthere (notably Nforce 4 and 4xx types) use a new crystal frequency base (25 Mhz) for the GPU chip which was not yet detected by the driver.
+
- Fixed I2C buses not working and so screen DDC/EDID fetch failing on C51 chips specifically. This makes default startup resolution, screenprefs panel and widescreen modes available without nvidia.settings file tricks on a number of Geforce 6100(Go) and 6150(Go) graphics outthere. Now there should nolonger be cards without functioning (but implemented) I2C channels in this driver.
-head (Haiku repository 1.10, Rudolf)
+Nvidia driver 1.10 (Rudolf)
- Fixed driver assuming enabling AGP mode succeeded on some occasions if it did not block it itself. Blocking AGP mode completely via the AGP busmanager (option 'block_agp') resulted in a crashing acceleration engine because it was setup for AGP transfers instead of using PCI transfers. Error was solved with help from user kraton.
- Fixed shared_info struct problem occuring when 3D 'accelerant' is used (tested Alpha 4.1): the TVencoder type definition list apparantly gets some memory assigned these days when done inside the definition of shared_info. Moved encoder list outside the shared_info definition.