- print vars of interest to help setup mem map
- shuffle memory map - set up transparent translations: first 32MB of RAM and last 16MB for IO space. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26478 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
François Revol
parent
6eeea348d0
commit
36265c4de7
@ -5,25 +5,70 @@
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#ifndef ATARI_MEMORY_MAP_H
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#define ATARI_MEMORY_MAP_H
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#define ATARI_CHIPRAM_TOP_TT 0x00a00000
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/* -> e00000 is VME for MegaST*/
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#define ATARI_CHIPRAM_TOP_FALCON 0x00e00000
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/* the DMA-accessible RAM */
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#define ATARI_CHIPRAM_BASE 0x00000000
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#define ATARI_CHIPRAM_MAX 0x00e00000
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#define ATARI_CHIPRAM_LAST \
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(ATARI_CHIPRAM_BASE + (ATARI_CHIPRAM_MAX - 1))
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#define ATARI_ROM_BASE ATARI_CHIPRAM_TOP_FALCON
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#define ATARI_ROM_TOP 0x00f00000
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#define ATARI_IO_BASE ATARI_ROM_TOP
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#define ATARI_CARTRIDGE_BASE 0x00fa0000
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#define ATARI_OLD_ROM_BASE 0x00fc0000
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#define ATARI_TOSROM_BASE 0x00e00000
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#define ATARI_TOSROM_MAX 0x00100000
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#define ATARI_TOSROM_LAST \
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(ATARI_TOSROM_BASE + (ATARI_TOSROM_MAX - 1))
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#define ATARI_IO_TOP 0x01000000
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#define ATARI_FASTRAM_TOP ATARI_IO_TOP
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/* some reserved ST I/O there... */
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/* cartridge ROM */
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#define ATARI_CARTROM_BASE 0x00fa0000
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#define ATARI_CARTROM_MAX 0x00020000
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#define ATARI_CARTROM_LAST \
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(ATARI_CARTROM_BASE + (ATARI_CARTROM_MAX - 1))
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#define ATARI_SYSROM_BASE 0x00fc0000
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#define ATARI_SYSROM_MAX 0x00030000
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#define ATARI_SYSROM_LAST \
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(ATARI_SYSROM_BASE + (ATARI_SYSROM_MAX - 1))
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/* more ST I/O there... */
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/* the fast, non-DMA-accessible RAM */
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#define ATARI_FASTRAM_BASE 0x01000000
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// max on TT,
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// but there is nothing beyond until SHADOW_BASE
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//#define ATARI_FASTRAM_MAX 0x00400000
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#define ATARI_FASTRAM_MAX 0xfe000000
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#define ATARI_FASTRAM_LAST \
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(ATARI_FASTRAM_BASE + (ATARI_FASTRAM_MAX - 1))
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/* due to ST legacy (24 bit addressing), IO is actually there */
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#define ATARI_SHADOW_BASE 0xff000000
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/* how we will use it */
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#define ATARI_IO_BASE (ATARI_SHADOW_BASE + 0x00f00000)
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#define ATARI_IO_MAX 0x00100000
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#define ATARI_IO_LAST \
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(ATARI_IO_BASE + (ATARI_IO_MAX - 1))
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/* physical memory layout as used by the bootloader */
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//#define ATARI_ZBEOS_STACK_BASE 0x00040000
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#define ATARI_ZBEOS_STACK_BASE 0x00060000
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#define ATARI_ZBEOS_STACK_END 0x00080000
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#define ATARI_ZBEOS_BASE 0x00080000 /* from .prg shell.S will copy itself there */
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/* from .prg shell.S will copy itself there
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* must stay in sync with src/system/ldscripts/m68k/boot_prg_atari_m68k.ld
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*/
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#define ATARI_ZBEOS_BASE 0x00080000
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#define ATARI_ZBEOS_MAX 0x00080000
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#define ATARI_ZBEOS_LAST \
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(ATARI_ZBEOS_BASE + (ATARI_ZBEOS_MAX - 1))
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#define ATARI_STRAM_VIRT_BASE
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#endif /* ATARI_MEMORY_MAP_H */
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@ -6,6 +6,7 @@
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*/
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#include "atari_memory_map.h"
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#include "mmu.h"
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#include <boot/platform.h>
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@ -46,20 +47,14 @@
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/** The (physical) memory layout of the boot loader is currently as follows:
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* 0x0800 - 0x10000 supervisor mode stack (1) XXX: more ? x86 starts at 500
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* 0x10000 - ? code (up to ~500 kB)
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* unused (TT0 instead):
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* 0x90000 1st temporary page table (identity maps 0-4 MB)
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* 0x91000 2nd (4-8 MB)
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*
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* 0x92000 - 0x92000 further page tables
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* 0x100000 page directory
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* 0x100000 or FAST_RAM_BASE if any:
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* ... page directory
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* ... boot loader heap (32 kB)
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* ... free physical memory
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* [0xa00000] end of chip RAM for TT (falcon has more till ROM)
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* [0xe00000 - 0xf00000 TOS ROM]
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* [0xf00000 - 0x1000000 I/O]
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XXX: where is the video buffer ?
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* 0xdNNNNN video buffer usually there, as per v_bas_ad
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* (=Logbase() but Physbase() is better)
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*
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* The first 16 MB (2) are identity mapped (0x0 - 0x1000000); paging
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* The first 32 MB (2) are identity mapped (0x0 - 0x1000000); paging
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* is turned on. The kernel is mapped at 0x80000000, all other stuff
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* mapped by the loader (kernel args, modules, driver settings, ...)
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* comes after 0x81000000 which means that there is currently only
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@ -67,9 +62,10 @@
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*
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* (1) no need for user stack, we are already in supervisor mode in the
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* loader.
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* (2) maps the whole regular ST space; transparent translation registers
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* have larger granularity anyway;
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* (2) maps the whole regular ST space; transparent translation registers
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* have larger granularity anyway.
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*/
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#warning M68K: check for Physbase() < ST_RAM_TOP
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#define TRACE_MMU
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#ifdef TRACE_MMU
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@ -444,7 +440,8 @@ mmu_init_for_kernel(void)
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// remove identity mapping of ST space
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gMMUOps->set_tt(0, NULL, 0, 0);
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// actually done by the kernel when it's done using query_early
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//gMMUOps->set_tt(0, NULL, 0, 0);
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#if 0
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// set up a new idt
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@ -594,6 +591,11 @@ mmu_init(void)
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gKernelArgs.num_physical_allocated_ranges = 1;
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// remember the start of the allocated physical pages
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// enable transparent translation of the first 32 MB
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gMMUOps->set_tt(0, ATARI_CHIPRAM_BASE, 0x02000000, 0);
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// enable transparent translation of the 16MB ST shadow range for I/O
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gMMUOps->set_tt(0, ATARI_SHADOW_BASE, 0x01000000, 0);
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init_page_directory();
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#if 0
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@ -45,20 +45,20 @@ initialize(void)
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static status_t
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set_tt(int which, addr_t pa, size_t len, uint32 perms)
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{
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TRACE(("mmu_030:set_tt(%d, 0x%lx, %ld, 0x%08lx)\n", which, pa, len, perms));
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TRACE(("mmu_030:set_tt(%d, 0x%lx, 0x%lx, 0x%08lx)\n", which, pa, len, perms));
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uint32 mask;
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uint32 ttr = 0;
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mask = 1;
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mask = 0x0000ffff;
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if (len) {
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len = (len >> 24) & 0x00ff;
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while (len >>= 1)
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mask <<= 1;
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mask = (mask - 1);
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// enable, cachable(?), r/w
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// super only
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// mc68030 user's manual, page 9-57
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ttr = 0x08043;
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ttr |= (pa & 0xff000000);
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ttr |= ((mask & 0xff000000) >> 8);
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ttr |= (mask & 0x00ff0000);
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}
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TRACE(("mmu_030:set_tt: 0x%08lx\n", ttr));
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@ -43,21 +43,21 @@ initialize(void)
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static status_t
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set_tt(int which, addr_t pa, size_t len, uint32 perms)
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set_tt(int which, addr_t pa, size_t len, uint32 perms /* NOTUSED */)
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{
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TRACE(("mmu_040:set_tt(%d, 0x%lx, %ld, 0x%08lx)\n", which, pa, len, perms));
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TRACE(("mmu_040:set_tt(%d, 0x%lx, 0x%lx, 0x%08lx)\n", which, pa, len, perms));
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uint32 mask;
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uint32 ttr = 0;
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mask = 1;
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mask = 0x0000ffff;
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if (len) {
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len = (len >> 24) & 0x00ff;
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while (len >>= 1)
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mask <<= 1;
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mask = (mask - 1);
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// enable, super only, upa=0,
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// cachable write-through, rw
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ttr = 0x0a000;
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ttr |= (pa & 0xff000000);
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ttr |= ((mask & 0xff000000) >> 8);
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ttr |= (mask & 0x00ff0000);
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}
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TRACE(("mmu_040:set_tt: 0x%08lx\n", ttr));
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@ -123,11 +123,16 @@ _start(void)
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init_nat_features();
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//serial_init();
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console_init();
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Bconout(DEV_CON, 'K');
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cpu_init();
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console_init();
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Bconout(DEV_CON, 'U');
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//mmu_init();
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dprintf("membot = %p\n", *TOSVAR_membot);
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dprintf("memtop = %p\n", *TOSVAR_memtop);
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dprintf("v_bas_ad= %p\n", *TOSVAR_v_bas_ad);
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dprintf("phystop = %p\n", *TOSVARphystop);
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dprintf("ramtop = %p\n", *TOSVARramtop);
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cpu_init();
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mmu_init();
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// wait a bit to give the user the opportunity to press a key
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spin(750000);
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