ARM: add DTS files required for Beagle-XM target
These were taking from mainline Linux (arch/arm/boot/dts)
This commit is contained in:
Ithamar R. Adema
parent
a17ff8279b
commit
35afac0769
15
src/data/dts/dt-bindings/gpio/gpio.h
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15
src/data/dts/dt-bindings/gpio/gpio.h
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@ -0,0 +1,15 @@
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/*
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* This header provides constants for most GPIO bindings.
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*
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* Most GPIO bindings include a flags cell as part of the GPIO specifier.
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* In most cases, the format of the flags cell uses the standard values
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* defined in this header.
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*/
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#ifndef _DT_BINDINGS_GPIO_GPIO_H
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#define _DT_BINDINGS_GPIO_GPIO_H
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#define GPIO_ACTIVE_HIGH 0
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#define GPIO_ACTIVE_LOW 1
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#endif
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19
src/data/dts/dt-bindings/interrupt-controller/irq.h
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19
src/data/dts/dt-bindings/interrupt-controller/irq.h
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@ -0,0 +1,19 @@
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/*
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* This header provides constants for most IRQ bindings.
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*
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* Most IRQ bindings include a flags cell as part of the IRQ specifier.
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* In most cases, the format of the flags cell uses the standard values
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* defined in this header.
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*/
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#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
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#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
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#define IRQ_TYPE_NONE 0
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#define IRQ_TYPE_EDGE_RISING 1
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#define IRQ_TYPE_EDGE_FALLING 2
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#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
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#define IRQ_TYPE_LEVEL_HIGH 4
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#define IRQ_TYPE_LEVEL_LOW 8
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#endif
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90
src/data/dts/dt-bindings/pinctrl/omap.h
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90
src/data/dts/dt-bindings/pinctrl/omap.h
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@ -0,0 +1,90 @@
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/*
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* This header provides constants for OMAP pinctrl bindings.
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*
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* Copyright (C) 2009 Nokia
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* Copyright (C) 2009-2010 Texas Instruments
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*/
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#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
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#define _DT_BINDINGS_PINCTRL_OMAP_H
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/* 34xx mux mode options for each pin. See TRM for options */
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#define MUX_MODE0 0
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#define MUX_MODE1 1
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#define MUX_MODE2 2
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#define MUX_MODE3 3
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#define MUX_MODE4 4
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#define MUX_MODE5 5
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#define MUX_MODE6 6
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#define MUX_MODE7 7
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/* 24xx/34xx mux bit defines */
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#define PULL_ENA (1 << 3)
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#define PULL_UP (1 << 4)
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#define ALTELECTRICALSEL (1 << 5)
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/* omap3/4/5 specific mux bit defines */
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#define INPUT_EN (1 << 8)
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#define OFF_EN (1 << 9)
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#define OFFOUT_EN (1 << 10)
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#define OFFOUT_VAL (1 << 11)
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#define OFF_PULL_EN (1 << 12)
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#define OFF_PULL_UP (1 << 13)
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#define WAKEUP_EN (1 << 14)
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#define WAKEUP_EVENT (1 << 15)
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/* Active pin states */
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#define PIN_OUTPUT 0
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#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
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#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
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#define PIN_INPUT INPUT_EN
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#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
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#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
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/* Off mode states */
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#define PIN_OFF_NONE 0
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#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
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#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN)
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#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
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#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
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#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
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/*
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* Macros to allow using the absolute physical address instead of the
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* padconf registers instead of the offset from padconf base.
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*/
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#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
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#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
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#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
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#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
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#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
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#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
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#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
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#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
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#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
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#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
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/*
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* Macros to allow using the offset from the padconf physical address
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* instead of the offset from padconf base.
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*/
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#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
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#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
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#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
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/*
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* Define some commonly used pins configured by the boards.
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* Note that some boards use alternative pins, so check
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* the schematics before using these.
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*/
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#define OMAP3_UART1_RX 0x152
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#define OMAP3_UART2_RX 0x14a
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#define OMAP3_UART3_RX 0x16e
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#define OMAP4_UART2_RX 0xdc
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#define OMAP4_UART3_RX 0x104
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#define OMAP4_UART4_RX 0x11c
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#endif
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366
src/data/dts/omap3-beagle-xm.dts
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366
src/data/dts/omap3-beagle-xm.dts
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@ -0,0 +1,366 @@
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/*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "omap36xx.dtsi"
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/ {
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model = "TI OMAP3 BeagleBoard xM";
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compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3";
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cpus {
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cpu@0 {
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cpu0-supply = <&vcc>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512 MB */
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};
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aliases {
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display0 = &dvi0;
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display1 = &tv0;
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};
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leds {
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compatible = "gpio-leds";
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heartbeat {
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label = "beagleboard::usr0";
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gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
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linux,default-trigger = "heartbeat";
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};
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mmc {
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label = "beagleboard::usr1";
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gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
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linux,default-trigger = "mmc0";
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};
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};
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pwmleds {
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compatible = "pwm-leds";
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pmu_stat {
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label = "beagleboard::pmu_stat";
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pwms = <&twl_pwmled 1 7812500>;
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max-brightness = <127>;
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};
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};
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sound {
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compatible = "ti,omap-twl4030";
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ti,model = "omap3beagle";
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ti,mcbsp = <&mcbsp2>;
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ti,codec = <&twl_audio>;
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};
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gpio_keys {
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compatible = "gpio-keys";
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user {
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label = "user";
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gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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linux,code = <0x114>;
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gpio-key,wakeup;
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};
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};
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/* HS USB Port 2 Power */
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hsusb2_power: hsusb2_power_reg {
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compatible = "regulator-fixed";
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regulator-name = "hsusb2_vbus";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
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startup-delay-us = <70000>;
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};
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/* HS USB Host PHY on PORT 2 */
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hsusb2_phy: hsusb2_phy {
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compatible = "usb-nop-xceiv";
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reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
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vcc-supply = <&hsusb2_power>;
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};
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tfp410: encoder@0 {
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compatible = "ti,tfp410";
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powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
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/* XXX pinctrl from twl */
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tfp410_in: endpoint@0 {
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remote-endpoint = <&dpi_out>;
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};
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};
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port@1 {
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reg = <1>;
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tfp410_out: endpoint@0 {
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remote-endpoint = <&dvi_connector_in>;
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};
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};
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};
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};
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dvi0: connector@0 {
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compatible = "dvi-connector";
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label = "dvi";
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digital;
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ddc-i2c-bus = <&i2c3>;
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port {
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dvi_connector_in: endpoint {
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remote-endpoint = <&tfp410_out>;
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};
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};
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};
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tv0: connector@1 {
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compatible = "svideo-connector";
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label = "tv";
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port {
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tv_connector_in: endpoint {
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remote-endpoint = <&venc_out>;
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};
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};
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};
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};
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&omap3_pmx_wkup {
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gpio1_pins: pinmux_gpio1_pins {
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pinctrl-single,pins = <
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0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
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>;
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};
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dss_dpi_pins2: pinmux_dss_dpi_pins1 {
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pinctrl-single,pins = <
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0x0a (PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
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0x0c (PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
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0x10 (PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
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0x12 (PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
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0x14 (PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
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0x16 (PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
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>;
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};
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};
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&omap3_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <
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&hsusb2_pins
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>;
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uart3_pins: pinmux_uart3_pins {
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pinctrl-single,pins = <
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0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
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0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
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>;
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};
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hsusb2_pins: pinmux_hsusb2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
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OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
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OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
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OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
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OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
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OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
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>;
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};
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dss_dpi_pins1: pinmux_dss_dpi_pins2 {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
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OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
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OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
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OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
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OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
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OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
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OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
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OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
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OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
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OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
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OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
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OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
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OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
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OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
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OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
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OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
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OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
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OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
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OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
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OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
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OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
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OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
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>;
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};
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};
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&omap3_pmx_core2 {
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pinctrl-names = "default";
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pinctrl-0 = <
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&hsusb2_2_pins
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>;
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hsusb2_2_pins: pinmux_hsusb2_2_pins {
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pinctrl-single,pins = <
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OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
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OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
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OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
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OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
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OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
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OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
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>;
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};
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};
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&i2c1 {
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clock-frequency = <2600000>;
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twl: twl@48 {
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reg = <0x48>;
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interrupts = <7>; /* SYS_NIRQ cascaded to intc */
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interrupt-parent = <&intc>;
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twl_audio: audio {
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compatible = "ti,twl4030-audio";
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codec {
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};
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};
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twl_power: power {
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compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off";
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ti,use_poweroff;
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};
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};
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};
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#include "twl4030.dtsi"
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#include "twl4030_omap3.dtsi"
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&i2c2 {
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clock-frequency = <400000>;
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};
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&i2c3 {
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clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
vmmc-supply = <&vmmc1>;
|
||||
vmmc_aux-supply = <&vsim>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
/* pullups: BIT(1) */
|
||||
ti,pullups = <0x000002>;
|
||||
/*
|
||||
* pulldowns:
|
||||
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
|
||||
* BIT(15), BIT(16), BIT(17)
|
||||
*/
|
||||
ti,pulldowns = <0x03a1c4>;
|
||||
};
|
||||
|
||||
&usb_otg_hs {
|
||||
interface-type = <0>;
|
||||
usb-phy = <&usb2_phy>;
|
||||
phys = <&usb2_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
mode = <3>;
|
||||
power = <50>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio1_pins>;
|
||||
};
|
||||
|
||||
&usbhshost {
|
||||
port2-mode = "ehci-phy";
|
||||
};
|
||||
|
||||
&usbhsehci {
|
||||
phys = <0 &hsusb2_phy>;
|
||||
};
|
||||
|
||||
&vaux2 {
|
||||
regulator-name = "usb_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mcbsp2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&dss_dpi_pins1
|
||||
&dss_dpi_pins2
|
||||
>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint {
|
||||
remote-endpoint = <&tfp410_in>;
|
||||
data-lines = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&venc {
|
||||
status = "ok";
|
||||
|
||||
vdda-supply = <&vdac>;
|
||||
|
||||
port {
|
||||
venc_out: endpoint {
|
||||
remote-endpoint = <&tv_connector_in>;
|
||||
ti,channels = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
814
src/data/dts/omap3.dtsi
Normal file
814
src/data/dts/omap3.dtsi
Normal file
@ -0,0 +1,814 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP3 SoC
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/pinctrl/omap.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap3430", "ti,omap3";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
|
||||
clocks = <&dpll1_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a8-pmu";
|
||||
reg = <0x54000000 0x800000>;
|
||||
interrupts = <3>;
|
||||
ti,hwmods = "debugss";
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap3-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
|
||||
iva: iva {
|
||||
compatible = "ti,iva2.2";
|
||||
ti,hwmods = "iva";
|
||||
|
||||
dsp {
|
||||
compatible = "ti,omap3-c64";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since it will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x68000000 0x10000>;
|
||||
interrupts = <9 10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
|
||||
aes: aes@480c5000 {
|
||||
compatible = "ti,omap3-aes";
|
||||
ti,hwmods = "aes";
|
||||
reg = <0x480c5000 0x50>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
|
||||
prm: prm@48306000 {
|
||||
compatible = "ti,omap3-prm";
|
||||
reg = <0x48306000 0x4000>;
|
||||
interrupts = <11>;
|
||||
|
||||
prm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm: cm@48004000 {
|
||||
compatible = "ti,omap3-cm";
|
||||
reg = <0x48004000 0x4000>;
|
||||
|
||||
cm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@48002000 {
|
||||
compatible = "ti,omap3-scrm";
|
||||
reg = <0x48002000 0x2000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
counter32k: counter@48320000 {
|
||||
compatible = "ti,omap-counter32k";
|
||||
reg = <0x48320000 0x20>;
|
||||
ti,hwmods = "counter_32k";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@48200000 {
|
||||
compatible = "ti,omap3-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
sdma: dma-controller@48056000 {
|
||||
compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
|
||||
reg = <0x48056000 0x1000>;
|
||||
interrupts = <12>,
|
||||
<13>,
|
||||
<14>,
|
||||
<15>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <32>;
|
||||
#dma-requests = <96>;
|
||||
};
|
||||
|
||||
omap3_pmx_core: pinmux@48002030 {
|
||||
compatible = "ti,omap3-padconf", "pinctrl-single";
|
||||
reg = <0x48002030 0x0238>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0xff1f>;
|
||||
};
|
||||
|
||||
omap3_pmx_wkup: pinmux@48002a00 {
|
||||
compatible = "ti,omap3-padconf", "pinctrl-single";
|
||||
reg = <0x48002a00 0x5c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0xff1f>;
|
||||
};
|
||||
|
||||
omap3_scm_general: tisyscon@48002270 {
|
||||
compatible = "syscon";
|
||||
reg = <0x48002270 0x2f0>;
|
||||
};
|
||||
|
||||
pbias_regulator: pbias_regulator {
|
||||
compatible = "ti,pbias-omap";
|
||||
reg = <0x2b0 0x4>;
|
||||
syscon = <&omap3_scm_general>;
|
||||
pbias_mmc_reg: pbias_mmc_omap2430 {
|
||||
regulator-name = "pbias_mmc_omap2430";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@48310000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
reg = <0x48310000 0x200>;
|
||||
interrupts = <29>;
|
||||
ti,hwmods = "gpio1";
|
||||
ti,gpio-always-on;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@49050000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
reg = <0x49050000 0x200>;
|
||||
interrupts = <30>;
|
||||
ti,hwmods = "gpio2";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@49052000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
reg = <0x49052000 0x200>;
|
||||
interrupts = <31>;
|
||||
ti,hwmods = "gpio3";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@49054000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
reg = <0x49054000 0x200>;
|
||||
interrupts = <32>;
|
||||
ti,hwmods = "gpio4";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@49056000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
reg = <0x49056000 0x200>;
|
||||
interrupts = <33>;
|
||||
ti,hwmods = "gpio5";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@49058000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
reg = <0x49058000 0x200>;
|
||||
interrupts = <34>;
|
||||
ti,hwmods = "gpio6";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart1: serial@4806a000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
reg = <0x4806a000 0x2000>;
|
||||
interrupts-extended = <&intc 72>;
|
||||
dmas = <&sdma 49 &sdma 50>;
|
||||
dma-names = "tx", "rx";
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart2: serial@4806c000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
reg = <0x4806c000 0x400>;
|
||||
interrupts-extended = <&intc 73>;
|
||||
dmas = <&sdma 51 &sdma 52>;
|
||||
dma-names = "tx", "rx";
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart3: serial@49020000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
reg = <0x49020000 0x400>;
|
||||
interrupts-extended = <&intc 74>;
|
||||
dmas = <&sdma 53 &sdma 54>;
|
||||
dma-names = "tx", "rx";
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48070000 {
|
||||
compatible = "ti,omap3-i2c";
|
||||
reg = <0x48070000 0x80>;
|
||||
interrupts = <56>;
|
||||
dmas = <&sdma 27 &sdma 28>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c1";
|
||||
};
|
||||
|
||||
i2c2: i2c@48072000 {
|
||||
compatible = "ti,omap3-i2c";
|
||||
reg = <0x48072000 0x80>;
|
||||
interrupts = <57>;
|
||||
dmas = <&sdma 29 &sdma 30>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c2";
|
||||
};
|
||||
|
||||
i2c3: i2c@48060000 {
|
||||
compatible = "ti,omap3-i2c";
|
||||
reg = <0x48060000 0x80>;
|
||||
interrupts = <61>;
|
||||
dmas = <&sdma 25 &sdma 26>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c3";
|
||||
};
|
||||
|
||||
mailbox: mailbox@48094000 {
|
||||
compatible = "ti,omap3-mailbox";
|
||||
ti,hwmods = "mailbox";
|
||||
reg = <0x48094000 0x200>;
|
||||
interrupts = <26>;
|
||||
ti,mbox-num-users = <2>;
|
||||
ti,mbox-num-fifos = <2>;
|
||||
mbox_dsp: dsp {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
mcspi1: spi@48098000 {
|
||||
compatible = "ti,omap2-mcspi";
|
||||
reg = <0x48098000 0x100>;
|
||||
interrupts = <65>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "mcspi1";
|
||||
ti,spi-num-cs = <4>;
|
||||
dmas = <&sdma 35>,
|
||||
<&sdma 36>,
|
||||
<&sdma 37>,
|
||||
<&sdma 38>,
|
||||
<&sdma 39>,
|
||||
<&sdma 40>,
|
||||
<&sdma 41>,
|
||||
<&sdma 42>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1",
|
||||
"tx2", "rx2", "tx3", "rx3";
|
||||
};
|
||||
|
||||
mcspi2: spi@4809a000 {
|
||||
compatible = "ti,omap2-mcspi";
|
||||
reg = <0x4809a000 0x100>;
|
||||
interrupts = <66>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "mcspi2";
|
||||
ti,spi-num-cs = <2>;
|
||||
dmas = <&sdma 43>,
|
||||
<&sdma 44>,
|
||||
<&sdma 45>,
|
||||
<&sdma 46>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1";
|
||||
};
|
||||
|
||||
mcspi3: spi@480b8000 {
|
||||
compatible = "ti,omap2-mcspi";
|
||||
reg = <0x480b8000 0x100>;
|
||||
interrupts = <91>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "mcspi3";
|
||||
ti,spi-num-cs = <2>;
|
||||
dmas = <&sdma 15>,
|
||||
<&sdma 16>,
|
||||
<&sdma 23>,
|
||||
<&sdma 24>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1";
|
||||
};
|
||||
|
||||
mcspi4: spi@480ba000 {
|
||||
compatible = "ti,omap2-mcspi";
|
||||
reg = <0x480ba000 0x100>;
|
||||
interrupts = <48>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "mcspi4";
|
||||
ti,spi-num-cs = <1>;
|
||||
dmas = <&sdma 70>, <&sdma 71>;
|
||||
dma-names = "tx0", "rx0";
|
||||
};
|
||||
|
||||
hdqw1w: 1w@480b2000 {
|
||||
compatible = "ti,omap3-1w";
|
||||
reg = <0x480b2000 0x1000>;
|
||||
interrupts = <58>;
|
||||
ti,hwmods = "hdq1w";
|
||||
};
|
||||
|
||||
mmc1: mmc@4809c000 {
|
||||
compatible = "ti,omap3-hsmmc";
|
||||
reg = <0x4809c000 0x200>;
|
||||
interrupts = <83>;
|
||||
ti,hwmods = "mmc1";
|
||||
ti,dual-volt;
|
||||
dmas = <&sdma 61>, <&sdma 62>;
|
||||
dma-names = "tx", "rx";
|
||||
pbias-supply = <&pbias_mmc_reg>;
|
||||
};
|
||||
|
||||
mmc2: mmc@480b4000 {
|
||||
compatible = "ti,omap3-hsmmc";
|
||||
reg = <0x480b4000 0x200>;
|
||||
interrupts = <86>;
|
||||
ti,hwmods = "mmc2";
|
||||
dmas = <&sdma 47>, <&sdma 48>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
mmc3: mmc@480ad000 {
|
||||
compatible = "ti,omap3-hsmmc";
|
||||
reg = <0x480ad000 0x200>;
|
||||
interrupts = <94>;
|
||||
ti,hwmods = "mmc3";
|
||||
dmas = <&sdma 77>, <&sdma 78>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
mmu_isp: mmu@480bd400 {
|
||||
compatible = "ti,omap2-iommu";
|
||||
reg = <0x480bd400 0x80>;
|
||||
interrupts = <24>;
|
||||
ti,hwmods = "mmu_isp";
|
||||
ti,#tlb-entries = <8>;
|
||||
};
|
||||
|
||||
mmu_iva: mmu@5d000000 {
|
||||
compatible = "ti,omap2-iommu";
|
||||
reg = <0x5d000000 0x80>;
|
||||
interrupts = <28>;
|
||||
ti,hwmods = "mmu_iva";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt2: wdt@48314000 {
|
||||
compatible = "ti,omap3-wdt";
|
||||
reg = <0x48314000 0x80>;
|
||||
ti,hwmods = "wd_timer2";
|
||||
};
|
||||
|
||||
mcbsp1: mcbsp@48074000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x48074000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <16>, /* OCP compliant interrupt */
|
||||
<59>, /* TX interrupt */
|
||||
<60>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp1";
|
||||
dmas = <&sdma 31>,
|
||||
<&sdma 32>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcbsp2: mcbsp@49022000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x49022000 0xff>,
|
||||
<0x49028000 0xff>;
|
||||
reg-names = "mpu", "sidetone";
|
||||
interrupts = <17>, /* OCP compliant interrupt */
|
||||
<62>, /* TX interrupt */
|
||||
<63>, /* RX interrupt */
|
||||
<4>; /* Sidetone */
|
||||
interrupt-names = "common", "tx", "rx", "sidetone";
|
||||
ti,buffer-size = <1280>;
|
||||
ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
|
||||
dmas = <&sdma 33>,
|
||||
<&sdma 34>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcbsp3: mcbsp@49024000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x49024000 0xff>,
|
||||
<0x4902a000 0xff>;
|
||||
reg-names = "mpu", "sidetone";
|
||||
interrupts = <22>, /* OCP compliant interrupt */
|
||||
<89>, /* TX interrupt */
|
||||
<90>, /* RX interrupt */
|
||||
<5>; /* Sidetone */
|
||||
interrupt-names = "common", "tx", "rx", "sidetone";
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
|
||||
dmas = <&sdma 17>,
|
||||
<&sdma 18>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcbsp4: mcbsp@49026000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x49026000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <23>, /* OCP compliant interrupt */
|
||||
<54>, /* TX interrupt */
|
||||
<55>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp4";
|
||||
dmas = <&sdma 19>,
|
||||
<&sdma 20>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcbsp5: mcbsp@48096000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x48096000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <27>, /* OCP compliant interrupt */
|
||||
<81>, /* TX interrupt */
|
||||
<82>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp5";
|
||||
dmas = <&sdma 21>,
|
||||
<&sdma 22>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sham: sham@480c3000 {
|
||||
compatible = "ti,omap3-sham";
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x480c3000 0x64>;
|
||||
interrupts = <49>;
|
||||
};
|
||||
|
||||
smartreflex_core: smartreflex@480cb000 {
|
||||
compatible = "ti,omap3-smartreflex-core";
|
||||
ti,hwmods = "smartreflex_core";
|
||||
reg = <0x480cb000 0x400>;
|
||||
interrupts = <19>;
|
||||
};
|
||||
|
||||
smartreflex_mpu_iva: smartreflex@480c9000 {
|
||||
compatible = "ti,omap3-smartreflex-iva";
|
||||
ti,hwmods = "smartreflex_mpu_iva";
|
||||
reg = <0x480c9000 0x400>;
|
||||
interrupts = <18>;
|
||||
};
|
||||
|
||||
timer1: timer@48318000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x48318000 0x400>;
|
||||
interrupts = <37>;
|
||||
ti,hwmods = "timer1";
|
||||
ti,timer-alwon;
|
||||
};
|
||||
|
||||
timer2: timer@49032000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x49032000 0x400>;
|
||||
interrupts = <38>;
|
||||
ti,hwmods = "timer2";
|
||||
};
|
||||
|
||||
timer3: timer@49034000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x49034000 0x400>;
|
||||
interrupts = <39>;
|
||||
ti,hwmods = "timer3";
|
||||
};
|
||||
|
||||
timer4: timer@49036000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x49036000 0x400>;
|
||||
interrupts = <40>;
|
||||
ti,hwmods = "timer4";
|
||||
};
|
||||
|
||||
timer5: timer@49038000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x49038000 0x400>;
|
||||
interrupts = <41>;
|
||||
ti,hwmods = "timer5";
|
||||
ti,timer-dsp;
|
||||
};
|
||||
|
||||
timer6: timer@4903a000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x4903a000 0x400>;
|
||||
interrupts = <42>;
|
||||
ti,hwmods = "timer6";
|
||||
ti,timer-dsp;
|
||||
};
|
||||
|
||||
timer7: timer@4903c000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x4903c000 0x400>;
|
||||
interrupts = <43>;
|
||||
ti,hwmods = "timer7";
|
||||
ti,timer-dsp;
|
||||
};
|
||||
|
||||
timer8: timer@4903e000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x4903e000 0x400>;
|
||||
interrupts = <44>;
|
||||
ti,hwmods = "timer8";
|
||||
ti,timer-pwm;
|
||||
ti,timer-dsp;
|
||||
};
|
||||
|
||||
timer9: timer@49040000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x49040000 0x400>;
|
||||
interrupts = <45>;
|
||||
ti,hwmods = "timer9";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer10: timer@48086000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x48086000 0x400>;
|
||||
interrupts = <46>;
|
||||
ti,hwmods = "timer10";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer11: timer@48088000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x48088000 0x400>;
|
||||
interrupts = <47>;
|
||||
ti,hwmods = "timer11";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer12: timer@48304000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x48304000 0x400>;
|
||||
interrupts = <95>;
|
||||
ti,hwmods = "timer12";
|
||||
ti,timer-alwon;
|
||||
ti,timer-secure;
|
||||
};
|
||||
|
||||
usbhstll: usbhstll@48062000 {
|
||||
compatible = "ti,usbhs-tll";
|
||||
reg = <0x48062000 0x1000>;
|
||||
interrupts = <78>;
|
||||
ti,hwmods = "usb_tll_hs";
|
||||
};
|
||||
|
||||
usbhshost: usbhshost@48064000 {
|
||||
compatible = "ti,usbhs-host";
|
||||
reg = <0x48064000 0x400>;
|
||||
ti,hwmods = "usb_host_hs";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbhsohci: ohci@48064400 {
|
||||
compatible = "ti,ohci-omap3";
|
||||
reg = <0x48064400 0x400>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <76>;
|
||||
};
|
||||
|
||||
usbhsehci: ehci@48064800 {
|
||||
compatible = "ti,ehci-omap";
|
||||
reg = <0x48064800 0x400>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <77>;
|
||||
};
|
||||
};
|
||||
|
||||
gpmc: gpmc@6e000000 {
|
||||
compatible = "ti,omap3430-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
reg = <0x6e000000 0x02d0>;
|
||||
interrupts = <20>;
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
usb_otg_hs: usb_otg_hs@480ab000 {
|
||||
compatible = "ti,omap3-musb";
|
||||
reg = <0x480ab000 0x1000>;
|
||||
interrupts = <92>, <93>;
|
||||
interrupt-names = "mc", "dma";
|
||||
ti,hwmods = "usb_otg_hs";
|
||||
multipoint = <1>;
|
||||
num-eps = <16>;
|
||||
ram-bits = <12>;
|
||||
};
|
||||
|
||||
dss: dss@48050000 {
|
||||
compatible = "ti,omap3-dss";
|
||||
reg = <0x48050000 0x200>;
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_core";
|
||||
clocks = <&dss1_alwon_fck>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dispc@48050400 {
|
||||
compatible = "ti,omap3-dispc";
|
||||
reg = <0x48050400 0x400>;
|
||||
interrupts = <25>;
|
||||
ti,hwmods = "dss_dispc";
|
||||
clocks = <&dss1_alwon_fck>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
dsi: encoder@4804fc00 {
|
||||
compatible = "ti,omap3-dsi";
|
||||
reg = <0x4804fc00 0x200>,
|
||||
<0x4804fe00 0x40>,
|
||||
<0x4804ff00 0x20>;
|
||||
reg-names = "proto", "phy", "pll";
|
||||
interrupts = <25>;
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_dsi1";
|
||||
clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
|
||||
clock-names = "fck", "sys_clk";
|
||||
};
|
||||
|
||||
rfbi: encoder@48050800 {
|
||||
compatible = "ti,omap3-rfbi";
|
||||
reg = <0x48050800 0x100>;
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_rfbi";
|
||||
clocks = <&dss1_alwon_fck>, <&dss_ick>;
|
||||
clock-names = "fck", "ick";
|
||||
};
|
||||
|
||||
venc: encoder@48050c00 {
|
||||
compatible = "ti,omap3-venc";
|
||||
reg = <0x48050c00 0x100>;
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_venc";
|
||||
clocks = <&dss_tv_fck>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
|
||||
ssi: ssi-controller@48058000 {
|
||||
compatible = "ti,omap3-ssi";
|
||||
ti,hwmods = "ssi";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
reg = <0x48058000 0x1000>,
|
||||
<0x48059000 0x1000>;
|
||||
reg-names = "sys",
|
||||
"gdd";
|
||||
|
||||
interrupts = <71>;
|
||||
interrupt-names = "gdd_mpu";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
ssi_port1: ssi-port@4805a000 {
|
||||
compatible = "ti,omap3-ssi-port";
|
||||
|
||||
reg = <0x4805a000 0x800>,
|
||||
<0x4805a800 0x800>;
|
||||
reg-names = "tx",
|
||||
"rx";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <67>,
|
||||
<68>;
|
||||
};
|
||||
|
||||
ssi_port2: ssi-port@4805b000 {
|
||||
compatible = "ti,omap3-ssi-port";
|
||||
|
||||
reg = <0x4805b000 0x800>,
|
||||
<0x4805b800 0x800>;
|
||||
reg-names = "tx",
|
||||
"rx";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <69>,
|
||||
<70>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "omap3xxx-clocks.dtsi"
|
||||
268
src/data/dts/omap34xx-omap36xx-clocks.dtsi
Normal file
268
src/data/dts/omap34xx-omap36xx-clocks.dtsi
Normal file
@ -0,0 +1,268 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP34XX/OMAP36XX clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&cm_clocks {
|
||||
security_l4_ick2: security_l4_ick2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
aes1_ick: aes1_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0a14>;
|
||||
};
|
||||
|
||||
rng_ick: rng_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
sha11_ick: sha11_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
des1_ick: des1_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
cam_mclk: cam_mclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll4_m5x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0f00>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
cam_ick: cam_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x0f10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
csi2_96m_fck: csi2_96m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0f00>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
security_l3_ick: security_l3_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l3_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pka_ick: pka_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l3_ick>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
icr_ick: icr_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <29>;
|
||||
};
|
||||
|
||||
des2_ick: des2_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <26>;
|
||||
};
|
||||
|
||||
mspro_ick: mspro_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
|
||||
mailboxes_ick: mailboxes_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sr1_fck: sr1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0c00>;
|
||||
ti,bit-shift = <6>;
|
||||
};
|
||||
|
||||
sr2_fck: sr2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0c00>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
|
||||
sr_l4_ick: sr_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll2_fck: dpll2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <19>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x0040>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll2_ck: dpll2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-clock";
|
||||
clocks = <&sys_ck>, <&dpll2_fck>;
|
||||
reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
|
||||
ti,low-power-stop;
|
||||
ti,lock;
|
||||
ti,low-power-bypass;
|
||||
};
|
||||
|
||||
dpll2_m2_ck: dpll2_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0044>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
iva2_ck: iva2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&dpll2_m2_ck>;
|
||||
reg = <0x0000>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
modem_fck: modem_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <31>;
|
||||
};
|
||||
|
||||
sad2d_ick: sad2d_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
mad2d_ick: mad2d_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0a18>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
mspro_fck: mspro_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
cam_clkdm: cam_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&cam_ick>, <&csi2_96m_fck>;
|
||||
};
|
||||
|
||||
iva2_clkdm: iva2_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&iva2_ck>;
|
||||
};
|
||||
|
||||
dpll2_clkdm: dpll2_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll2_ck>;
|
||||
};
|
||||
|
||||
wkup_clkdm: wkup_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
|
||||
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
|
||||
<&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
|
||||
};
|
||||
|
||||
d2d_clkdm: d2d_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
|
||||
<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
|
||||
<&mspro_fck>;
|
||||
};
|
||||
};
|
||||
242
src/data/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
Normal file
242
src/data/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
Normal file
@ -0,0 +1,242 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&prm_clocks {
|
||||
corex2_d3_fck: corex2_d3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <3>;
|
||||
};
|
||||
|
||||
corex2_d5_fck: corex2_d5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <5>;
|
||||
};
|
||||
};
|
||||
&cm_clocks {
|
||||
dpll5_ck: dpll5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-clock";
|
||||
clocks = <&sys_ck>, <&sys_ck>;
|
||||
reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
|
||||
ti,low-power-stop;
|
||||
ti,lock;
|
||||
};
|
||||
|
||||
dpll5_m2_ck: dpll5_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll5_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0d50>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
sgx_gate_fck: sgx_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0b00>;
|
||||
};
|
||||
|
||||
core_d3_ck: core_d3_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <3>;
|
||||
};
|
||||
|
||||
core_d4_ck: core_d4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
core_d6_ck: core_d6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <6>;
|
||||
};
|
||||
|
||||
omap_192m_alwon_fck: omap_192m_alwon_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll4_m2x2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
core_d2_ck: core_d2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&core_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
sgx_mux_fck: sgx_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
|
||||
reg = <0x0b40>;
|
||||
};
|
||||
|
||||
sgx_fck: sgx_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
|
||||
};
|
||||
|
||||
sgx_ick: sgx_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0b10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
cpefuse_fck: cpefuse_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0a08>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
ts_fck: ts_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&omap_32k_fck>;
|
||||
reg = <0x0a08>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
usbtll_fck: usbtll_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
reg = <0x0a08>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
usbtll_ick: usbtll_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a18>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
mmchs3_ick: mmchs3_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
|
||||
mmchs3_fck: mmchs3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
|
||||
dss1_alwon_fck: dss1_alwon_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0e00>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dss_ick: dss_ick_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dss-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x0e10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usbhost_120m_fck: usbhost_120m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
reg = <0x1400>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
usbhost_48m_fck: usbhost_48m_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&omap_48m_fck>;
|
||||
reg = <0x1400>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usbhost_ick: usbhost_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dss-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x1410>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
dpll5_clkdm: dpll5_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll5_ck>;
|
||||
};
|
||||
|
||||
sgx_clkdm: sgx_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sgx_ick>;
|
||||
};
|
||||
|
||||
dss_clkdm: dss_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
|
||||
<&dss1_alwon_fck>, <&dss_ick>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
||||
<&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
|
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
|
||||
};
|
||||
|
||||
usbhost_clkdm: usbhost_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
|
||||
<&usbhost_ick>;
|
||||
};
|
||||
};
|
||||
110
src/data/dts/omap36xx-clocks.dtsi
Normal file
110
src/data/dts/omap36xx-clocks.dtsi
Normal file
@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP36xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&cm_clocks {
|
||||
dpll4_ck: dpll4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-dpll-per-j-type-clock";
|
||||
clocks = <&sys_ck>, <&sys_ck>;
|
||||
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
|
||||
};
|
||||
|
||||
dpll4_m5x2_ck: dpll4_m5x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m5x2_mul_ck>;
|
||||
ti,bit-shift = <0x1e>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-rate-parent;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll4_m2x2_ck: dpll4_m2x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m2x2_mul_ck>;
|
||||
ti,bit-shift = <0x1b>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll3_m3x2_ck: dpll3_m3x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll3_m3x2_mul_ck>;
|
||||
ti,bit-shift = <0xc>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll4_m3x2_ck: dpll4_m3x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m3x2_mul_ck>;
|
||||
ti,bit-shift = <0x1c>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
dpll4_m6x2_ck: dpll4_m6x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m6x2_mul_ck>;
|
||||
ti,bit-shift = <0x1f>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
uart4_fck: uart4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&per_48m_fck>;
|
||||
reg = <0x1000>;
|
||||
ti,bit-shift = <18>;
|
||||
};
|
||||
};
|
||||
|
||||
&dpll4_m2x2_mul_ck {
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
&dpll4_m3x2_mul_ck {
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
&dpll4_m4x2_mul_ck {
|
||||
ti,clock-mult = <1>;
|
||||
};
|
||||
|
||||
&dpll4_m5x2_mul_ck {
|
||||
ti,clock-mult = <1>;
|
||||
};
|
||||
|
||||
&dpll4_m6x2_mul_ck {
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
dpll4_clkdm: dpll4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll4_ck>;
|
||||
};
|
||||
|
||||
per_clkdm: per_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
|
||||
<&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
|
||||
<&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
|
||||
<&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
|
||||
<&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
|
||||
<&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
|
||||
<&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
|
||||
<&mcbsp4_ick>, <&uart4_fck>;
|
||||
};
|
||||
};
|
||||
198
src/data/dts/omap36xx-omap3430es2plus-clocks.dtsi
Normal file
198
src/data/dts/omap36xx-omap3430es2plus-clocks.dtsi
Normal file
@ -0,0 +1,198 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP34xx/OMAP36xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&cm_clocks {
|
||||
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0a00>;
|
||||
};
|
||||
|
||||
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
|
||||
ssi_ssr_fck: ssi_ssr_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
|
||||
};
|
||||
|
||||
ssi_sst_fck: ssi_sst_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&ssi_ssr_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-hsotgusb-interface-clock";
|
||||
clocks = <&core_l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&l4_ick>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ssi_ick: ssi_ick_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-ssi-interface-clock";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usim_gate_fck: usim_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
ti,bit-shift = <9>;
|
||||
reg = <0x0c00>;
|
||||
};
|
||||
|
||||
sys_d2_ck: sys_d2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
omap_96m_d2_fck: omap_96m_d2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
omap_96m_d4_fck: omap_96m_d4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
omap_96m_d8_fck: omap_96m_d8_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
omap_96m_d10_fck: omap_96m_d10_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <10>;
|
||||
};
|
||||
|
||||
dpll5_m2_d4_ck: dpll5_m2_d4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
dpll5_m2_d8_ck: dpll5_m2_d8_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
dpll5_m2_d16_ck: dpll5_m2_d16_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <16>;
|
||||
};
|
||||
|
||||
dpll5_m2_d20_ck: dpll5_m2_d20_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll5_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <20>;
|
||||
};
|
||||
|
||||
usim_mux_fck: usim_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0c40>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
usim_fck: usim_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
|
||||
};
|
||||
|
||||
usim_ick: usim_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&wkup_l4_ick>;
|
||||
reg = <0x0c10>;
|
||||
ti,bit-shift = <9>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
core_l3_clkdm: core_l3_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
|
||||
};
|
||||
|
||||
wkup_clkdm: wkup_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
|
||||
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
|
||||
<&gpt1_ick>, <&usim_ick>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
|
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
|
||||
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
||||
<&ssi_ick>;
|
||||
};
|
||||
};
|
||||
95
src/data/dts/omap36xx.dtsi
Normal file
95
src/data/dts/omap36xx.dtsi
Normal file
@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP3 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include "omap3.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
/* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
|
||||
cpu@0 {
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
300000 1012500
|
||||
600000 1200000
|
||||
800000 1325000
|
||||
>;
|
||||
clock-latency = <300000>; /* From legacy driver */
|
||||
};
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart4: serial@49042000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
reg = <0x49042000 0x400>;
|
||||
interrupts = <80>;
|
||||
dmas = <&sdma 81 &sdma 82>;
|
||||
dma-names = "tx", "rx";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
abb_mpu_iva: regulator-abb-mpu {
|
||||
compatible = "ti,abb-v1";
|
||||
regulator-name = "abb_mpu_iva";
|
||||
#address-cell = <0>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x483072f0 0x8>, <0x48306818 0x4>;
|
||||
reg-names = "base-address", "int-address";
|
||||
ti,tranxdone-status-mask = <0x4000000>;
|
||||
clocks = <&sys_ck>;
|
||||
ti,settling-time = <30>;
|
||||
ti,clock-cycles = <8>;
|
||||
ti,abb_info = <
|
||||
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
||||
1012500 0 0 0 0 0
|
||||
1200000 0 0 0 0 0
|
||||
1325000 0 0 0 0 0
|
||||
1375000 1 0 0 0 0
|
||||
>;
|
||||
};
|
||||
|
||||
omap3_pmx_core2: pinmux@480025a0 {
|
||||
compatible = "ti,omap3-padconf", "pinctrl-single";
|
||||
reg = <0x480025a0 0x5c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0xff1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* OMAP3630 needs dss_96m_fck for VENC */
|
||||
&venc {
|
||||
clocks = <&dss_tv_fck>, <&dss_96m_fck>;
|
||||
clock-names = "fck", "tv_dac_clk";
|
||||
};
|
||||
|
||||
&ssi {
|
||||
status = "ok";
|
||||
|
||||
clocks = <&ssi_ssr_fck>,
|
||||
<&ssi_sst_fck>,
|
||||
<&ssi_ick>;
|
||||
clock-names = "ssi_ssr_fck",
|
||||
"ssi_sst_fck",
|
||||
"ssi_ick";
|
||||
};
|
||||
|
||||
/include/ "omap34xx-omap36xx-clocks.dtsi"
|
||||
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
|
||||
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
|
||||
/include/ "omap36xx-clocks.dtsi"
|
||||
1664
src/data/dts/omap3xxx-clocks.dtsi
Normal file
1664
src/data/dts/omap3xxx-clocks.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
161
src/data/dts/twl4030.dtsi
Normal file
161
src/data/dts/twl4030.dtsi
Normal file
@ -0,0 +1,161 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Integrated Power Management Chip
|
||||
*/
|
||||
&twl {
|
||||
compatible = "ti,twl4030";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
rtc {
|
||||
compatible = "ti,twl4030-rtc";
|
||||
interrupts = <11>;
|
||||
};
|
||||
|
||||
charger: bci {
|
||||
compatible = "ti,twl4030-bci";
|
||||
interrupts = <9>, <2>;
|
||||
bci3v1-supply = <&vusb3v1>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "ti,twl4030-wdt";
|
||||
};
|
||||
|
||||
vaux1: regulator-vaux1 {
|
||||
compatible = "ti,twl4030-vaux1";
|
||||
};
|
||||
|
||||
vaux2: regulator-vaux2 {
|
||||
compatible = "ti,twl4030-vaux2";
|
||||
};
|
||||
|
||||
vaux3: regulator-vaux3 {
|
||||
compatible = "ti,twl4030-vaux3";
|
||||
};
|
||||
|
||||
vaux4: regulator-vaux4 {
|
||||
compatible = "ti,twl4030-vaux4";
|
||||
};
|
||||
|
||||
vcc: regulator-vdd1 {
|
||||
compatible = "ti,twl4030-vdd1";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
};
|
||||
|
||||
vdac: regulator-vdac {
|
||||
compatible = "ti,twl4030-vdac";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vio: regulator-vio {
|
||||
compatible = "ti,twl4030-vio";
|
||||
};
|
||||
|
||||
vintana1: regulator-vintana1 {
|
||||
compatible = "ti,twl4030-vintana1";
|
||||
};
|
||||
|
||||
vintana2: regulator-vintana2 {
|
||||
compatible = "ti,twl4030-vintana2";
|
||||
};
|
||||
|
||||
vintdig: regulator-vintdig {
|
||||
compatible = "ti,twl4030-vintdig";
|
||||
};
|
||||
|
||||
vmmc1: regulator-vmmc1 {
|
||||
compatible = "ti,twl4030-vmmc1";
|
||||
regulator-min-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
};
|
||||
|
||||
vmmc2: regulator-vmmc2 {
|
||||
compatible = "ti,twl4030-vmmc2";
|
||||
regulator-min-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
};
|
||||
|
||||
vusb1v5: regulator-vusb1v5 {
|
||||
compatible = "ti,twl4030-vusb1v5";
|
||||
};
|
||||
|
||||
vusb1v8: regulator-vusb1v8 {
|
||||
compatible = "ti,twl4030-vusb1v8";
|
||||
};
|
||||
|
||||
vusb3v1: regulator-vusb3v1 {
|
||||
compatible = "ti,twl4030-vusb3v1";
|
||||
};
|
||||
|
||||
vpll1: regulator-vpll1 {
|
||||
compatible = "ti,twl4030-vpll1";
|
||||
};
|
||||
|
||||
vpll2: regulator-vpll2 {
|
||||
compatible = "ti,twl4030-vpll2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vsim: regulator-vsim {
|
||||
compatible = "ti,twl4030-vsim";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
twl_gpio: gpio {
|
||||
compatible = "ti,twl4030-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
usb2_phy: twl4030-usb {
|
||||
compatible = "ti,twl4030-usb";
|
||||
interrupts = <10>, <4>;
|
||||
usb1v5-supply = <&vusb1v5>;
|
||||
usb1v8-supply = <&vusb1v8>;
|
||||
usb3v1-supply = <&vusb3v1>;
|
||||
usb_mode = <1>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
twl_pwm: pwm {
|
||||
compatible = "ti,twl4030-pwm";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
twl_pwmled: pwmled {
|
||||
compatible = "ti,twl4030-pwmled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
twl_pwrbutton: pwrbutton {
|
||||
compatible = "ti,twl4030-pwrbutton";
|
||||
interrupts = <8>;
|
||||
};
|
||||
|
||||
twl_keypad: keypad {
|
||||
compatible = "ti,twl4030-keypad";
|
||||
interrupts = <1>;
|
||||
keypad,num-rows = <8>;
|
||||
keypad,num-columns = <8>;
|
||||
};
|
||||
|
||||
twl_madc: madc {
|
||||
compatible = "ti,twl4030-madc";
|
||||
interrupts = <3>;
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
42
src/data/dts/twl4030_omap3.dtsi
Normal file
42
src/data/dts/twl4030_omap3.dtsi
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Linaro, Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&twl {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&twl4030_pins &twl4030_vpins>;
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
/*
|
||||
* On most OMAP3 platforms, the twl4030 IRQ line is connected
|
||||
* to the SYS_NIRQ line on OMAP. Therefore, configure the
|
||||
* defaults for the SYS_NIRQ pin here.
|
||||
*/
|
||||
twl4030_pins: pinmux_twl4030_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* If your board is not using the I2C4 pins with twl4030, then don't include
|
||||
* this file. For proper idle mode signaling with sys_clkreq and sys_off_mode
|
||||
* pins we need to configure I2C4, or else use the legacy sys_nvmode1 and
|
||||
* sys_nvmode2 signaling.
|
||||
*/
|
||||
&omap3_pmx_wkup {
|
||||
twl4030_vpins: pinmux_twl4030_vpins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */
|
||||
OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */
|
||||
OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */
|
||||
OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user