changed codec detection and special ICH4 handling
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@793 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
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1ddfa2f84e
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@ -29,6 +29,7 @@
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#include <stdio.h>
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#include <stdio.h>
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#include <MediaDefs.h>
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#include <MediaDefs.h>
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#include "ac97.h"
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#include "ac97.h"
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#include "config.h"
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//#define DEBUG 1
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//#define DEBUG 1
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@ -114,20 +115,20 @@ ac97_amp_enable(bool yesno)
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{
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{
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LOG(("using Cirrus enable"));
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LOG(("using Cirrus enable"));
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if (yesno)
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if (yesno)
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ich_codec_write(0x68, 0x8004);
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ich_codec_write(config->codecoffset + 0x68, 0x8004);
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else
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else
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ich_codec_write(0x68, 0);
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ich_codec_write(config->codecoffset + 0x68, 0);
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break;
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break;
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}
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}
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default:
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default:
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{
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{
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LOG(("powerdown register was = %#04x\n",ich_codec_read(AC97_POWERDOWN)));
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LOG(("powerdown register was = %#04x\n",ich_codec_read(config->codecoffset + AC97_POWERDOWN)));
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if (yesno)
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if (yesno)
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ich_codec_write(AC97_POWERDOWN, ich_codec_read(AC97_POWERDOWN) & ~0x8000); /* switch on (low active) */
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ich_codec_write(config->codecoffset + AC97_POWERDOWN, ich_codec_read(AC97_POWERDOWN) & ~0x8000); /* switch on (low active) */
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else
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else
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ich_codec_write(AC97_POWERDOWN, ich_codec_read(AC97_POWERDOWN) | 0x8000); /* switch off */
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ich_codec_write(config->codecoffset + AC97_POWERDOWN, ich_codec_read(AC97_POWERDOWN) | 0x8000); /* switch off */
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LOG(("powerdown register is = %#04x\n",ich_codec_read(AC97_POWERDOWN)));
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LOG(("powerdown register is = %#04x\n",ich_codec_read(config->codecoffset + AC97_POWERDOWN)));
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break;
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break;
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}
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}
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}
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}
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@ -140,7 +141,7 @@ ac97_init()
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{
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{
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case 0x41445461: /* Analog Devices AD1886 */
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case 0x41445461: /* Analog Devices AD1886 */
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LOG(("using AD1886 init"));
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LOG(("using AD1886 init"));
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ich_codec_write(0x72, 0x0010);
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ich_codec_write(config->codecoffset + 0x72, 0x0010);
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break;
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break;
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default:
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default:
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break;
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break;
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@ -82,6 +82,7 @@ status_t probe_device(void)
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config->log_mbbar = 0;
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config->log_mbbar = 0;
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config->area_mmbar = -1;
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config->area_mmbar = -1;
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config->area_mbbar = -1;
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config->area_mbbar = -1;
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config->codecoffset = 0;
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result = B_ERROR;
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result = B_ERROR;
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cookie = 0;
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cookie = 0;
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@ -43,6 +43,7 @@ typedef struct
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void * log_mbbar; // ich4
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void * log_mbbar; // ich4
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area_id area_mmbar; // ich4
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area_id area_mmbar; // ich4
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area_id area_mbbar; // ich4
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area_id area_mbbar; // ich4
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uint32 codecoffset;
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} device_config;
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} device_config;
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extern device_config *config;
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extern device_config *config;
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@ -33,7 +33,8 @@ enum ICH_GLOBAL_REGISTER
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{
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{
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ICH_REG_GLOB_CNT = 0x2C,
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ICH_REG_GLOB_CNT = 0x2C,
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ICH_REG_GLOB_STA = 0x30,
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ICH_REG_GLOB_STA = 0x30,
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ICH_REG_ACC_SEMA = 0x34
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ICH_REG_ACC_SEMA = 0x34,
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ICH_REG_SDM = 0x80
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};
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};
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enum ICH_X_REGISTER_BASE /* base addresses for the following offsets */
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enum ICH_X_REGISTER_BASE /* base addresses for the following offsets */
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@ -94,10 +95,10 @@ enum REG_GLOB_STA_BITS
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STA_PIINT = 0x00000020, /* PCM In Interrupt */
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STA_PIINT = 0x00000020, /* PCM In Interrupt */
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STA_POINT = 0x00000040, /* PCM Out Interrupt */
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STA_POINT = 0x00000040, /* PCM Out Interrupt */
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STA_MINT = 0x00000080, /* Mic In Interrupt */
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STA_MINT = 0x00000080, /* Mic In Interrupt */
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STA_PCR = 0x00000100, /* AC_SDIN0 Codec Ready */
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STA_S0CR = 0x00000100, /* AC_SDIN0 Codec Ready */
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STA_SCR = 0x00000200, /* AC_SDIN1 Codec Ready */
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STA_S1CR = 0x00000200, /* AC_SDIN1 Codec Ready */
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STA_PRI = 0x00000400, /* AC_SDIN0 Resume Interrupt */
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STA_S0RI = 0x00000400, /* AC_SDIN0 Resume Interrupt */
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STA_SRI = 0x00000800, /* AC_SDIN1 Resume Interrupt */
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STA_S1RI = 0x00000800, /* AC_SDIN1 Resume Interrupt */
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STA_RCS = 0x00008000, /* Read Completition Status */
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STA_RCS = 0x00008000, /* Read Completition Status */
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STA_AD3 = 0x00010000,
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STA_AD3 = 0x00010000,
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STA_MD3 = 0x00020000,
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STA_MD3 = 0x00020000,
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@ -107,7 +108,7 @@ enum REG_GLOB_STA_BITS
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STA_BCS = 0x08000000, /* Bit Clock Stopped */
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STA_BCS = 0x08000000, /* Bit Clock Stopped */
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STA_S2CR = 0x10000000, /* AC_SDIN2 Codec Ready */
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STA_S2CR = 0x10000000, /* AC_SDIN2 Codec Ready */
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STA_S2RI = 0x20000000, /* AC_SDIN2 Resume Interrupt */
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STA_S2RI = 0x20000000, /* AC_SDIN2 Resume Interrupt */
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STA_INTMASK = (STA_MIINT | STA_MOINT | STA_PIINT | STA_POINT | STA_MINT | STA_PRI | STA_SRI | STA_M2INT | STA_P2INT | STA_SPINT | STA_S2RI)
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STA_INTMASK = (STA_MIINT | STA_MOINT | STA_PIINT | STA_POINT | STA_MINT | STA_S0RI | STA_S1RI | STA_M2INT | STA_P2INT | STA_SPINT | STA_S2RI)
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};
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};
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#define ICH_BD_COUNT 32
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#define ICH_BD_COUNT 32
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@ -337,6 +337,7 @@ init_driver(void)
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{
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{
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status_t rv;
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status_t rv;
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bigtime_t start;
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bigtime_t start;
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bool s0cr, s1cr, s2cr;
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LOG_CREATE();
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LOG_CREATE();
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@ -374,57 +375,87 @@ init_driver(void)
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LOG(("cold reset failed\n"));
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LOG(("cold reset failed\n"));
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}
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}
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/* wait until a codec is ready */
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/* detect which codecs are ready */
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s0cr = s1cr = s2cr = false;
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start = system_time();
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start = system_time();
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while ((system_time() - start) < 1000000) {
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do {
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rv = ich_reg_read_32(ICH_REG_GLOB_STA);
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rv = ich_reg_read_32(ICH_REG_GLOB_STA);
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if ((rv & STA_PCR) != 0)
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if (!s0cr && (rv & STA_S0CR)) {
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break;
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s0cr = true;
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LOG(("AC_SDIN0 codec ready after %Ld us\n",(system_time() - start)));
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}
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if (!s1cr && (rv & STA_S1CR)) {
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s1cr = true;
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LOG(("AC_SDIN1 codec ready after %Ld us\n",(system_time() - start)));
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}
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if (!s2cr && (rv & STA_S2CR)) {
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s2cr = true;
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LOG(("AC_SDIN2 codec ready after %Ld us\n",(system_time() - start)));
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}
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snooze(50000);
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snooze(50000);
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} while ((system_time() - start) < 1000000);
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if (!s0cr) {
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LOG(("AC_SDIN0 codec not ready\n"));
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}
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}
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if ((rv & STA_PCR)) {
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if (!s1cr) {
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LOG(("primary codec ready after %Ld us\n",(system_time() - start)));
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LOG(("AC_SDIN1 codec not ready\n"));
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} else {
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LOG(("primary codec not ready after %Ld us\n",(system_time() - start)));
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}
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}
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while ((system_time() - start) < 1000000) {
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if (!s2cr) {
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rv = ich_reg_read_32(ICH_REG_GLOB_STA);
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LOG(("AC_SDIN2 codec not ready\n"));
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if ((rv & STA_SCR) != 0)
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break;
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snooze(50000);
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}
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if ((rv & STA_SCR)) {
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LOG(("secondary codec ready after %Ld us\n",(system_time() - start)));
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} else {
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LOG(("secondary codec not ready after %Ld us\n",(system_time() - start)));
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}
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while ((system_time() - start) < 1000000) {
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rv = ich_reg_read_32(ICH_REG_GLOB_STA);
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if ((rv & STA_S2CR) != 0)
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break;
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snooze(50000);
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}
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if ((rv & STA_S2CR)) {
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LOG(("tertiary codec ready after %Ld us\n",(system_time() - start)));
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} else {
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LOG(("tertiary codec not ready after %Ld us\n",(system_time() - start)));
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}
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}
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dump_hardware_regs();
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dump_hardware_regs();
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if ((rv & (STA_PCR | STA_SCR | STA_S2CR)) == 0) {
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if (!s0cr && !s1cr && !s2cr) {
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PRINT(("compatible chipset found, but no codec ready!\n"));
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PRINT(("compatible chipset found, but no codec ready!\n"));
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unmap_io_memory();
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unmap_io_memory();
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return B_ERROR;
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return B_ERROR;
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}
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}
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if ((rv & STA_PCR) == 0 && (rv & STA_S2CR) != 0) {
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LOG(("using tertiary codec!\n"));
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if (config->type & TYPE_ICH4) {
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config->nambar += 0x100;
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/* we are using a ICH4 chipset, and assume that the codec beeing ready
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config->log_mmbar += 0x100; /* ICH 4 */
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* is the primary one.
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} else if ((rv & STA_PCR) == 0 && (rv & STA_SCR) != 0) {
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*/
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LOG(("using secondary codec!\n"));
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uint8 sdin;
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config->nambar += 0x80;
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uint16 reset;
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config->log_mmbar += 0x80; /* ICH 4 */
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uint8 id;
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reset = ich_codec_read(0x00); /* access the primary codec */
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if (reset == 0 || reset == 0xFFFF) {
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LOG(("primary codec not present\n"));
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} //else {
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sdin = 0x02 & ich_reg_read_8(ICH_REG_SDM);
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id = 0x02 & (ich_codec_read(0x00 + 0x28) >> 14);
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LOG(("primary codec id %d is connected to AC_SDIN%d\n", id, sdin));
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//}
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reset = ich_codec_read(0x80); /* access the secondary codec */
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if (reset == 0 || reset == 0xFFFF) {
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LOG(("secondary codec not present\n"));
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} //else {
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sdin = 0x02 & ich_reg_read_8(ICH_REG_SDM);
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id = 0x02 & (ich_codec_read(0x80 + 0x28) >> 14);
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LOG(("secondary codec id %d is connected to AC_SDIN%d\n", id, sdin));
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//}
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reset = ich_codec_read(0x100); /* access the tertiary codec */
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if (reset == 0 || reset == 0xFFFF) {
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LOG(("tertiary codec not present\n"));
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} //else {
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sdin = 0x02 & ich_reg_read_8(ICH_REG_SDM);
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id = 0x02 & (ich_codec_read(0x100 + 0x28) >> 14);
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LOG(("tertiary codec id %d is connected to AC_SDIN%d\n", id, sdin));
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//}
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/* XXX this may be wrong */
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ich_reg_write_8(ICH_REG_SDM, (ich_reg_read_8(ICH_REG_SDM) & 0x0F) | 0x08 | 0x90);
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} else {
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/* we are using a pre-ICH4 chipset, that has a fixed mapping of
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* AC_SDIN0 = primary, AC_SDIN1 = secondary codec.
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*/
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if (!s0cr && s2cr) {
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// is is unknown if this really works, perhaps we should better abort here
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LOG(("primary codec doesn't seem to be available, using secondary!\n"));
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config->codecoffset = 0x80;
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}
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}
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}
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dump_hardware_regs();
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dump_hardware_regs();
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@ -480,9 +511,9 @@ init_driver(void)
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chan_po->regbase = ICH_REG_PO_BASE;
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chan_po->regbase = ICH_REG_PO_BASE;
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chan_mc->regbase = ICH_REG_MC_BASE;
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chan_mc->regbase = ICH_REG_MC_BASE;
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/* reset the (primary?) codec */
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/* reset the codec */
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LOG(("codec reset\n"));
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LOG(("codec reset\n"));
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ich_codec_write(0x00, 0x0000);
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ich_codec_write(config->codecoffset + 0x00, 0x0000);
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snooze(50000); // 50 ms
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snooze(50000); // 50 ms
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ac97_init();
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ac97_init();
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@ -517,24 +548,24 @@ init_driver(void)
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}
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}
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/* enable master output */
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/* enable master output */
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ich_codec_write(0x02, 0x0000);
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ich_codec_write(config->codecoffset + 0x02, 0x0000);
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/* enable pcm output */
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/* enable pcm output */
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ich_codec_write(0x18, 0x0404);
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ich_codec_write(config->codecoffset + 0x18, 0x0404);
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#if 0
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#if 0
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/* enable pcm input */
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/* enable pcm input */
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ich_codec_write(0x10, 0x0000);
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ich_codec_write(config->codecoffset + 0x10, 0x0000);
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/* enable mic input */
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/* enable mic input */
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/* ich_codec_write(0x0E, 0x0000); */
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/* ich_codec_write(config->codecoffset + 0x0E, 0x0000); */
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/* select pcm input record */
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/* select pcm input record */
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ich_codec_write(0x1A, 4 | (4 << 8));
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ich_codec_write(config->codecoffset + 0x1A, 4 | (4 << 8));
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/* enable PCM record */
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/* enable PCM record */
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ich_codec_write(0x1C, 0x0000);
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ich_codec_write(config->codecoffset + 0x1C, 0x0000);
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/* enable mic record */
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/* enable mic record */
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/* ich_codec_write(0x1E, 0x0000); */
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/* ich_codec_write(config->codecoffset + 0x1E, 0x0000); */
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#endif
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#endif
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LOG(("init_driver finished!\n"));
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LOG(("init_driver finished!\n"));
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@ -615,9 +646,9 @@ int32 ich_int(void *unused)
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if ((sta & STA_INTMASK) == 0)
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if ((sta & STA_INTMASK) == 0)
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return B_UNHANDLED_INTERRUPT;
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return B_UNHANDLED_INTERRUPT;
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if (sta & (STA_PRI | STA_SRI)) {
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if (sta & (STA_S0RI | STA_S1RI | STA_S2RI)) {
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/* ignore and clear resume interrupt(s) */
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/* ignore and clear resume interrupt(s) */
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ich_reg_write_32(ICH_REG_GLOB_STA, sta & (STA_PRI | STA_SRI));
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ich_reg_write_32(ICH_REG_GLOB_STA, sta & (STA_S0RI | STA_S1RI | STA_S2RI));
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}
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}
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if (sta & STA_POINT) { // pcm-out
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if (sta & STA_POINT) { // pcm-out
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@ -30,7 +30,7 @@
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#include "hardware.h"
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#include "hardware.h"
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#define VERSION "Version 1.3, Copyright (c) 2002 Marcus Overhagen, compiled on " ## __DATE__ ## " " ## __TIME__
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#define VERSION "Version 1.4, Copyright (c) 2002 Marcus Overhagen, compiled on " ## __DATE__ ## " " ## __TIME__
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#define DRIVER_NAME "ich_ac97"
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#define DRIVER_NAME "ich_ac97"
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#define BUFFER_SIZE 2048
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#define BUFFER_SIZE 2048
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