intel_extreme: Some basic pipe cleanup
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e5494f1bb2
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32807945aa
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@ -94,9 +94,6 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
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return;
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}
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// Wait for the clocks to stabilize
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spin(150);
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// update timing (fPipeBase bumps the DISPLAY_A to B when needed)
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_HTOTAL),
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((uint32)(target->timing.h_total - 1) << 16)
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@ -118,24 +115,24 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
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((uint32)(target->timing.v_sync_end - 1) << 16)
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| ((uint32)target->timing.v_sync_start - 1));
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// XXX: Is it ok to do these on non-digital?
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_POS), 0);
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE),
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((uint32)(target->virtual_width - 1) << 16)
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| ((uint32)target->virtual_height - 1));
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_PIPE_SIZE),
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((uint32)(target->timing.v_display - 1) << 16)
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| ((uint32)target->timing.h_display - 1));
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// This is useful for debugging: it sets the border to red, so you
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// can see what is border and what is porch (black area around the
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// sync)
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//write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_RED), 0x00FF0000);
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// TODO: Review these
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE),
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((uint32)(target->virtual_width - 1) << 16)
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| ((uint32)target->virtual_height - 1));
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_PIPE_SIZE),
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((uint32)(target->timing.v_display - 1) << 16)
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| ((uint32)target->timing.h_display - 1));
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write32(portAddress, (read32(portAddress)
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& ~(DISPLAY_MONITOR_POLARITY_MASK
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| DISPLAY_MONITOR_VGA_POLARITY))
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// XXX: Is it ok to do this on non-analog?
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write32(portAddress, (read32(portAddress) & ~(DISPLAY_MONITOR_POLARITY_MASK
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| DISPLAY_MONITOR_VGA_POLARITY))
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| ((target->timing.flags & B_POSITIVE_HSYNC) != 0
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? DISPLAY_MONITOR_POSITIVE_HSYNC : 0)
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| ((target->timing.flags & B_POSITIVE_VSYNC) != 0
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@ -235,7 +232,8 @@ DisplayPipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
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pll |= DISPLAY_PLL_POST1_DIVIDE_2;
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}
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write32(pllControl, pll);
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// Allow the PLL to warm up by masking its bit.
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write32(pllControl, pll & ~DISPLAY_PLL_NO_VGA_CONTROL);
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read32(pllControl);
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spin(150);
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write32(pllControl, pll);
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@ -622,9 +622,6 @@ if (first) {
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TRACE("%s: Port configuration completed successfully!\n", __func__);
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// RIP DIGITAL / LVDS (strange..)
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// RIP ANALOG
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// We set the same color mode across all pipes
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program_pipe_color_modes(colorMode);
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@ -656,7 +653,10 @@ intel_get_display_mode(display_mode* _currentMode)
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{
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CALLED();
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retrieve_current_mode(*_currentMode, INTEL_DISPLAY_A_PLL);
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*_currentMode = gInfo->shared_info->current_mode;
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// This seems unreliable. We should always know the current_mode
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//retrieve_current_mode(*_currentMode, INTEL_DISPLAY_A_PLL);
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return B_OK;
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}
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