Patch from tqh, modified by myself: enable PCIe snooping through vendor specific registers (ATI and nVidia).
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@28838 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -48,6 +48,17 @@ static const struct {
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};
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static inline void
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update_pci_register(hda_controller* controller, uint8 reg, uint8 mask, uint8 value)
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{
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uint8 tmp = (gPci->read_pci_config)(controller->pci_info.bus,
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controller->pci_info.device, controller->pci_info.function, reg, 1);
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(gPci->write_pci_config)(controller->pci_info.bus,
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controller->pci_info.device, controller->pci_info.function,
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reg, 1, (tmp & mask) | value);
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}
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static inline rirb_t&
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current_rirb(hda_controller *controller)
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{
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@ -700,8 +711,7 @@ hda_hw_init(hda_controller* controller)
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{
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uint16 capabilities, stateStatus, cmd;
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status_t status;
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uint8 tcsel;
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/* Map MMIO registers */
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controller->regs_area = map_physical_memory("hda_hw_regs",
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(void*)controller->pci_info.u.h0.base_registers[0],
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@ -729,11 +739,22 @@ hda_hw_init(hda_controller* controller)
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goto no_irq;
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/* TCSEL is reset to TC0 (clear 0-2 bits) */
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tcsel = (gPci->read_pci_config)(controller->pci_info.bus,
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controller->pci_info.device, controller->pci_info.function, PCI_HDA_TCSEL, 1);
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(gPci->write_pci_config)(controller->pci_info.bus,
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controller->pci_info.device, controller->pci_info.function,
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PCI_HDA_TCSEL, 1, tcsel & 0xf8);
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update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0);
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/* Enable snooping for ATI and Nvidia, right now for all their hda-devices,
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but only based on guessing. */
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switch (controller->pci_info.vendor_id) {
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/* NVIDIA */
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case 0x10de:
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update_pci_register(controller, NVIDIA_HDA_TRANSREG,
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NVIDIA_HDA_TRANSREG_MASK, NVIDIA_HDA_ENABLE_COHBITS);
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break;
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/* ATI */
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case 0x1002:
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update_pci_register(controller, ATI_HDA_MISC_CNTR2,
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ATI_HDA_MISC_CNTR2_MASK, ATI_HDA_ENABLE_SNOOP);
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break;
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}
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capabilities = controller->Read16(HDAC_GLOBAL_CAP);
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controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities);
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@ -762,7 +783,7 @@ hda_hw_init(hda_controller* controller)
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dprintf("hda: init_corb_rirb_pos failed\n");
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goto corb_rirb_failed;
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}
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controller->Write16(HDAC_WAKE_ENABLE, 0x7fff);
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/* Enable controller interrupts */
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@ -133,6 +133,15 @@
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/* PCI space register definitions */
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#define PCI_HDA_TCSEL 0x44
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#define PCI_HDA_TCSEL_MASK 0xf8
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#define ATI_HDA_MISC_CNTR2 0x42
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#define ATI_HDA_MISC_CNTR2_MASK 0xf8
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#define ATI_HDA_ENABLE_SNOOP 0x02
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#define NVIDIA_HDA_TRANSREG 0x4e
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#define NVIDIA_HDA_TRANSREG_MASK 0xf0
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#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
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typedef uint32 corb_t;
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typedef struct {
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