* Ensuring that reading interrupt status register and disabling interrupts
is done only once. * Coding style cleanup. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34814 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -1070,7 +1070,7 @@ ipw_rx_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf)
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case IPW_STATE_DISABLED:
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/* XXX? is this right? */
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sc->flags &= ~(IPW_FLAG_HACK | IPW_FLAG_SCANNING |
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sc->flags &= ~(IPW_FLAG_HACK | IPW_FLAG_SCANNING |
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IPW_FLAG_ASSOCIATING | IPW_FLAG_ASSOCIATED);
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DPRINTFN(2, ("Firmware disabled (%s flags 0x%x)\n",
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IEEESTATE(vap), sc->flags));
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@ -1392,12 +1392,16 @@ ipw_intr(void *arg)
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IPW_LOCK(sc);
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#if !defined(__HAIKU__)
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r = CSR_READ_4(sc, IPW_CSR_INTR);
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if (r == 0 || r == 0xffffffff)
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goto done;
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/* disable interrupts */
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CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
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#else
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r = atomic_get((int32 *)&sc->sc_intr_status);
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#endif
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/* acknowledge all interrupts */
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CSR_WRITE_4(sc, IPW_CSR_INTR, r);
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@ -158,6 +158,10 @@ struct ipw_softc {
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struct ipw_rx_radiotap_header sc_rxtap;
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struct ipw_tx_radiotap_header sc_txtap;
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#if defined(__HAIKU__)
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uint32_t sc_intr_status;
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#endif
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};
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/*
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@ -20,6 +20,7 @@
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HAIKU_FBSD_WLAN_DRIVER_GLUE(iprowifi2100, ipw, pci)
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NO_HAIKU_FBSD_MII_DRIVER();
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NO_HAIKU_REENABLE_INTERRUPTS();
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HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_SWI_TASKQUEUE | FBSD_WLAN);
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HAIKU_FIRMWARE_VERSION(130);
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@ -29,28 +30,14 @@ HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev)
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{
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struct ipw_softc* sc = (struct ipw_softc*)device_get_softc(dev);
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uint32 r;
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HAIKU_INTR_REGISTER_STATE;
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HAIKU_INTR_REGISTER_ENTER();
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if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) {
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HAIKU_INTR_REGISTER_LEAVE();
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r = CSR_READ_4(sc, IPW_CSR_INTR);
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if (r == 0 || r == 0xffffffff)
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return 0;
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}
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/* disable interrupts */
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atomic_set((int32*)&sc->sc_intr_status, r);
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CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
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HAIKU_INTR_REGISTER_LEAVE();
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// disable interrupts
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return 1;
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}
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void
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HAIKU_REENABLE_INTERRUPTS(device_t dev)
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{
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struct ipw_softc* sc = (struct ipw_softc*)device_get_softc(dev);
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/* enable interrupts */
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CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
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}
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