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intel_extreme: Fix pll divisors on gen 3 cards

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* Likely a regression from my card generation rework
This commit is contained in:
Alexander von Gluck IV 2016-01-03 15:21:20 -06:00
parent af0dad4771
commit 2bf16c66b5
1 changed files with 2 additions and 3 deletions
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5
src/add-ons/accelerants/intel_extreme/Pipes.cpp
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@ -241,9 +241,7 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL | extraFlags;
if (gInfo->shared_info->device_type.Generation() >= 4
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
if (gInfo->shared_info->device_type.Generation() >= 3) {
// post1 divisor << 1 , 1-8
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
pll |= ((1 << (divisors.post1 - 1))
@ -269,6 +267,7 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
pll |= DISPLAY_PLL_2X_CLOCK;
// TODO: Is this supposed to be DISPLAY_PLL_IGD_POST1_DIVISOR_MASK??
if (divisors.post1 > 2) {
pll |= ((divisors.post1 - 2) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
& DISPLAY_PLL_POST1_DIVISOR_MASK;