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XHCI USB: Add port routing for Intel WildcatPoint LP USB. 

* from FreeBSD.
This commit is contained in:
Jérôme Duval 2015-11-23 20:47:15 +01:00
parent 95c8163a16
commit 2bc202c430
3 changed files with 38 additions and 25 deletions
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60
src/add-ons/kernel/busses/usb/xhci.cpp
View File

@ -240,31 +240,17 @@ XHCI::XHCI(pci_info *info, Stack *stack)
// On Intel's Panther Point and Lynx Point Chipset taking ownership
// of EHCI owned ports, is what we do here.
if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL
&& (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI
|| fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI
|| fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI
|| fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI
|| fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) {
TRACE("Intel xHC Controller\n");
TRACE("Looking for EHCI owned ports\n");
uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4);
TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports);
sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports);
ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4);
TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports);
ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4);
TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports);
sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports);
ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4);
TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports);
if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL) {
switch (fPCIInfo->device_id) {
case PCI_DEVICE_INTEL_PANTHER_POINT_XHCI:
case PCI_DEVICE_INTEL_LYNX_POINT_XHCI:
case PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI:
case PCI_DEVICE_INTEL_BAYTRAIL_XHCI:
case PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI:
case PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI:
_SwitchIntelPorts();
break;
}
}
// halt the host controller
@ -360,6 +346,30 @@ XHCI::~XHCI()
}
void
XHCI::_SwitchIntelPorts()
{
TRACE("Intel xHC Controller\n");
TRACE("Looking for EHCI owned ports\n");
uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4);
TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports);
sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports);
ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4);
TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports);
ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4);
TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports);
sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports);
ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4);
TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports);
}
status_t
XHCI::Start()
{

2
src/add-ons/kernel/busses/usb/xhci.h
View File

@ -196,6 +196,8 @@ private:
inline uint32 ReadDoorReg32(uint32 reg);
inline void WriteDoorReg32(uint32 reg, uint32 value);
void _SwitchIntelPorts();
static pci_module_info * sPCIModule;
static pci_x86_module_info *sPCIx86Module;

1
src/add-ons/kernel/busses/usb/xhci_hardware.h
View File

@ -17,6 +17,7 @@
#define PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 0x9c31
#define PCI_DEVICE_INTEL_BAYTRAIL_XHCI 0x0f35
#define PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI 0x8cb1
#define PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI 0x9cb1
// Intel quirks registers in PCI config
#define XHCI_INTEL_USB3PRM 0xdc // USB 3.0 Port Routing Mask