Work in progress on xHCI bus driver.
* added more traces, coding style
* added xhci_td, xhci_endpoint structs.
* SubmitRequest: this links a 3-stage TD control request into
the endpoint ring.
* _InsertEndpointForPipe: when a pipe is created, configure the
endpoint and set up the controller cookie.
* CreateDescriptor and FreeDescriptor: allocates memory for a TD.
* _LinkDescriptorForPipe: link a TD in an endpoint ring.
* _UnlinkDescriptorForPipe: unlink a TD
* AllocateDevice:
slot number zero isn't valid.
stick the slot number to the device struct.
configure the default endpoint before calling SetAddress.
address is found in the device context instead of the input context.
device address passed to the USB stack has to begin with 1.
* Ring:
check for invalid slot/endpoint combination.
ring the slot doorbell instead of the doorbell 0.
* Root hub: fixed USB version.
* HandleTransferComplete: finds out the TD which submitted a
transfer.
This commit is contained in:
Jérôme Duval
parent
319a3798bc
commit
2b31b4a88c
@ -12,7 +12,7 @@
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Device::Device(Object *parent, int8 hubAddress, uint8 hubPort,
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usb_device_descriptor &desc, int8 deviceAddress, usb_speed speed,
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bool isRootHub)
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bool isRootHub, void *controllerCookie)
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: Object(parent),
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fDeviceDescriptor(desc),
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fInitOK(false),
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@ -23,7 +23,8 @@ Device::Device(Object *parent, int8 hubAddress, uint8 hubPort,
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fSpeed(speed),
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fDeviceAddress(deviceAddress),
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fHubAddress(hubAddress),
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fHubPort(hubPort)
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fHubPort(hubPort),
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fControllerCookie(controllerCookie)
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{
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TRACE("creating device\n");
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@ -455,20 +456,20 @@ Device::InitEndpoints(int32 interfaceIndex)
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direction = Pipe::In;
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switch (endpoint->descr->attributes & 0x03) {
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case 0x00: /* Control Endpoint */
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case USB_ENDPOINT_ATTR_CONTROL: /* Control Endpoint */
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pipe = new(std::nothrow) ControlPipe(this);
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direction = Pipe::Default;
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break;
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case 0x01: /* Isochronous Endpoint */
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case USB_ENDPOINT_ATTR_ISOCHRONOUS: /* Isochronous Endpoint */
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pipe = new(std::nothrow) IsochronousPipe(this);
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break;
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case 0x02: /* Bulk Endpoint */
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case USB_ENDPOINT_ATTR_BULK: /* Bulk Endpoint */
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pipe = new(std::nothrow) BulkPipe(this);
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break;
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case 0x03: /* Interrupt Endpoint */
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case USB_ENDPOINT_ATTR_INTERRUPT: /* Interrupt Endpoint */
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pipe = new(std::nothrow) InterruptPipe(this);
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break;
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}
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@ -480,7 +480,8 @@ public:
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uint8 hubPort,
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usb_device_descriptor &desc,
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int8 deviceAddress,
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usb_speed speed, bool isRootHub);
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usb_speed speed, bool isRootHub,
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void *controllerCookie = NULL);
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virtual ~Device();
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status_t InitCheck();
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@ -535,6 +536,11 @@ virtual status_t BuildDeviceName(char *string,
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{ return fHubAddress; }
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uint8 HubPort() const { return fHubPort; }
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void SetControllerCookie(void *cookie)
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{ fControllerCookie = cookie; }
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void * ControllerCookie() const
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{ return fControllerCookie; }
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// Convenience functions for standard requests
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virtual status_t SetFeature(uint16 selector);
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virtual status_t ClearFeature(uint16 selector);
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@ -554,6 +560,7 @@ private:
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int8 fHubAddress;
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uint8 fHubPort;
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ControlPipe * fDefaultPipe;
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void * fControllerCookie;
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};
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@ -422,6 +422,55 @@ XHCI::SubmitTransfer(Transfer *transfer)
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Pipe *pipe = transfer->TransferPipe();
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if (pipe->Type() & USB_OBJECT_ISO_PIPE)
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return B_UNSUPPORTED;
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if (pipe->Type() & USB_OBJECT_CONTROL_PIPE)
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return SubmitRequest(transfer);
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return B_OK;
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}
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status_t
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XHCI::SubmitRequest(Transfer *transfer)
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{
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Pipe *pipe = transfer->TransferPipe();
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usb_request_data *requestData = transfer->RequestData();
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bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0;
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TRACE("SubmitRequest()\n");
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xhci_td *setupDescriptor = CreateDescriptor(sizeof(usb_request_data));
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// set SetupStage
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uint8 index = 0;
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setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8);
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setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_SETUP_STAGE)
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| TRB_3_IDT_BIT | TRB_3_CYCLE_BIT;
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if (requestData->Length > 0) {
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setupDescriptor->trbs[index].dwtrb3 |= directionIn ? TRB_3_TRT_IN
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: TRB_3_TRT_OUT;
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}
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memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData,
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sizeof(usb_request_data));
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index++;
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// set DataStage if any
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// set StatusStage
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setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0);
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setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_STATUS_STAGE)
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| (directionIn ? 0 : TRB_3_DIR_IN) | TRB_3_CYCLE_BIT | TRB_3_IOC_BIT;
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setupDescriptor->last_used = index;
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xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie();
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uint8 id = XHCI_ENDPOINT_ID(pipe);
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if (id >= XHCI_MAX_ENDPOINTS)
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return B_BAD_VALUE;
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setupDescriptor->transfer = transfer;
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_LinkDescriptorForPipe(setupDescriptor, endpoint);
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TRACE("SubmitRequest() request linked\n");
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Ring(endpoint->device->slot, id);
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return B_OK;
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}
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@ -440,11 +489,11 @@ XHCI::NotifyPipeChange(Pipe *pipe, usb_change change)
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TRACE("pipe change %d for pipe %p\n", change, pipe);
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switch (change) {
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case USB_CHANGE_CREATED:
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case USB_CHANGE_DESTROYED: {
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// ToDo: we should create and keep a single queue head
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// for all transfers to/from this pipe
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_InsertEndpointForPipe(pipe);
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break;
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case USB_CHANGE_DESTROYED:
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_RemoveEndpointForPipe(pipe);
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break;
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}
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case USB_CHANGE_PIPE_POLICY_CHANGED: {
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// ToDo: for isochronous pipes we might need to adapt to new
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@ -533,6 +582,52 @@ XHCI::AddTo(Stack *stack)
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}
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xhci_td *
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XHCI::CreateDescriptor(size_t bufferSize)
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{
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xhci_td *result;
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addr_t physicalAddress;
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if (fStack->AllocateChunk((void **)&result, (void**)&physicalAddress,
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sizeof(xhci_td)) < B_OK) {
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TRACE_ERROR("failed to allocate a transfer descriptor\n");
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return NULL;
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}
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result->this_phy = (addr_t)physicalAddress;
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result->buffer_size = bufferSize;
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if (bufferSize <= 0) {
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result->buffer_log = NULL;
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result->buffer_phy = 0;
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return result;
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}
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if (fStack->AllocateChunk(&result->buffer_log, (void **)&result->buffer_phy,
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bufferSize) < B_OK) {
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TRACE_ERROR("unable to allocate space for the buffer\n");
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fStack->FreeChunk(result, (void *)result->this_phy, sizeof(xhci_td));
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return NULL;
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}
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return result;
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}
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void
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XHCI::FreeDescriptor(xhci_td *descriptor)
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{
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if (!descriptor)
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return;
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if (descriptor->buffer_log) {
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fStack->FreeChunk(descriptor->buffer_log,
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(void *)descriptor->buffer_phy, descriptor->buffer_size);
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}
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fStack->FreeChunk(descriptor, (void *)descriptor->this_phy, sizeof(xhci_td));
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}
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Device *
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XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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usb_speed speed)
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@ -548,7 +643,7 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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return NULL;
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}
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if (slot > fSlotCount) {
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if (slot == 0 || slot > fSlotCount) {
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TRACE_ERROR("AllocateDevice() bad slot\n");
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return NULL;
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}
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@ -561,9 +656,11 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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struct xhci_device *device = &fDevices[slot];
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memset(device, 0, sizeof(struct xhci_device));
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device->state = XHCI_STATE_ENABLED;
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device->slot = slot;
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device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx,
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(void**)&device->input_ctx_addr, sizeof(*device->input_ctx), "XHCI input context");
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(void**)&device->input_ctx_addr, sizeof(*device->input_ctx),
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"XHCI input context");
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if (device->input_ctx_area < B_OK) {
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TRACE_ERROR("unable to create a input context area\n");
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return NULL;
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@ -587,6 +684,9 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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}
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device->input_ctx->slot.dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route);
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//device->input_ctx->slot.dwslot0 =
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// SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1) | SLOT_0_ROUTE(route);
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// add the speed
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switch (speed) {
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case USB_SPEED_LOWSPEED:
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@ -606,7 +706,7 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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break;
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}
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device->input_ctx->slot.dwslot1 = SLOT_1_RH_PORT(rhPort);
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device->input_ctx->slot.dwslot1 = SLOT_1_RH_PORT(rhPort); // TODO enable power save
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device->input_ctx->slot.dwslot2 = SLOT_2_IRQ_TARGET(0);
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if (0)
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device->input_ctx->slot.dwslot2 |= SLOT_2_PORT_NUM(hubPort);
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@ -664,18 +764,31 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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return NULL;
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}
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if (SetAddress(device->input_ctx_addr, 1, slot) != B_OK) {
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device->endpoints[0].device = device;
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device->endpoints[0].td_head = NULL;
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device->endpoints[0].trbs = device->trbs[0];
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device->endpoints[0].used = 0;
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device->endpoints[0].current = 0;
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device->endpoints[0].trb_addr = device->trb_addr;
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// device should get to default state (bsr = 1)
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if (SetAddress(device->input_ctx_addr, 0, slot) != B_OK) {
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TRACE_ERROR("unable to set address\n");
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return NULL;
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}
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uint8 deviceAddress = SLOT_3_DEVICE_ADDRESS(device->input_ctx->slot.dwslot3);
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device->state = XHCI_STATE_DEFAULT;
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device->address = SLOT_3_DEVICE_ADDRESS_GET(device->device_ctx->slot.dwslot3);
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TRACE("deviceAddress 0x%x\n", deviceAddress);
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TRACE("device: address 0x%x state 0x%lx\n", device->address,
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SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3));
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TRACE("endpoint0 state 0x%lx\n",
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ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0));
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// Create a temporary pipe with the new address
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ControlPipe pipe(parent);
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pipe.InitCommon(deviceAddress, 0, speed, Pipe::Default, 8, 0, hubAddress,
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pipe.SetControllerCookie(&device->endpoints[0]);
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pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, 8, 0, hubAddress,
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hubPort);
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// Get the device descriptor
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@ -698,13 +811,16 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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if (actualLength != 8) {
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TRACE_ERROR("error while getting the device descriptor\n");
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FreeAddress(deviceAddress);
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return NULL;
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}
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TRACE("device_class: %d device_subclass %d device_protocol %d\n",
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deviceDescriptor.device_class, deviceDescriptor.device_subclass,
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deviceDescriptor.device_protocol);
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TRACE("creating new device\n");
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Device *deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort,
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deviceDescriptor, deviceAddress, speed, false);
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deviceDescriptor, device->address + 1, speed, false, device);
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if (!deviceObject) {
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TRACE_ERROR("no memory to allocate device\n");
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return NULL;
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@ -731,6 +847,114 @@ XHCI::FreeDevice(Device *device)
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}
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status_t
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XHCI::_InsertEndpointForPipe(Pipe *pipe)
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{
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if (pipe->ControllerCookie() != NULL
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|| pipe->Parent()->Type() != USB_OBJECT_DEVICE) {
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// default pipe is already referenced
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return B_OK;
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}
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Device* usbDevice = (Device *)pipe->Parent();
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struct xhci_device *device = (struct xhci_device *)
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usbDevice->ControllerCookie();
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if (usbDevice->Parent() == RootObject())
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return B_OK;
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if (device == NULL) {
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panic("_InsertEndpointForPipe device is NULL\n");
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return B_OK;
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}
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uint8 id = XHCI_ENDPOINT_ID(pipe);
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if (id >= XHCI_MAX_ENDPOINTS)
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return B_BAD_VALUE;
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device->endpoints[id].device = device;
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device->endpoints[id].trbs = device->trbs[id];
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device->endpoints[id].td_head = NULL;
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device->endpoints[id].used = 0;
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device->endpoints[id].trb_addr = device->trb_addr
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+ id * sizeof(device->trbs[0]);
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pipe->SetControllerCookie(&device->endpoints[id]);
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TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id);
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return B_OK;
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}
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status_t
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XHCI::_RemoveEndpointForPipe(Pipe *pipe)
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{
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if (pipe->Parent()->Type() != USB_OBJECT_DEVICE)
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return B_OK;
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//Device* device = (Device *)pipe->Parent();
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return B_OK;
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}
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status_t
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XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint)
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{
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TRACE("_LinkDescriptorForPipe\n");
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if (endpoint->used >= XHCI_MAX_TRANSFERS)
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return B_BAD_VALUE;
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endpoint->used++;
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if (endpoint->td_head == NULL)
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descriptor-> next = NULL;
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else
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descriptor->next = endpoint->td_head;
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endpoint->td_head = descriptor;
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uint8 current = endpoint->current;
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uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS - 1);
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// compute next link
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uint8 lastUsed = descriptor->last_used;
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addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb);
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descriptor->trbs[lastUsed + 1].qwtrb0 = addr;
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descriptor->trbs[lastUsed + 1].dwtrb2 = TRB_2_IRQ(0);
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descriptor->trbs[lastUsed + 1].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK)
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| TRB_3_IOC_BIT | TRB_3_CYCLE_BIT;
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endpoint->trbs[next]->qwtrb0 = 0;
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endpoint->trbs[next]->dwtrb2 = 0;
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endpoint->trbs[next]->dwtrb3 = 0;
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endpoint->trbs[current]->qwtrb0 = descriptor->this_phy;
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endpoint->trbs[current]->dwtrb2 = TRB_2_IRQ(0);
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endpoint->trbs[current]->dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK)
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| TRB_3_CYCLE_BIT;
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endpoint->current = next;
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return B_OK;
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}
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status_t
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XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint)
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{
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TRACE("_UnlinkDescriptorForPipe\n");
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endpoint->used--;
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if (descriptor == endpoint->td_head)
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endpoint->td_head = descriptor->next;
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else {
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for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) {
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if (td->next == descriptor) {
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td->next = descriptor->next;
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return B_OK;
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}
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}
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}
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endpoint->used++;
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return B_ERROR;
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}
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status_t
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XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, uint16 interval,
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uint8 maxPacketCount, uint8 mult, uint8 fpsShift, uint16 maxPacketSize,
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@ -1003,22 +1227,28 @@ XHCI::Interrupt()
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uint32 temp = ReadRunReg32(XHCI_IMAN(0));
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WriteOpReg(XHCI_STS, status);
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WriteRunReg32(XHCI_IMAN(0), temp);
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TRACE("STS: %lx IRQ_PENDING: %lx\n", status, temp);
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int32 result = B_HANDLED_INTERRUPT;
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if (status & STS_HCH) {
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if ((status & STS_HCH) != 0) {
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TRACE_ERROR("Host Controller halted\n");
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return result;
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}
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if (status & STS_HSE) {
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if ((status & STS_HSE) != 0) {
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TRACE_ERROR("Host System Error\n");
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return result;
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}
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if (status & STS_HCE) {
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if ((status & STS_HCE) != 0) {
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TRACE_ERROR("Host Controller Error\n");
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return result;
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}
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if ((status & STS_EINT) == 0) {
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TRACE("STS: %lx IRQ_PENDING: %lx\n", status, temp);
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return B_UNHANDLED_INTERRUPT;
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}
|
||||
|
||||
TRACE("Event Interrupt\n");
|
||||
uint16 i = fEventIdx;
|
||||
uint8 j = fEventCcs;
|
||||
uint8 t = 2;
|
||||
@ -1038,6 +1268,13 @@ XHCI::Interrupt()
|
||||
HandleCmdComplete(&fEventRing[i]);
|
||||
result = B_INVOKE_SCHEDULER;
|
||||
break;
|
||||
case TRB_TYPE_TRANSFER:
|
||||
HandleTransferComplete(&fEventRing[i]);
|
||||
result = B_INVOKE_SCHEDULER;
|
||||
break;
|
||||
case TRB_TYPE_PORT_STATUS_CHANGE:
|
||||
TRACE("port change detected\n");
|
||||
break;
|
||||
default:
|
||||
TRACE_ERROR("Unhandled event = %u\n", event);
|
||||
break;
|
||||
@ -1065,12 +1302,17 @@ XHCI::Interrupt()
|
||||
|
||||
|
||||
void
|
||||
XHCI::Ring()
|
||||
XHCI::Ring(uint8 slot, uint8 endpoint)
|
||||
{
|
||||
TRACE("Ding Dong!\n")
|
||||
WriteDoorReg32(XHCI_DOORBELL(0), 0);
|
||||
TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint)
|
||||
if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0))
|
||||
panic("Ring() invalid slot/endpoint combination\n");
|
||||
if (slot > fSlotCount || endpoint > XHCI_MAX_ENDPOINTS)
|
||||
panic("Ring() invalid slot or endpoint\n");
|
||||
WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint)
|
||||
| XHCI_DOORBELL_STREAMID(0));
|
||||
/* Flush PCI posted writes */
|
||||
ReadDoorReg32(XHCI_DOORBELL(0));
|
||||
ReadDoorReg32(XHCI_DOORBELL(slot));
|
||||
}
|
||||
|
||||
|
||||
@ -1130,6 +1372,32 @@ XHCI::HandleCmdComplete(xhci_trb *trb)
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
XHCI::HandleTransferComplete(xhci_trb *trb)
|
||||
{
|
||||
TRACE("HandleTransferComplete trb %p\n", trb);
|
||||
addr_t source = trb->qwtrb0;
|
||||
//uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2);
|
||||
//uint32 remainder = TRB_2_REM(trb->dwtrb2);
|
||||
uint8 endpointNumber = TRB_3_ENDPOINT(trb->dwtrb3);
|
||||
uint8 slot = TRB_3_SLOT(trb->dwtrb3);
|
||||
|
||||
if (slot > fSlotCount)
|
||||
TRACE_ERROR("invalid slot\n");
|
||||
if (endpointNumber == 0 || endpointNumber > XHCI_MAX_ENDPOINTS)
|
||||
TRACE_ERROR("invalid endpoint\n");
|
||||
|
||||
xhci_device *device = &fDevices[slot];
|
||||
xhci_endpoint *endpoint = &device->endpoints[endpointNumber];
|
||||
for (xhci_td *td = endpoint->td_head; td != NULL; td = td->next) {
|
||||
int64 offset = source - td->this_phy;
|
||||
TRACE("HandleTransferComplete td %p offset %lld\n", td, offset);
|
||||
_UnlinkDescriptorForPipe(td, endpoint);
|
||||
FreeDescriptor(td);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
status_t
|
||||
XHCI::DoCommand(xhci_trb *trb)
|
||||
{
|
||||
@ -1137,7 +1405,7 @@ XHCI::DoCommand(xhci_trb *trb)
|
||||
return B_ERROR;
|
||||
|
||||
QueueCommand(trb);
|
||||
Ring();
|
||||
Ring(0, 0);
|
||||
|
||||
if (acquire_sem(fCmdCompSem) < B_OK) {
|
||||
Unlock();
|
||||
@ -1159,6 +1427,7 @@ XHCI::DoCommand(xhci_trb *trb)
|
||||
|
||||
trb->dwtrb2 = fCmdResult[0];
|
||||
trb->dwtrb3 = fCmdResult[1];
|
||||
TRACE("Storing trb 0x%08lx 0x%08lx\n", trb->dwtrb2, trb->dwtrb3);
|
||||
|
||||
Unlock();
|
||||
return status;
|
||||
@ -1190,7 +1459,7 @@ XHCI::EnableSlot(uint8 *slot)
|
||||
return status;
|
||||
|
||||
*slot = TRB_3_SLOT_GET(trb.dwtrb3);
|
||||
return B_OK;
|
||||
return *slot != 0 ? B_OK : B_BAD_VALUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -17,18 +17,48 @@
|
||||
|
||||
struct pci_info;
|
||||
struct pci_module_info;
|
||||
struct xhci_td;
|
||||
struct xhci_device;
|
||||
struct xhci_endpoint;
|
||||
class XHCIRootHub;
|
||||
|
||||
|
||||
enum xhci_state {
|
||||
XHCI_STATE_DISABLED = 0,
|
||||
XHCI_STATE_ENABLED,
|
||||
XHCI_STATE_DEFAULT,
|
||||
XHCI_STATE_ADDRESSED,
|
||||
XHCI_STATE_CONFIGURED,
|
||||
};
|
||||
|
||||
|
||||
struct xhci_device {
|
||||
typedef struct xhci_td {
|
||||
struct xhci_trb trbs[18];
|
||||
|
||||
addr_t buffer_phy;
|
||||
addr_t this_phy; // A physical pointer to this address
|
||||
void *buffer_log; // Pointer to the logical buffer
|
||||
size_t buffer_size; // Size of the buffer
|
||||
|
||||
struct xhci_td *next;
|
||||
uint8 last_used;
|
||||
Transfer *transfer;
|
||||
} xhci_td __attribute__((__aligned__(16)));
|
||||
|
||||
|
||||
typedef struct xhci_endpoint {
|
||||
xhci_device *device;
|
||||
xhci_td *td_head;
|
||||
struct xhci_trb (*trbs)[XHCI_MAX_TRANSFERS];
|
||||
addr_t trb_addr;
|
||||
uint8 used;
|
||||
uint8 current;
|
||||
} xhci_endpoint;
|
||||
|
||||
|
||||
typedef struct xhci_device {
|
||||
uint8 slot;
|
||||
uint8 address;
|
||||
enum xhci_state state;
|
||||
area_id trb_area;
|
||||
addr_t trb_addr;
|
||||
@ -41,7 +71,9 @@ struct xhci_device {
|
||||
area_id device_ctx_area;
|
||||
addr_t device_ctx_addr;
|
||||
struct xhci_device_ctx *device_ctx;
|
||||
};
|
||||
|
||||
xhci_endpoint endpoints[XHCI_MAX_ENDPOINTS - 1];
|
||||
} xhci_device;
|
||||
|
||||
|
||||
class XHCI : public BusManager {
|
||||
@ -51,6 +83,7 @@ public:
|
||||
|
||||
status_t Start();
|
||||
virtual status_t SubmitTransfer(Transfer *transfer);
|
||||
status_t SubmitRequest(Transfer *transfer);
|
||||
virtual status_t CancelQueuedTransfers(Pipe *pipe, bool force);
|
||||
|
||||
virtual status_t NotifyPipeChange(Pipe *pipe,
|
||||
@ -68,6 +101,9 @@ public:
|
||||
uint16 maxPacketSize, uint16 maxFrameSize);
|
||||
virtual void FreeDevice(Device *device);
|
||||
|
||||
status_t _InsertEndpointForPipe(Pipe *pipe);
|
||||
status_t _RemoveEndpointForPipe(Pipe *pipe);
|
||||
|
||||
// Port operations for root hub
|
||||
uint8 PortCount() const { return fPortCount; }
|
||||
status_t GetPortStatus(uint8 index,
|
||||
@ -92,12 +128,22 @@ private:
|
||||
static int32 FinishThread(void *data);
|
||||
void FinishTransfers();
|
||||
|
||||
// Descriptor
|
||||
xhci_td * CreateDescriptor(size_t bufferSize);
|
||||
void FreeDescriptor(xhci_td *descriptor);
|
||||
|
||||
status_t _LinkDescriptorForPipe(xhci_td *descriptor,
|
||||
xhci_endpoint *endpoint);
|
||||
status_t _UnlinkDescriptorForPipe(xhci_td *descriptor,
|
||||
xhci_endpoint *endpoint);
|
||||
|
||||
// Command
|
||||
void QueueCommand(xhci_trb *trb);
|
||||
void HandleCmdComplete(xhci_trb *trb);
|
||||
void HandleTransferComplete(xhci_trb *trb);
|
||||
status_t DoCommand(xhci_trb *trb);
|
||||
//Doorbell
|
||||
void Ring();
|
||||
void Ring(uint8 slot, uint8 endpoint);
|
||||
|
||||
// Commands
|
||||
status_t Noop();
|
||||
|
||||
@ -42,8 +42,9 @@
|
||||
// USB Status Register
|
||||
#define STS_HCH (1 << 0)
|
||||
#define STS_HSE (1 << 2)
|
||||
#define STS_EINT (1 << 3)
|
||||
#define STS_PCD (1 << 4)
|
||||
#define STS_CNR (1<<11)
|
||||
#define STS_CNR (1 << 11)
|
||||
#define STS_HCE (1 << 12)
|
||||
#define XHCI_PAGESIZE 0x08 // PAGE SIZE
|
||||
#define XHCI_DNCTRL 0x14
|
||||
@ -81,6 +82,11 @@
|
||||
|
||||
// Host Controller Doorbell Registers
|
||||
#define XHCI_DOORBELL(n) (0x0000 + (4 * (n)))
|
||||
#define XHCI_DOORBELL_TARGET(x) ((x) & 0xff)
|
||||
#define XHCI_DOORBELL_TARGET_GET(x) ((x) & 0xff)
|
||||
#define XHCI_DOORBELL_STREAMID(x) (((x) & 0xffff) << 16)
|
||||
#define XHCI_DOORBELL_STREAMID_GET(x) (((x) >> 16) & 0xffff)
|
||||
|
||||
|
||||
// Extended Capabilities
|
||||
#define XECP_ID(x) ((x) & 0xff)
|
||||
@ -400,4 +406,8 @@ struct xhci_device_ctx {
|
||||
};
|
||||
|
||||
|
||||
#define XHCI_ENDPOINT_ID(pipe) (2 * pipe->EndpointAddress() \
|
||||
+ (pipe->Direction() != Pipe::Out ? 1 : 0))
|
||||
|
||||
|
||||
#endif // !XHCI_HARDWARE_H
|
||||
|
||||
@ -23,7 +23,7 @@ static usb_device_descriptor sXHCIRootHubDevice =
|
||||
9, // Max packet size on endpoint 0
|
||||
0, // Vendor ID
|
||||
0, // Product ID
|
||||
0x003, // Version
|
||||
0x300, // Version
|
||||
1, // Index of manufacturer string
|
||||
2, // Index of product string
|
||||
0, // Index of serial number string
|
||||
|
||||
Loading…
Reference in New Issue
Block a user