added dualhead switch mode
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@6405 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -1,6 +1,5 @@
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/* NV registers definitions and macros for access to */
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/* NV registers definitions and macros for access to them */
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//new:
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/* PCI_config_space */
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/* PCI_config_space */
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#define NVCFG_DEVID 0x00
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#define NVCFG_DEVID 0x00
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#define NVCFG_DEVCTRL 0x04
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#define NVCFG_DEVCTRL 0x04
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@ -609,8 +608,8 @@
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#define NVBES_NV10_1SRCPTCH 0x0000895c
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#define NVBES_NV10_1SRCPTCH 0x0000895c
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/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */
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/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */
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#define NVBES_DEC_GENCTRL 0x00001588
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#define NVBES_DEC_GENCTRL 0x00001588
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//end new.
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//old:
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/*MAVEN registers (<= G400) */
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/*MAVEN registers (<= G400) */
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#define NVMAV_PGM 0x3E
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#define NVMAV_PGM 0x3E
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#define NVMAV_PIXPLLM 0x80
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#define NVMAV_PIXPLLM 0x80
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@ -668,8 +667,8 @@
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#define NVMAV_STABLE 0xBF
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#define NVMAV_STABLE 0xBF
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#define NVMAV_HDISPLAYTV 0xC2
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#define NVMAV_HDISPLAYTV 0xC2
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#define NVMAV_BREG_0XC6 0xC6
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#define NVMAV_BREG_0XC6 0xC6
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//end old.
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//new:
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/* Macros for convenient accesses to the NV chips */
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/* Macros for convenient accesses to the NV chips */
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#define NV_REG8(r_) ((vuint8 *)regs)[(r_)]
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#define NV_REG8(r_) ((vuint8 *)regs)[(r_)]
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#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]
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#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]
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@ -718,8 +717,8 @@
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/* read and write from the acceleration engine registers */
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/* read and write from the acceleration engine registers */
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#define ACCR(A) (NV_REG32(NVACC_##A))
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#define ACCR(A) (NV_REG32(NVACC_##A))
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#define ACCW(A,B) (NV_REG32(NVACC_##A)=B)
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#define ACCW(A,B) (NV_REG32(NVACC_##A)=B)
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//end new.
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//old:
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/* read and write from maven (<= G400) */
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/* read and write from maven (<= G400) */
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#define MAVR(A) (i2c_maven_read (NVMAV_##A ))
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#define MAVR(A) (i2c_maven_read (NVMAV_##A ))
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#define MAVW(A,B) (i2c_maven_write(NVMAV_##A ,B))
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#define MAVW(A,B) (i2c_maven_write(NVMAV_##A ,B))
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