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* add commented out radeon_hd driver/accel to HaikuImage

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* add boot item support to radeon hd driver
* add edid storage to shared info
* add pull of active monitor VESA EDID to radeon hd driver (until AtomBios complete)
* EDID pulled in driver now passed to create_display_modes
* move registers to external stock xorg radeon hd register headers (lic. allows it)


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41411 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV 2011-05-10 02:02:41 +00:00
parent dde6902f79
commit 2613175e19
10 changed files with 5066 additions and 253 deletions
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3
build/jam/HaikuImage
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@ -118,6 +118,7 @@ SYSTEM_ADD_ONS_ACCELERANTS = $(X86_ONLY)radeon.accelerant
$(X86_ONLY)s3.accelerant $(X86_ONLY)vesa.accelerant $(X86_ONLY)s3.accelerant $(X86_ONLY)vesa.accelerant
$(X86_ONLY)ati.accelerant $(X86_ONLY)ati.accelerant
$(X86_ONLY)3dfx.accelerant $(X86_ONLY)3dfx.accelerant
#$(X86_ONLY)radeon_hd.accelerant
#$(X86_ONLY)via.accelerant #$(X86_ONLY)via.accelerant
#$(X86_ONLY)vmware.accelerant #$(X86_ONLY)vmware.accelerant
; ;
@ -162,7 +163,7 @@ SYSTEM_ADD_ONS_DRIVERS_AUDIO_OLD = ; #cmedia usb_audio ;
SYSTEM_ADD_ONS_DRIVERS_GRAPHICS = $(X86_ONLY)radeon $(X86_ONLY)nvidia SYSTEM_ADD_ONS_DRIVERS_GRAPHICS = $(X86_ONLY)radeon $(X86_ONLY)nvidia
$(X86_ONLY)neomagic $(X86_ONLY)matrox $(X86_ONLY)intel_extreme $(X86_ONLY)neomagic $(X86_ONLY)matrox $(X86_ONLY)intel_extreme
$(X86_ONLY)s3 $(X86_ONLY)vesa #$(X86_ONLY)via #$(X86_ONLY)vmware $(X86_ONLY)s3 $(X86_ONLY)vesa #$(X86_ONLY)via #$(X86_ONLY)vmware
$(X86_ONLY)ati $(X86_ONLY)3dfx $(X86_ONLY)ati $(X86_ONLY)3dfx #$(X86_ONLY)radeon_hd
; ;
SYSTEM_ADD_ONS_DRIVERS_MIDI = emuxki usb_midi ; SYSTEM_ADD_ONS_DRIVERS_MIDI = emuxki usb_midi ;
SYSTEM_ADD_ONS_DRIVERS_NET = $(X86_ONLY)3com $(X86_ONLY)atheros813x SYSTEM_ADD_ONS_DRIVERS_NET = $(X86_ONLY)3com $(X86_ONLY)atheros813x

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headers/private/graphics/radeon_hd/r600_reg.h Normal file
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/*
* RadeonHD R6xx, R7xx Register documentation
*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2009 Matthias Hopf
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _R600_REG_H_
#define _R600_REG_H_
/*
* Register definitions
*/
#include "r600_reg_auto_r6xx.h"
#include "r600_reg_r6xx.h"
#include "r600_reg_r7xx.h"
/* SET_*_REG offsets + ends */
enum {
SET_CONFIG_REG_offset = 0x00008000,
SET_CONFIG_REG_end = 0x0000ac00,
SET_CONTEXT_REG_offset = 0x00028000,
SET_CONTEXT_REG_end = 0x00029000,
SET_ALU_CONST_offset = 0x00030000,
SET_ALU_CONST_end = 0x00032000,
SET_RESOURCE_offset = 0x00038000,
SET_RESOURCE_end = 0x0003c000,
SET_SAMPLER_offset = 0x0003c000,
SET_SAMPLER_end = 0x0003cff0,
SET_CTL_CONST_offset = 0x0003cff0,
SET_CTL_CONST_end = 0x0003e200,
SET_LOOP_CONST_offset = 0x0003e200,
SET_LOOP_CONST_end = 0x0003e380,
SET_BOOL_CONST_offset = 0x0003e380,
SET_BOOL_CONST_end = 0x0003e38c
};
/* packet3 IT_SURFACE_BASE_UPDATE bits */
enum {
DEPTH_BASE = (1 << 0),
COLOR0_BASE = (1 << 1),
COLOR1_BASE = (1 << 2),
COLOR2_BASE = (1 << 3),
COLOR3_BASE = (1 << 4),
COLOR4_BASE = (1 << 5),
COLOR5_BASE = (1 << 6),
COLOR6_BASE = (1 << 7),
COLOR7_BASE = (1 << 8),
STRMOUT_BASE0 = (1 << 9),
STRMOUT_BASE1 = (1 << 10),
STRMOUT_BASE2 = (1 << 11),
STRMOUT_BASE3 = (1 << 12),
COHER_BASE0 = (1 << 13),
COHER_BASE1 = (1 << 14)
};
/* packet3 IT_WAIT_REG_MEM operation encoding */
enum {
WAIT_ALWAYS = (0<<0),
WAIT_LT = (1<<0),
WAIT_LE = (2<<0),
WAIT_EQ = (3<<0),
WAIT_NE = (4<<0),
WAIT_GE = (5<<0),
WAIT_GT = (6<<0),
WAIT_REG = (0<<4),
WAIT_MEM = (1<<4)
};
/* Packet3 commands */
enum {
IT_NOP = 0x10,
IT_INDIRECT_BUFFER_END = 0x17,
IT_SET_PREDICATION = 0x20,
IT_REG_RMW = 0x21,
IT_COND_EXEC = 0x22,
IT_PRED_EXEC = 0x23,
IT_START_3D_CMDBUF = 0x24,
IT_DRAW_INDEX_2 = 0x27,
IT_CONTEXT_CONTROL = 0x28,
IT_DRAW_INDEX_IMMD_BE = 0x29,
IT_INDEX_TYPE = 0x2A,
IT_DRAW_INDEX = 0x2B,
IT_DRAW_INDEX_AUTO = 0x2D,
IT_DRAW_INDEX_IMMD = 0x2E,
IT_NUM_INSTANCES = 0x2F,
IT_STRMOUT_BUFFER_UPDATE = 0x34,
IT_INDIRECT_BUFFER_MP = 0x38,
IT_MEM_SEMAPHORE = 0x39,
IT_MPEG_INDEX = 0x3A,
IT_WAIT_REG_MEM = 0x3C,
IT_MEM_WRITE = 0x3D,
IT_INDIRECT_BUFFER = 0x32,
IT_CP_INTERRUPT = 0x40,
IT_SURFACE_SYNC = 0x43,
IT_ME_INITIALIZE = 0x44,
IT_COND_WRITE = 0x45,
IT_EVENT_WRITE = 0x46,
IT_EVENT_WRITE_EOP = 0x47,
IT_ONE_REG_WRITE = 0x57,
IT_SET_CONFIG_REG = 0x68,
IT_SET_CONTEXT_REG = 0x69,
IT_SET_ALU_CONST = 0x6A,
IT_SET_BOOL_CONST = 0x6B,
IT_SET_LOOP_CONST = 0x6C,
IT_SET_RESOURCE = 0x6D,
IT_SET_SAMPLER = 0x6E,
IT_SET_CTL_CONST = 0x6F,
IT_SURFACE_BASE_UPDATE = 0x73
};
#endif

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headers/private/graphics/radeon_hd/r600_reg_auto_r6xx.h Normal file
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headers/private/graphics/radeon_hd/r600_reg_r6xx.h Normal file
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/*
* RadeonHD R6xx, R7xx Register documentation
*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2009 Matthias Hopf
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _R600_REG_R6xx_H_
#define _R600_REG_R6xx_H_
/*
* Registers for R6xx chips that are not documented yet
*/
enum {
MM_INDEX = 0x0000,
MM_DATA = 0x0004,
SRBM_STATUS = 0x0e50,
RLC_RQ_PENDING_bit = 1 << 3,
RCU_RQ_PENDING_bit = 1 << 4,
GRBM_RQ_PENDING_bit = 1 << 5,
HI_RQ_PENDING_bit = 1 << 6,
IO_EXTERN_SIGNAL_bit = 1 << 7,
VMC_BUSY_bit = 1 << 8,
MCB_BUSY_bit = 1 << 9,
MCDZ_BUSY_bit = 1 << 10,
MCDY_BUSY_bit = 1 << 11,
MCDX_BUSY_bit = 1 << 12,
MCDW_BUSY_bit = 1 << 13,
SEM_BUSY_bit = 1 << 14,
SRBM_STATUS__RLC_BUSY_bit = 1 << 15,
PDMA_BUSY_bit = 1 << 16,
IH_BUSY_bit = 1 << 17,
CSC_BUSY_bit = 1 << 20,
CMC7_BUSY_bit = 1 << 21,
CMC6_BUSY_bit = 1 << 22,
CMC5_BUSY_bit = 1 << 23,
CMC4_BUSY_bit = 1 << 24,
CMC3_BUSY_bit = 1 << 25,
CMC2_BUSY_bit = 1 << 26,
CMC1_BUSY_bit = 1 << 27,
CMC0_BUSY_bit = 1 << 28,
BIF_BUSY_bit = 1 << 29,
IDCT_BUSY_bit = 1 << 30,
SRBM_READ_ERROR = 0x0e98,
READ_ADDRESS_mask = 0xffff << 2,
READ_ADDRESS_shift = 2,
READ_REQUESTER_HI_bit = 1 << 24,
READ_REQUESTER_GRBM_bit = 1 << 25,
READ_REQUESTER_RCU_bit = 1 << 26,
READ_REQUESTER_RLC_bit = 1 << 27,
READ_ERROR_bit = 1 << 31,
SRBM_INT_STATUS = 0x0ea4,
RDERR_INT_STAT_bit = 1 << 0,
GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
SRBM_INT_ACK = 0x0ea8,
RDERR_INT_ACK_bit = 1 << 0,
GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1,
/* R6XX_MC_VM_FB_LOCATION = 0x2180, */
VENDOR_DEVICE_ID = 0x4000,
HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480,
/* D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, */
/* D1GRPH_PITCH = 0x6120, */
/* D1GRPH_Y_END = 0x6138, */
GRBM_STATUS = 0x8010,
R600_CMDFIFO_AVAIL_mask = 0x1f << 0,
R700_CMDFIFO_AVAIL_mask = 0xf << 0,
CMDFIFO_AVAIL_shift = 0,
SRBM_RQ_PENDING_bit = 1 << 5,
CP_RQ_PENDING_bit = 1 << 6,
CF_RQ_PENDING_bit = 1 << 7,
PF_RQ_PENDING_bit = 1 << 8,
GRBM_EE_BUSY_bit = 1 << 10,
GRBM_STATUS__VC_BUSY_bit = 1 << 11,
DB03_CLEAN_bit = 1 << 12,
CB03_CLEAN_bit = 1 << 13,
VGT_BUSY_NO_DMA_bit = 1 << 16,
GRBM_STATUS__VGT_BUSY_bit = 1 << 17,
TA03_BUSY_bit = 1 << 18,
GRBM_STATUS__TC_BUSY_bit = 1 << 19,
SX_BUSY_bit = 1 << 20,
SH_BUSY_bit = 1 << 21,
SPI03_BUSY_bit = 1 << 22,
SMX_BUSY_bit = 1 << 23,
SC_BUSY_bit = 1 << 24,
PA_BUSY_bit = 1 << 25,
DB03_BUSY_bit = 1 << 26,
CR_BUSY_bit = 1 << 27,
CP_COHERENCY_BUSY_bit = 1 << 28,
GRBM_STATUS__CP_BUSY_bit = 1 << 29,
CB03_BUSY_bit = 1 << 30,
GUI_ACTIVE_bit = 1 << 31,
GRBM_STATUS2 = 0x8014,
CR_CLEAN_bit = 1 << 0,
SMX_CLEAN_bit = 1 << 1,
SPI0_BUSY_bit = 1 << 8,
SPI1_BUSY_bit = 1 << 9,
SPI2_BUSY_bit = 1 << 10,
SPI3_BUSY_bit = 1 << 11,
TA0_BUSY_bit = 1 << 12,
TA1_BUSY_bit = 1 << 13,
TA2_BUSY_bit = 1 << 14,
TA3_BUSY_bit = 1 << 15,
DB0_BUSY_bit = 1 << 16,
DB1_BUSY_bit = 1 << 17,
DB2_BUSY_bit = 1 << 18,
DB3_BUSY_bit = 1 << 19,
CB0_BUSY_bit = 1 << 20,
CB1_BUSY_bit = 1 << 21,
CB2_BUSY_bit = 1 << 22,
CB3_BUSY_bit = 1 << 23,
GRBM_SOFT_RESET = 0x8020,
SOFT_RESET_CP_bit = 1 << 0,
SOFT_RESET_CB_bit = 1 << 1,
SOFT_RESET_CR_bit = 1 << 2,
SOFT_RESET_DB_bit = 1 << 3,
SOFT_RESET_PA_bit = 1 << 5,
SOFT_RESET_SC_bit = 1 << 6,
SOFT_RESET_SMX_bit = 1 << 7,
SOFT_RESET_SPI_bit = 1 << 8,
SOFT_RESET_SH_bit = 1 << 9,
SOFT_RESET_SX_bit = 1 << 10,
SOFT_RESET_TC_bit = 1 << 11,
SOFT_RESET_TA_bit = 1 << 12,
SOFT_RESET_VC_bit = 1 << 13,
SOFT_RESET_VGT_bit = 1 << 14,
SOFT_RESET_GRBM_GCA_bit = 1 << 15,
WAIT_UNTIL = 0x8040,
WAIT_CP_DMA_IDLE_bit = 1 << 8,
WAIT_CMDFIFO_bit = 1 << 10,
WAIT_2D_IDLE_bit = 1 << 14,
WAIT_3D_IDLE_bit = 1 << 15,
WAIT_2D_IDLECLEAN_bit = 1 << 16,
WAIT_3D_IDLECLEAN_bit = 1 << 17,
WAIT_EXTERN_SIG_bit = 1 << 19,
CMDFIFO_ENTRIES_mask = 0x1f << 20,
CMDFIFO_ENTRIES_shift = 20,
GRBM_READ_ERROR = 0x8058,
/* READ_ADDRESS_mask = 0xffff << 2, */
/* READ_ADDRESS_shift = 2, */
READ_REQUESTER_SRBM_bit = 1 << 28,
READ_REQUESTER_CP_bit = 1 << 29,
READ_REQUESTER_WU_POLL_bit = 1 << 30,
/* READ_ERROR_bit = 1 << 31, */
SCRATCH_REG0 = 0x8500,
SCRATCH_REG1 = 0x8504,
SCRATCH_REG2 = 0x8508,
SCRATCH_REG3 = 0x850c,
SCRATCH_REG4 = 0x8510,
SCRATCH_REG5 = 0x8514,
SCRATCH_REG6 = 0x8518,
SCRATCH_REG7 = 0x851c,
SCRATCH_UMSK = 0x8540,
SCRATCH_ADDR = 0x8544,
CP_COHER_CNTL = 0x85f0,
DEST_BASE_0_ENA_bit = 1 << 0,
DEST_BASE_1_ENA_bit = 1 << 1,
SO0_DEST_BASE_ENA_bit = 1 << 2,
SO1_DEST_BASE_ENA_bit = 1 << 3,
SO2_DEST_BASE_ENA_bit = 1 << 4,
SO3_DEST_BASE_ENA_bit = 1 << 5,
CB0_DEST_BASE_ENA_bit = 1 << 6,
CB1_DEST_BASE_ENA_bit = 1 << 7,
CB2_DEST_BASE_ENA_bit = 1 << 8,
CB3_DEST_BASE_ENA_bit = 1 << 9,
CB4_DEST_BASE_ENA_bit = 1 << 10,
CB5_DEST_BASE_ENA_bit = 1 << 11,
CB6_DEST_BASE_ENA_bit = 1 << 12,
CB7_DEST_BASE_ENA_bit = 1 << 13,
DB_DEST_BASE_ENA_bit = 1 << 14,
CR_DEST_BASE_ENA_bit = 1 << 15,
TC_ACTION_ENA_bit = 1 << 23,
VC_ACTION_ENA_bit = 1 << 24,
CB_ACTION_ENA_bit = 1 << 25,
DB_ACTION_ENA_bit = 1 << 26,
SH_ACTION_ENA_bit = 1 << 27,
SMX_ACTION_ENA_bit = 1 << 28,
CR0_ACTION_ENA_bit = 1 << 29,
CR1_ACTION_ENA_bit = 1 << 30,
CR2_ACTION_ENA_bit = 1 << 31,
CP_COHER_SIZE = 0x85f4,
CP_COHER_BASE = 0x85f8,
CP_COHER_STATUS = 0x85fc,
MATCHING_GFX_CNTX_mask = 0xff << 0,
MATCHING_GFX_CNTX_shift = 0,
MATCHING_CR_CNTX_mask = 0xffff << 8,
MATCHING_CR_CNTX_shift = 8,
STATUS_bit = 1 << 31,
CP_STALLED_STAT1 = 0x8674,
RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0,
RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1,
RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2,
RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3,
RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4,
RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5,
RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6,
RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7,
RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8,
RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9,
MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16,
MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17,
MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18,
RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24,
RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25,
RCIU_STALLED_ON_ME_READ_bit = 1 << 26,
RCIU_STALLED_ON_DMA_READ_bit = 1 << 27,
RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28,
CP_STALLED_STAT2 = 0x8678,
PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0,
PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1,
PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2,
PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3,
MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4,
ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8,
ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9,
CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10,
GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11,
ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12,
ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13,
ME_WAITING_DATA_FROM_PFP_bit = 1 << 14,
ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15,
RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16,
RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17,
EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18,
EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19,
EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20,
EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21,
SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22,
SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23,
PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24,
SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30,
SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31,
CP_BUSY_STAT = 0x867c,
REG_BUS_FIFO_BUSY_bit = 1 << 0,
RING_FETCHING_DATA_bit = 1 << 1,
INDR1_FETCHING_DATA_bit = 1 << 2,
INDR2_FETCHING_DATA_bit = 1 << 3,
STATE_FETCHING_DATA_bit = 1 << 4,
PRED_FETCHING_DATA_bit = 1 << 5,
COHER_CNTR_NEQ_ZERO_bit = 1 << 6,
PFP_PARSING_PACKETS_bit = 1 << 7,
ME_PARSING_PACKETS_bit = 1 << 8,
RCIU_PFP_BUSY_bit = 1 << 9,
RCIU_ME_BUSY_bit = 1 << 10,
OUTSTANDING_READ_TAGS_bit = 1 << 11,
SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12,
SEM_FAILED_AND_HOLDING_bit = 1 << 13,
SEM_POLLING_FOR_PASS_bit = 1 << 14,
_3D_BUSY_bit = 1 << 15,
_2D_BUSY_bit = 1 << 16,
CP_STAT = 0x8680,
CSF_RING_BUSY_bit = 1 << 0,
CSF_WPTR_POLL_BUSY_bit = 1 << 1,
CSF_INDIRECT1_BUSY_bit = 1 << 2,
CSF_INDIRECT2_BUSY_bit = 1 << 3,
CSF_STATE_BUSY_bit = 1 << 4,
CSF_PREDICATE_BUSY_bit = 1 << 5,
CSF_BUSY_bit = 1 << 6,
MIU_RDREQ_BUSY_bit = 1 << 7,
MIU_WRREQ_BUSY_bit = 1 << 8,
ROQ_RING_BUSY_bit = 1 << 9,
ROQ_INDIRECT1_BUSY_bit = 1 << 10,
ROQ_INDIRECT2_BUSY_bit = 1 << 11,
ROQ_STATE_BUSY_bit = 1 << 12,
ROQ_PREDICATE_BUSY_bit = 1 << 13,
ROQ_ALIGN_BUSY_bit = 1 << 14,
PFP_BUSY_bit = 1 << 15,
MEQ_BUSY_bit = 1 << 16,
ME_BUSY_bit = 1 << 17,
QUERY_BUSY_bit = 1 << 18,
SEMAPHORE_BUSY_bit = 1 << 19,
INTERRUPT_BUSY_bit = 1 << 20,
SURFACE_SYNC_BUSY_bit = 1 << 21,
DMA_BUSY_bit = 1 << 22,
RCIU_BUSY_bit = 1 << 23,
CP_STAT__CP_BUSY_bit = 1 << 31,
CP_ME_CNTL = 0x86d8,
ME_STATMUX_mask = 0xff << 0,
ME_STATMUX_shift = 0,
ME_HALT_bit = 1 << 28,
CP_ME_STATUS = 0x86dc,
CP_RB_RPTR = 0x8700,
RB_RPTR_mask = 0xfffff << 0,
RB_RPTR_shift = 0,
CP_RB_WPTR_DELAY = 0x8704,
PRE_WRITE_TIMER_mask = 0xfffffff << 0,
PRE_WRITE_TIMER_shift = 0,
PRE_WRITE_LIMIT_mask = 0x0f << 28,
PRE_WRITE_LIMIT_shift = 28,
CP_ROQ_RB_STAT = 0x8780,
ROQ_RPTR_PRIMARY_mask = 0x3ff << 0,
ROQ_RPTR_PRIMARY_shift = 0,
ROQ_WPTR_PRIMARY_mask = 0x3ff << 16,
ROQ_WPTR_PRIMARY_shift = 16,
CP_ROQ_IB1_STAT = 0x8784,
ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0,
ROQ_RPTR_INDIRECT1_shift = 0,
ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16,
ROQ_WPTR_INDIRECT1_shift = 16,
CP_ROQ_IB2_STAT = 0x8788,
ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0,
ROQ_RPTR_INDIRECT2_shift = 0,
ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16,
ROQ_WPTR_INDIRECT2_shift = 16,
CP_MEQ_STAT = 0x8794,
MEQ_RPTR_mask = 0x3ff << 0,
MEQ_RPTR_shift = 0,
MEQ_WPTR_mask = 0x3ff << 16,
MEQ_WPTR_shift = 16,
CC_GC_SHADER_PIPE_CONFIG = 0x8950,
INACTIVE_QD_PIPES_mask = 0xff << 8,
INACTIVE_QD_PIPES_shift = 8,
R6XX_MAX_QD_PIPES = 8,
INACTIVE_SIMDS_mask = 0xff << 16,
INACTIVE_SIMDS_shift = 16,
R6XX_MAX_SIMDS = 8,
GC_USER_SHADER_PIPE_CONFIG = 0x8954,
VC_ENHANCE = 0x9714,
DB_DEBUG = 0x9830,
PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31,
DB_WATERMARKS = 0x00009838,
DEPTH_FREE_mask = 0x1f << 0,
DEPTH_FREE_shift = 0,
DEPTH_FLUSH_mask = 0x3f << 5,
DEPTH_FLUSH_shift = 5,
FORCE_SUMMARIZE_mask = 0x0f << 11,
FORCE_SUMMARIZE_shift = 11,
DEPTH_PENDING_FREE_mask = 0x1f << 15,
DEPTH_PENDING_FREE_shift = 15,
DEPTH_CACHELINE_FREE_mask = 0x1f << 20,
DEPTH_CACHELINE_FREE_shift = 20,
EARLY_Z_PANIC_DISABLE_bit = 1 << 25,
LATE_Z_PANIC_DISABLE_bit = 1 << 26,
RE_Z_PANIC_DISABLE_bit = 1 << 27,
DB_EXTRA_DEBUG_mask = 0x0f << 28,
DB_EXTRA_DEBUG_shift = 28,
CP_RB_BASE = 0xc100,
CP_RB_CNTL = 0xc104,
RB_BUFSZ_mask = 0x3f << 0,
CP_RB_WPTR = 0xc114,
RB_WPTR_mask = 0xfffff << 0,
RB_WPTR_shift = 0,
CP_RB_RPTR_WR = 0xc108,
RB_RPTR_WR_mask = 0xfffff << 0,
RB_RPTR_WR_shift = 0,
CP_INT_STATUS = 0xc128,
DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0,
ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
SEM_SIGNAL_INT_STAT_bit = 1 << 18,
CNTX_BUSY_INT_STAT_bit = 1 << 19,
CNTX_EMPTY_INT_STAT_bit = 1 << 20,
WAITMEM_SEM_INT_STAT_bit = 1 << 21,
PRIV_INSTR_INT_STAT_bit = 1 << 22,
PRIV_REG_INT_STAT_bit = 1 << 23,
OPCODE_ERROR_INT_STAT_bit = 1 << 24,
SCRATCH_INT_STAT_bit = 1 << 25,
TIME_STAMP_INT_STAT_bit = 1 << 26,
RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27,
DMA_INT_STAT_bit = 1 << 28,
IB2_INT_STAT_bit = 1 << 29,
IB1_INT_STAT_bit = 1 << 30,
RB_INT_STAT_bit = 1 << 31,
/* SX_ALPHA_TEST_CONTROL = 0x00028410, */
ALPHA_FUNC__REF_NEVER = 0,
ALPHA_FUNC__REF_ALWAYS = 7,
/* DB_SHADER_CONTROL = 0x0002880c, */
Z_ORDER__EARLY_Z_THEN_LATE_Z = 2,
/* PA_SU_SC_MODE_CNTL = 0x00028814, */
/* POLY_MODE_mask = 0x03 << 3, */
POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE,
/* POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, */
POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES,
PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20,
DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */
/* DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, */
DB_ALPHA_TO_MASK = 0x00028d44,
ALPHA_TO_MASK_ENABLE = 1 << 0,
ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET0_shift = 8,
ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET1_shift = 10,
ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET2_shift = 12,
ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET3_shift = 14,
/* SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, */
/* SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, */
FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2,
FMT_16=5, FMT_16_FLOAT, FMT_8_8,
FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4,
FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16,
FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8,
FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10,
FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2,
FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16,
FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
FMT_1 = 37, FMT_GB_GR=39,
FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP,
FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32,
FMT_32_32_32_FLOAT=48,
/* High level register file lengths */
SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */
SQ_ALU_CONSTANT_ps_num = 256,
SQ_ALU_CONSTANT_vs_num = 256,
SQ_ALU_CONSTANT_all_num = 512,
SQ_ALU_CONSTANT_offset = 16,
SQ_ALU_CONSTANT_ps = 0,
SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num,
SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
SQ_TEX_RESOURCE_ps_num = 160,
SQ_TEX_RESOURCE_vs_num = 160,
SQ_TEX_RESOURCE_fs_num = 16,
SQ_TEX_RESOURCE_gs_num = 160,
SQ_TEX_RESOURCE_all_num = 496,
SQ_TEX_RESOURCE_offset = 28,
SQ_TEX_RESOURCE_ps = 0,
SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num,
SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num,
SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num,
SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
SQ_VTX_RESOURCE_ps_num = 160,
SQ_VTX_RESOURCE_vs_num = 160,
SQ_VTX_RESOURCE_fs_num = 16,
SQ_VTX_RESOURCE_gs_num = 160,
SQ_VTX_RESOURCE_all_num = 496,
SQ_VTX_RESOURCE_offset = 28,
SQ_VTX_RESOURCE_ps = 0,
SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num,
SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num,
SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num,
SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */
SQ_TEX_SAMPLER_WORD_ps_num = 18,
SQ_TEX_SAMPLER_WORD_vs_num = 18,
SQ_TEX_SAMPLER_WORD_gs_num = 18,
SQ_TEX_SAMPLER_WORD_all_num = 54,
SQ_TEX_SAMPLER_WORD_offset = 12,
SQ_TEX_SAMPLER_WORD_ps = 0,
SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num,
SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num,
SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */
SQ_LOOP_CONST_ps_num = 32,
SQ_LOOP_CONST_vs_num = 32,
SQ_LOOP_CONST_gs_num = 32,
SQ_LOOP_CONST_all_num = 96,
SQ_LOOP_CONST_offset = 4,
SQ_LOOP_CONST_ps = 0,
SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num,
SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num,
SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */
SQ_BOOL_CONST_ps_num = 1,
SQ_BOOL_CONST_vs_num = 1,
SQ_BOOL_CONST_gs_num = 1,
SQ_BOOL_CONST_all_num = 3,
SQ_BOOL_CONST_offset = 4,
SQ_BOOL_CONST_ps = 0,
SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num,
SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num
};
#endif

149
headers/private/graphics/radeon_hd/r600_reg_r7xx.h Normal file
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@ -0,0 +1,149 @@
/*
* RadeonHD R6xx, R7xx Register documentation
*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2009 Matthias Hopf
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _R600_REG_R7xx_H_
#define _R600_REG_R7xx_H_
/*
* Register update for R7xx chips
*/
enum {
/* R7XX_MC_VM_FB_LOCATION = 0x00002024, */
/* GRBM_STATUS = 0x00008010, */
R7XX_TA_BUSY_bit = 1 << 14,
R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x00008d8c,
RING0_OFFSET_mask = 0xff << 0,
RING0_OFFSET_shift = 0,
ISOLATE_ES_ENABLE_bit = 1 << 12,
ISOLATE_GS_ENABLE_bit = 1 << 13,
VS_PC_LIMIT_ENABLE_bit = 1 << 14,
/* SQ_ALU_WORD0 = 0x00008dfc, */
/* SRC0_SEL_mask = 0x1ff << 0, */
/* SRC1_SEL_mask = 0x1ff << 13, */
R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
/* INDEX_MODE_mask = 0x07 << 26, */
R7xx_SQ_INDEX_GLOBAL = 0x05,
R7xx_SQ_INDEX_GLOBAL_AR_X = 0x06,
R6xx_SQ_ALU_WORD1_OP2 = 0x00008dfc,
R7xx_SQ_ALU_WORD1_OP2_V2 = 0x00008dfc,
R6xx_FOG_MERGE_bit = 1 << 5,
R6xx_OMOD_mask = 0x03 << 6,
R7xx_OMOD_mask = 0x03 << 5,
R6xx_OMOD_shift = 6,
R7xx_OMOD_shift = 5,
R6xx_SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8,
R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7,
R6xx_SQ_ALU_WORD1_OP2__ALU_INST_shift = 8,
R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7,
R7xx_SQ_OP2_INST_FREXP_64 = 0x07,
R7xx_SQ_OP2_INST_ADD_64 = 0x17,
R7xx_SQ_OP2_INST_MUL_64 = 0x1b,
R7xx_SQ_OP2_INST_FLT64_TO_FLT32 = 0x1c,
R7xx_SQ_OP2_INST_FLT32_TO_FLT64 = 0x1d,
R7xx_SQ_OP2_INST_LDEXP_64 = 0x7a,
R7xx_SQ_OP2_INST_FRACT_64 = 0x7b,
R7xx_SQ_OP2_INST_PRED_SETGT_64 = 0x7c,
R7xx_SQ_OP2_INST_PRED_SETE_64 = 0x7d,
R7xx_SQ_OP2_INST_PRED_SETGE_64 = 0x7e,
/* SQ_ALU_WORD1_OP3 = 0x00008dfc, */
/* SRC2_SEL_mask = 0x1ff << 0, */
/* R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4, */
/* R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5, */
/* R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6, */
/* R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7, */
/* SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, */
R7xx_SQ_OP3_INST_MULADD_64 = 0x08,
R7xx_SQ_OP3_INST_MULADD_64_M2 = 0x09,
R7xx_SQ_OP3_INST_MULADD_64_M4 = 0x0a,
R7xx_SQ_OP3_INST_MULADD_64_D2 = 0x0b,
/* SQ_CF_ALU_WORD1 = 0x00008dfc, */
R6xx_USES_WATERFALL_bit = 1 << 25,
R7xx_SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
/* SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, */
/* ARRAY_BASE_mask = 0x1fff << 0, */
/* TYPE_mask = 0x03 << 13, */
/* SQ_EXPORT_PARAM = 0x02, */
/* X_UNUSED_FOR_SX_EXPORTS = 0x03, */
/* ELEM_SIZE_mask = 0x03 << 30, */
/* SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, */
/* SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23, */
R7xx_SQ_CF_INST_MEM_EXPORT = 0x3a,
/* SQ_CF_WORD1 = 0x00008dfc, */
/* SQ_CF_WORD1__COUNT_mask = 0x07 << 10, */
R7xx_COUNT_3_bit = 1 << 19,
/* SQ_CF_WORD1__CF_INST_mask = 0x7f << 23, */
R7xx_SQ_CF_INST_END_PROGRAM = 0x19,
R7xx_SQ_CF_INST_WAIT_ACK = 0x1a,
R7xx_SQ_CF_INST_TEX_ACK = 0x1b,
R7xx_SQ_CF_INST_VTX_ACK = 0x1c,
R7xx_SQ_CF_INST_VTX_TC_ACK = 0x1d,
/* SQ_VTX_WORD0 = 0x00008dfc, */
/* VTX_INST_mask = 0x1f << 0, */
R7xx_SQ_VTX_INST_MEM = 0x02,
/* SQ_VTX_WORD2 = 0x00008dfc, */
R7xx_SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20,
/* SQ_TEX_WORD0 = 0x00008dfc, */
/* TEX_INST_mask = 0x1f << 0, */
R7xx_X_MEMORY_READ = 0x02,
R7xx_SQ_TEX_INST_KEEP_GRADIENTS = 0x0a,
R7xx_X_FETCH4_LOAD4_INSTRUCTION_FOR_DX10_1 = 0x0f,
R7xx_SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24,
R7xx_PA_SC_EDGERULE = 0x00028230,
R7xx_SPI_THREAD_GROUPING = 0x000286c8,
PS_GROUPING_mask = 0x1f << 0,
PS_GROUPING_shift = 0,
VS_GROUPING_mask = 0x1f << 8,
VS_GROUPING_shift = 8,
GS_GROUPING_mask = 0x1f << 16,
GS_GROUPING_shift = 16,
ES_GROUPING_mask = 0x1f << 24,
ES_GROUPING_shift = 24,
R7xx_CB_SHADER_CONTROL = 0x000287a0,
RT0_ENABLE_bit = 1 << 0,
RT1_ENABLE_bit = 1 << 1,
RT2_ENABLE_bit = 1 << 2,
RT3_ENABLE_bit = 1 << 3,
RT4_ENABLE_bit = 1 << 4,
RT5_ENABLE_bit = 1 << 5,
RT6_ENABLE_bit = 1 << 6,
RT7_ENABLE_bit = 1 << 7,
/* DB_ALPHA_TO_MASK = 0x00028d44, */
R7xx_OFFSET_ROUND_bit = 1 << 16,
/* SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c, */
R7xx_TRUNCATE_COORD_bit = 1 << 9,
R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10
} ;
#endif /* _R600_REG_R7xx_H_ */

198
headers/private/graphics/radeon_hd/radeon_hd.h
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@ -1,45 +1,23 @@
/* /*
* Copyright 2006-2009, Haiku, Inc. All Rights Reserved. * Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License. * Distributed under the terms of the MIT License.
* *
* Authors: * Authors:
* Axel Dörfler, axeld@pinc-software.de * Axel Dörfler, axeld@pinc-software.de
* Alexander von Gluck IV, kallisti5@unixzen.com * Alexander von Gluck IV, kallisti5@unixzen.com
*/ */
/* Copyright for portions of this file (Xorg radeonhd registers)
*
* Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de>
* Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com>
* Copyright 2007, 2008 Egbert Eich <eich@novell.com>
* Copyright 2007, 2008 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RADEON_HD_H #ifndef RADEON_HD_H
#define RADEON_HD_H #define RADEON_HD_H
#include "lock.h" #include "lock.h"
#include "rhd_regs.h"
#include "r600_reg.h"
#include <Accelerant.h> #include <Accelerant.h>
#include <Drivers.h> #include <Drivers.h>
#include <edid.h>
#include <PCI.h> #include <PCI.h>
@ -54,9 +32,15 @@
#define RADEON_R700 0x0700 #define RADEON_R700 0x0700
#define RADEON_R800 0x0800 #define RADEON_R800 0x0800
#define RADEON_VBIOS_SIZE 0x10000
#define DEVICE_NAME "radeon_hd" #define DEVICE_NAME "radeon_hd"
#define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant"
// Used to collect EDID from boot loader
#define EDID_BOOT_INFO "vesa_edid/v1"
#define MODES_BOOT_INFO "vesa_modes/v1"
struct DeviceType { struct DeviceType {
uint32 type; uint32 type;
@ -128,6 +112,9 @@ struct radeon_shared_info {
addr_t physical_graphics_memory; addr_t physical_graphics_memory;
uint32 graphics_memory_size; uint32 graphics_memory_size;
bool has_edid;
edid1_info edid_info;
addr_t frame_buffer; addr_t frame_buffer;
uint32 frame_buffer_offset; uint32 frame_buffer_offset;
@ -193,163 +180,6 @@ struct radeon_free_graphics_memory {
uint32 buffer_base; uint32 buffer_base;
}; };
// ----------------------------------------------------------
// Register definitions, taken from X driver
// Generic Radeon registers
enum {
CLOCK_CNTL_INDEX = 0x8, /* (RW) */
CLOCK_CNTL_DATA = 0xC, /* (RW) */
BUS_CNTL = 0x4C, /* (RW) */
MC_IND_INDEX = 0x70, /* (RW) */
MC_IND_DATA = 0x74, /* (RW) */
RS600_MC_INDEX = 0x70,
RS600_MC_DATA = 0x74,
RS690_MC_INDEX = 0x78,
RS690_MC_DATA = 0x7c,
RS780_MC_INDEX = 0x28f8,
RS780_MC_DATA = 0x28fc,
RS60_MC_NB_MC_INDEX = 0x78,
RS60_MC_NB_MC_DATA = 0x7C,
CONFIG_CNTL = 0xE0,
PCIE_RS69_MC_INDEX = 0xE8,
PCIE_RS69_MC_DATA = 0xEC,
R5XX_CONFIG_MEMSIZE = 0x00F8,
HDP_FB_LOCATION = 0x0134,
SEPROM_CNTL1 = 0x1C0, /* (RW) */
AGP_BASE = 0x0170,
GPIOPAD_MASK = 0x198, /* (RW) */
GPIOPAD_A = 0x19C, /* (RW) */
GPIOPAD_EN = 0x1A0, /* (RW) */
VIPH_CONTROL = 0xC40, /* (RW) */
ROM_CNTL = 0x1600,
GENERAL_PWRMGT = 0x0618,
LOW_VID_LOWER_GPIO_CNTL = 0x0724,
MEDIUM_VID_LOWER_GPIO_CNTL = 0x0720,
HIGH_VID_LOWER_GPIO_CNTL = 0x071C,
CTXSW_VID_LOWER_GPIO_CNTL = 0x0718,
LOWER_GPIO_ENABLE = 0x0710,
/* VGA registers */
VGA_RENDER_CONTROL = 0x0300,
VGA_MODE_CONTROL = 0x0308,
VGA_MEMORY_BASE_ADDRESS = 0x0310,
VGA_HDP_CONTROL = 0x0328,
D1VGA_CONTROL = 0x0330,
D2VGA_CONTROL = 0x0338,
EXT1_PPLL_REF_DIV_SRC = 0x0400,
EXT1_PPLL_REF_DIV = 0x0404,
EXT1_PPLL_UPDATE_LOCK = 0x0408,
EXT1_PPLL_UPDATE_CNTL = 0x040C,
EXT2_PPLL_REF_DIV_SRC = 0x0410,
EXT2_PPLL_REF_DIV = 0x0414,
EXT2_PPLL_UPDATE_LOCK = 0x0418,
EXT2_PPLL_UPDATE_CNTL = 0x041C,
EXT1_PPLL_FB_DIV = 0x0430,
EXT2_PPLL_FB_DIV = 0x0434,
EXT1_PPLL_POST_DIV_SRC = 0x0438,
EXT1_PPLL_POST_DIV = 0x043C,
EXT2_PPLL_POST_DIV_SRC = 0x0440,
EXT2_PPLL_POST_DIV = 0x0444,
EXT1_PPLL_CNTL = 0x0448,
EXT2_PPLL_CNTL = 0x044C,
P1PLL_CNTL = 0x0450,
P2PLL_CNTL = 0x0454,
P1PLL_INT_SS_CNTL = 0x0458,
P2PLL_INT_SS_CNTL = 0x045C,
P1PLL_DISP_CLK_CNTL = 0x0468, /* rv620+ */
P2PLL_DISP_CLK_CNTL = 0x046C, /* rv620+ */
EXT1_SYM_PPLL_POST_DIV = 0x0470, /* rv620+ */
EXT2_SYM_PPLL_POST_DIV = 0x0474, /* rv620+ */
PCLK_CRTC1_CNTL = 0x0480,
PCLK_CRTC2_CNTL = 0x0484,
// TODO : xorg reverse engineered registers
};
// ATI r600 specific
enum _r6xxRegs {
/* MCLK */
R6_MCLK_PWRMGT_CNTL = 0x620,
/* I2C */
R6_DC_I2C_CONTROL = 0x7D30, /* (RW) */
R6_DC_I2C_ARBITRATION = 0x7D34, /* (RW) */
R6_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */
R6_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) */
R6_DC_I2C_DDC1_SPEED = 0x7D4C, /* (RW) */
R6_DC_I2C_DDC1_SETUP = 0x7D50, /* (RW) */
R6_DC_I2C_DDC2_SPEED = 0x7D54, /* (RW) */
R6_DC_I2C_DDC2_SETUP = 0x7D58, /* (RW) */
R6_DC_I2C_DDC3_SPEED = 0x7D5C, /* (RW) */
R6_DC_I2C_DDC3_SETUP = 0x7D60, /* (RW) */
R6_DC_I2C_TRANSACTION0 = 0x7D64, /* (RW) */
R6_DC_I2C_TRANSACTION1 = 0x7D68, /* (RW) */
R6_DC_I2C_DATA = 0x7D74, /* (RW) */
R6_DC_I2C_DDC4_SPEED = 0x7DB4, /* (RW) */
R6_DC_I2C_DDC4_SETUP = 0x7DBC, /* (RW) */
R6_DC_GPIO_DDC4_MASK = 0x7E00, /* (RW) */
R6_DC_GPIO_DDC4_A = 0x7E04, /* (RW) */
R6_DC_GPIO_DDC4_EN = 0x7E08, /* (RW) */
R6_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */
R6_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */
R6_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */
R6_DC_GPIO_DDC1_Y = 0x7E4C, /* (RW) */
R6_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */
R6_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */
R6_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */
R6_DC_GPIO_DDC2_Y = 0x7E5C, /* (RW) */
R6_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */
R6_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */
R6_DC_GPIO_DDC3_EN = 0x7E68, /* (RW) */
R6_DC_GPIO_DDC3_Y = 0x7E6C /* (RW) */
};
// PLL Clock Controls
enum {
/* CLOCK_CNTL_INDEX */
PLL_ADDR = (0x3f << 0),
PLL_WR_EN = (0x1 << 7),
PPLL_DIV_SEL = (0x3 << 8),
/* SPLL_FUNC_CNTL */
SPLL_CHG_STATUS = (0x1 << 29),
SPLL_BYPASS_EN = (0x1 << 25),
/* MC_IND_INDEX */
MC_IND_ADDR = (0xffff << 0),
MC_IND_SEQ_RBS_0 = (0x1 << 16),
MC_IND_SEQ_RBS_1 = (0x1 << 17),
MC_IND_SEQ_RBS_2 = (0x1 << 18),
MC_IND_SEQ_RBS_3 = (0x1 << 19),
MC_IND_AIC_RBS = (0x1 << 20),
MC_IND_CITF_ARB0 = (0x1 << 21),
MC_IND_CITF_ARB1 = (0x1 << 22),
MC_IND_WR_EN = (0x1 << 23),
MC_IND_RD_INV = (0x1 << 24)
};
/* CLOCK_CNTL_DATA */
#define PLL_DATA 0xffffffff
/* MC_IND_DATA */
#define MC_IND_ALL (MC_IND_SEQ_RBS_0 | MC_IND_SEQ_RBS_1 \
| MC_IND_SEQ_RBS_2 | MC_IND_SEQ_RBS_3 \
| MC_IND_AIC_RBS | MC_IND_CITF_ARB0 \
| MC_IND_CITF_ARB1)
#define MC_IND_DATA_BIT 0xffffffff
// cursor // cursor
#define RADEON_CURSOR_CONTROL 0x70080 #define RADEON_CURSOR_CONTROL 0x70080

1158
headers/private/graphics/radeon_hd/rhd_regs.h Normal file
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File diff suppressed because it is too large Load Diff

8
src/add-ons/accelerants/radeon_hd/mode.cpp
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@ -35,13 +35,14 @@ extern "C" void _sPrintf(const char *format, ...);
status_t status_t
create_mode_list(void) create_mode_list(void)
{ {
// TODO : Read active monitor EDID for create_display_modes
const color_space kRadeonHDSpaces[] = {B_RGB32_LITTLE, B_RGB24_LITTLE, const color_space kRadeonHDSpaces[] = {B_RGB32_LITTLE, B_RGB24_LITTLE,
B_RGB16_LITTLE, B_RGB15_LITTLE, B_CMAP8}; B_RGB16_LITTLE, B_RGB15_LITTLE, B_CMAP8};
// TODO : Read EDID for create_display_modes via AtomBios as well
gInfo->mode_list_area = create_display_modes("radeon HD modes", gInfo->mode_list_area = create_display_modes("radeon HD modes",
NULL, NULL, 0, kRadeonHDSpaces, gInfo->shared_info->has_edid ? &gInfo->shared_info->edid_info : NULL,
NULL, 0, kRadeonHDSpaces,
sizeof(kRadeonHDSpaces) / sizeof(kRadeonHDSpaces[0]), sizeof(kRadeonHDSpaces) / sizeof(kRadeonHDSpaces[0]),
is_mode_supported, &gInfo->mode_list, &gInfo->shared_info->mode_count); is_mode_supported, &gInfo->mode_list, &gInfo->shared_info->mode_count);
if (gInfo->mode_list_area < B_OK) if (gInfo->mode_list_area < B_OK)
@ -50,7 +51,6 @@ create_mode_list(void)
gInfo->shared_info->mode_list_area = gInfo->mode_list_area; gInfo->shared_info->mode_list_area = gInfo->mode_list_area;
/* Example nonstandard mode line (1600x900@60) */ /* Example nonstandard mode line (1600x900@60) */
//static display_mode sDisplayMode; //static display_mode sDisplayMode;
//sDisplayMode.timing.pixel_clock = 97750; //sDisplayMode.timing.pixel_clock = 97750;
//sDisplayMode.timing.h_display = 1600; //sDisplayMode.timing.h_display = 1600;

64
src/add-ons/accelerants/radeon_hd/mode.h
View File

@ -21,74 +21,10 @@
#define FMT1_REG_OFFSET 0x0000 #define FMT1_REG_OFFSET 0x0000
#define FMT2_REG_OFFSET 0x800 #define FMT2_REG_OFFSET 0x800
#define R6XX_CONFIG_FB_BASE 0x542C /* AKA CONFIG_F0_BASE */
status_t create_mode_list(void); status_t create_mode_list(void);
bool is_mode_supported(display_mode* mode); bool is_mode_supported(display_mode* mode);
status_t is_mode_sane(display_mode *mode); status_t is_mode_sane(display_mode *mode);
enum {
/* CRTC1 registers */
D1CRTC_H_TOTAL = 0x6000,
D1CRTC_H_BLANK_START_END = 0x6004,
D1CRTC_H_SYNC_A = 0x6008,
D1CRTC_H_SYNC_A_CNTL = 0x600C,
D1CRTC_H_SYNC_B = 0x6010,
D1CRTC_H_SYNC_B_CNTL = 0x6014,
D1CRTC_V_TOTAL = 0x6020,
D1CRTC_V_BLANK_START_END = 0x6024,
D1CRTC_V_SYNC_A = 0x6028,
D1CRTC_V_SYNC_A_CNTL = 0x602C,
D1CRTC_V_SYNC_B = 0x6030,
D1CRTC_V_SYNC_B_CNTL = 0x6034,
D1CRTC_CONTROL = 0x6080,
D1CRTC_BLANK_CONTROL = 0x6084,
D1CRTC_INTERLACE_CONTROL = 0x6088,
D1CRTC_BLACK_COLOR = 0x6098,
D1CRTC_STATUS = 0x609C,
D1CRTC_COUNT_CONTROL = 0x60B4,
/* D1GRPH registers */
D1GRPH_ENABLE = 0x6100,
D1GRPH_CONTROL = 0x6104,
D1GRPH_LUT_SEL = 0x6108,
D1GRPH_SWAP_CNTL = 0x610C,
D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110,
D1GRPH_SECONDARY_SURFACE_ADDRESS = 0x6118,
D1GRPH_PITCH = 0x6120,
D1GRPH_SURFACE_OFFSET_X = 0x6124,
D1GRPH_SURFACE_OFFSET_Y = 0x6128,
D1GRPH_X_START = 0x612C,
D1GRPH_Y_START = 0x6130,
D1GRPH_X_END = 0x6134,
D1GRPH_Y_END = 0x6138,
D1GRPH_UPDATE = 0x6144,
/* D1MODE */
D1MODE_DESKTOP_HEIGHT = 0x652C,
D1MODE_VLINE_START_END = 0x6538,
D1MODE_VLINE_STATUS = 0x653C,
D1MODE_VIEWPORT_START = 0x6580,
D1MODE_VIEWPORT_SIZE = 0x6584,
D1MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6588,
D1MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x658C,
D1MODE_DATA_FORMAT = 0x6528,
/* D1SCL */
D1SCL_ENABLE = 0x6590,
D1SCL_TAP_CONTROL = 0x6594,
D1MODE_CENTER = 0x659C, /* guess */
D1SCL_HVSCALE = 0x65A4, /* guess */
D1SCL_HFILTER = 0x65B0, /* guess */
D1SCL_VFILTER = 0x65C0, /* guess */
D1SCL_UPDATE = 0x65CC,
D1SCL_DITHER = 0x65D4, /* guess */
D1SCL_FLIP_CONTROL = 0x65D8 /* guess */
};
#endif /*RADEON_HD_MODE_H*/ #endif /*RADEON_HD_MODE_H*/

16
src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
View File

@ -19,6 +19,7 @@
#include <string.h> #include <string.h>
#include <errno.h> #include <errno.h>
#include <boot_item.h>
#include <driver_settings.h> #include <driver_settings.h>
#include <util/kernel_cpp.h> #include <util/kernel_cpp.h>
#include <vm/vm.h> #include <vm/vm.h>
@ -90,6 +91,21 @@ radeon_hd_init(radeon_info &info)
info.shared_info->physical_graphics_memory info.shared_info->physical_graphics_memory
= info.pci->u.h0.base_registers[RHD_FB_BAR]; = info.pci->u.h0.base_registers[RHD_FB_BAR];
// Pull active monitor VESA EDID from boot loader
edid1_info* edidInfo = (edid1_info*)get_boot_item(EDID_BOOT_INFO,
NULL);
if (edidInfo != NULL) {
TRACE((DEVICE_NAME ": %s found VESA EDID modes.\n", __func__));
info.shared_info->has_edid = true;
memcpy(&info.shared_info->edid_info, edidInfo, sizeof(edid1_info));
} else {
TRACE((DEVICE_NAME ": %s didn't find VESA EDID modes.\n", __func__));
info.shared_info->has_edid = false;
}
// Read R6XX memory size into shared info
//info.shared_info->graphics_memory_size = (uint32)read32(R6XX_CONFIG_MEMSIZE);
TRACE((DEVICE_NAME ": radeon_hd_init() completed successfully!\n")); TRACE((DEVICE_NAME ": radeon_hd_init() completed successfully!\n"));
return B_OK; return B_OK;
} }