perform port reset and wait for devices to be detected
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22293 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Marcus Overhagen
parent
be30f13184
commit
22cf14cfbe
@ -28,8 +28,8 @@ AHCIController::AHCIController(device_node_handle node, pci_device_info *device)
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{
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memset(fPort, 0, sizeof(fPort));
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ASSERT(sizeof(ahci_port) == 120);
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ASSERT(sizeof(ahci_hba) == 4096);
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ASSERT(sizeof(ahci_port) == 128);
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ASSERT(sizeof(ahci_hba) == 4352);
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ASSERT(sizeof(fis) == 256);
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ASSERT(sizeof(command_list_entry) == 32);
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ASSERT(sizeof(command_table) == 128);
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@ -144,19 +144,31 @@ AHCIController::Init()
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TRACE("out of memory creating port %d", i);
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break;
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}
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status_t status = fPort[i]->Init();
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status_t status = fPort[i]->Init1();
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if (status < B_OK) {
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TRACE("init port %d failed", i);
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TRACE("init-1 port %d failed", i);
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delete fPort[i];
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fPort[i] = NULL;
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break;
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}
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}
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}
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// enable interrupts
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fRegs->ghc |= GHC_IE;
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RegsFlush();
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FlushPostedWrites();
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for (int i = 0; i <= fPortCountMax; i++) {
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if (fPort[i]) {
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status_t status = fPort[i]->Init2();
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if (status < B_OK) {
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TRACE("init-2 port %d failed", i);
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fPort[i]->Uninit();
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delete fPort[i];
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fPort[i] = NULL;
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}
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}
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}
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return B_OK;
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@ -180,11 +192,11 @@ AHCIController::Uninit()
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// disable interrupts
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fRegs->ghc &= ~GHC_IE;
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RegsFlush();
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FlushPostedWrites();
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// clear pending interrupts
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fRegs->is = 0xffffffff;
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RegsFlush();
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FlushPostedWrites();
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// well...
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remove_io_interrupt_handler(fIRQ, Interrupt, this);
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@ -204,8 +216,9 @@ AHCIController::ResetController()
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uint32 saveCaps = fRegs->cap & (CAP_SMPS | CAP_SSS | CAP_SPM | CAP_EMS | CAP_SXS);
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uint32 savePI = fRegs->pi;
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#if 1
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fRegs->ghc |= GHC_HR;
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RegsFlush();
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FlushPostedWrites();
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for (int i = 0; i < 20; i++) {
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snooze(50000);
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if ((fRegs->ghc & GHC_HR) == 0)
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@ -213,12 +226,17 @@ AHCIController::ResetController()
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}
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if (fRegs->ghc & GHC_HR)
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return B_TIMED_OUT;
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#else
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fRegs->ghc &= ~GHC_AE;
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fRegs->is = 0xffffffff;
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FlushPostedWrites();
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#endif
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fRegs->ghc |= GHC_AE;
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RegsFlush();
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FlushPostedWrites();
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fRegs->cap |= saveCaps;
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fRegs->pi = savePI;
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RegsFlush();
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FlushPostedWrites();
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if (fPCIVendorID == 0x8086) {
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// Intel PCS—Port Control and Status
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@ -264,7 +282,7 @@ AHCIController::ExecuteRequest(scsi_ccb *request)
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return;
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}
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fPort[request->target_id]->ExecuteRequest(request);
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fPort[request->target_id]->ScsiExecuteRequest(request);
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}
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@ -274,7 +292,7 @@ AHCIController::AbortRequest(scsi_ccb *request)
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if (request->target_lun || !fPort[request->target_id])
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return SCSI_DEV_NOT_THERE;
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return fPort[request->target_id]->AbortRequest(request);
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return fPort[request->target_id]->ScsiAbortRequest(request);
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}
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@ -284,7 +302,7 @@ AHCIController::TerminateRequest(scsi_ccb *request)
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if (request->target_lun || !fPort[request->target_id])
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return SCSI_DEV_NOT_THERE;
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return fPort[request->target_id]->TerminateRequest(request);
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return fPort[request->target_id]->ScsiTerminateRequest(request);
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}
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@ -294,6 +312,6 @@ AHCIController::ResetDevice(uchar targetID, uchar targetLUN)
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if (targetLUN || !fPort[targetID])
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return SCSI_DEV_NOT_THERE;
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return fPort[targetID]->ResetDevice();
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return fPort[targetID]->ScsiResetDevice();
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}
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@ -29,7 +29,7 @@ public:
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private:
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bool IsDevicePresent(uint device);
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status_t ResetController();
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void RegsFlush();
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void FlushPostedWrites();
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static int32 Interrupt(void *data);
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@ -58,7 +58,7 @@ private:
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inline void
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AHCIController::RegsFlush()
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AHCIController::FlushPostedWrites()
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{
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volatile uint32 dummy = fRegs->ghc;
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dummy = dummy;
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@ -132,7 +132,7 @@ enum {
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PORT_INT_SDB | PORT_INT_DS | PORT_INT_PS | PORT_INT_DHR)
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enum {
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ATA_BUSY = 0x80,
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ATA_BSY = 0x80,
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ATA_DRQ = 0x08,
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ATA_ERR = 0x01,
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};
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@ -237,7 +237,7 @@ wait_until_set(volatile uint32 *reg, uint32 bits, bigtime_t timeout)
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{
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int trys = (timeout + 9999) / 10000;
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while (trys--) {
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if ((*reg & bits) == bits)
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if (((*reg) & bits) == bits)
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return B_OK;
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snooze(10000);
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}
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@ -250,7 +250,7 @@ wait_until_clear(volatile uint32 *reg, uint32 bits, bigtime_t timeout)
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{
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int trys = (timeout + 9999) / 10000;
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while (trys--) {
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if ((*reg & bits) == 0)
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if (((*reg) & bits) == 0)
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return B_OK;
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snooze(10000);
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}
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@ -29,9 +29,9 @@ AHCIPort::~AHCIPort()
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status_t
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AHCIPort::Init()
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AHCIPort::Init1()
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{
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TRACE("AHCIPort::Init port %d\n", fIndex);
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TRACE("AHCIPort::Init1 port %d\n", fIndex);
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size_t size = sizeof(command_list_entry) * COMMAND_LIST_ENTRY_COUNT + sizeof(fis) + sizeof(command_table) + sizeof(prd) * PRD_TABLE_ENTRY_COUNT;
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@ -67,7 +67,8 @@ AHCIPort::Init()
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fRegs->is = fRegs->is;
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// clear error bits
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fRegs->serr = fRegs->serr;
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// fRegs->serr = fRegs->serr;
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fRegs->serr = 0xffffffff;
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// spin up device
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fRegs->cmd |= PORT_CMD_SUD;
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@ -78,12 +79,39 @@ AHCIPort::Init()
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// enable FIS receive
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fRegs->cmd |= PORT_CMD_FER;
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FlushPostedWrites();
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return B_OK;
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}
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// called with global interrupts enabled
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status_t
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AHCIPort::Init2()
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{
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TRACE("AHCIPort::Init2 port %d\n", fIndex);
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// start DMA engine
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fRegs->cmd |= PORT_CMD_ST;
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// enable interrupts
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fRegs->ie = PORT_INT_MASK;
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FlushPostedWrites();
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// if (fRegs->sig == 0xffffffff)
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ResetDevice();
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PostResetDevice();
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TRACE("ie 0x%08lx\n", fRegs->ie);
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TRACE("is 0x%08lx\n", fRegs->is);
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TRACE("cmd 0x%08lx\n", fRegs->cmd);
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TRACE("ssts 0x%08lx\n", fRegs->ssts);
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TRACE("sctl 0x%08lx\n", fRegs->sctl);
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TRACE("serr 0x%08lx\n", fRegs->serr);
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TRACE("sact 0x%08lx\n", fRegs->sact);
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return B_OK;
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}
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@ -97,13 +125,7 @@ AHCIPort::Uninit()
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fRegs->cmd &= ~PORT_CMD_FER;
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// wait for receive completition, up to 500ms
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for (int i = 0; i < 15; i++) {
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if (!(fRegs->cmd & PORT_CMD_FR))
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break;
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snooze(50000);
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}
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if (fRegs->cmd & PORT_CMD_FR) {
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if (wait_until_clear(&fRegs->cmd, PORT_CMD_FR, 500000) < B_OK) {
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TRACE("AHCIPort::Uninit port %d error FIS rx still running\n", fIndex);
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}
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@ -111,13 +133,7 @@ AHCIPort::Uninit()
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fRegs->cmd &= ~PORT_CMD_ST;
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// wait for DMA completition
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for (int i = 0; i < 15; i++) {
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if (!(fRegs->cmd & PORT_CMD_CR))
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break;
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snooze(50000);
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}
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if (fRegs->cmd & PORT_CMD_CR) {
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if (wait_until_clear(&fRegs->cmd, PORT_CMD_CR, 500000) < B_OK) {
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TRACE("AHCIPort::Uninit port %d error DMA engine still running\n", fIndex);
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}
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@ -137,6 +153,84 @@ AHCIPort::Uninit()
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}
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status_t
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AHCIPort::ResetDevice()
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{
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TRACE("AHCIPort::ResetDevice port %d\n", fIndex);
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// stop DMA engine
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fRegs->cmd &= ~PORT_CMD_ST;
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FlushPostedWrites();
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if (wait_until_clear(&fRegs->cmd, PORT_CMD_CR, 500000) < B_OK) {
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TRACE("AHCIPort::ResetDevice port %d error DMA engine doesn't stop\n", fIndex);
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}
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// perform a hard reset
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fRegs->sctl = (fRegs->sctl & ~0xf) | 1;
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FlushPostedWrites();
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snooze(10000);
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fRegs->sctl &= ~0xf;
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FlushPostedWrites();
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if (wait_until_set(&fRegs->ssts, 0x1, 6000000) < B_OK) {
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TRACE("AHCIPort::ResetDevice port %d no device detected\n", fIndex);
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}
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// clear error bits
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// fRegs->serr = fRegs->serr;
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fRegs->serr = 0xffffffff;
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FlushPostedWrites();
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// start DMA engine
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fRegs->cmd |= PORT_CMD_ST;
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FlushPostedWrites();
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return B_OK;
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}
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status_t
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AHCIPort::PostResetDevice()
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{
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TRACE("AHCIPort::PostResetDevice port %d\n", fIndex);
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TRACE("tfd 1 0x%08lx\n", fRegs->tfd);
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// wait for DMA idle ?
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// if (wait_until_clear(&fRegs->cmd, PORT_CMD_CR, 1000000) < B_OK) {
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// TRACE("AHCIPort::PostResetDevice port %d error DMA engine doesn't stop\n", fIndex);
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// }
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switch (fRegs->tfd & 0xff) {
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case 0x7f:
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TRACE("no device present?\n");
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break;
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case 0xff:
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TRACE("invalid task file status 0xff\n");
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// fall through
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default:
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TRACE("waiting...\n");
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wait_until_clear(&fRegs->tfd, ATA_BSY | ATA_DRQ, 31000000);
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}
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if (fRegs->sig == 0xeb140101)
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fRegs->cmd |= PORT_CMD_ATAPI;
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else
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fRegs->cmd &= ~PORT_CMD_ATAPI;
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FlushPostedWrites();
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TRACE("device signature 0x%08lx (%s)\n", fRegs->sig,
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(fRegs->sig == 0xeb140101) ? "ATAPI" : (fRegs->sig == 0x00000101) ? "ATA" : "unknown");
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TRACE("tfd 0x%08lx\n", fRegs->tfd);
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TRACE("device detection: 0x%lx\n", fRegs->ssts & 0xf);
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return B_OK;
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}
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void
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AHCIPort::Interrupt()
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{
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@ -149,10 +243,11 @@ AHCIPort::Interrupt()
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void
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AHCIPort::ExecuteRequest(scsi_ccb *request)
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AHCIPort::ScsiExecuteRequest(scsi_ccb *request)
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{
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TRACE("AHCIPort::ExecuteRequest port %d, opcode %u, length %u\n", fIndex, request->cdb[0], request->cdb_length);
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TRACE("AHCIPort::ScsiExecuteRequest port %d, opcode %u, length %u\n", fIndex, request->cdb[0], request->cdb_length);
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request->subsys_status = SCSI_DEV_NOT_THERE;
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gSCSI->finished(request, 1);
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@ -164,7 +259,7 @@ AHCIPort::ExecuteRequest(scsi_ccb *request)
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uchar
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AHCIPort::AbortRequest(scsi_ccb *request)
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AHCIPort::ScsiAbortRequest(scsi_ccb *request)
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{
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return SCSI_REQ_CMP;
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@ -172,15 +267,14 @@ AHCIPort::AbortRequest(scsi_ccb *request)
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uchar
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AHCIPort::TerminateRequest(scsi_ccb *request)
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AHCIPort::ScsiTerminateRequest(scsi_ccb *request)
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{
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return SCSI_REQ_CMP;
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}
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uchar
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AHCIPort::ResetDevice()
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AHCIPort::ScsiResetDevice()
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{
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return SCSI_REQ_CMP;
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}
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@ -14,18 +14,22 @@ public:
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AHCIPort(AHCIController *controller, int index);
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~AHCIPort();
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status_t Init();
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status_t Init1();
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status_t Init2();
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void Uninit();
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void Interrupt();
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void ExecuteRequest(scsi_ccb *request);
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uchar AbortRequest(scsi_ccb *request);
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uchar TerminateRequest(scsi_ccb *request);
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uchar ResetDevice();
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void ScsiExecuteRequest(scsi_ccb *request);
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uchar ScsiAbortRequest(scsi_ccb *request);
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uchar ScsiTerminateRequest(scsi_ccb *request);
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uchar ScsiResetDevice();
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private:
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status_t ResetDevice();
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status_t PostResetDevice();
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void FlushPostedWrites();
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private:
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int fIndex;
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@ -38,4 +42,10 @@ private:
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volatile prd * fPRDTable;
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};
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inline void
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AHCIPort::FlushPostedWrites()
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{
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volatile uint32 dummy = fRegs->cmd;
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dummy = dummy;
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}
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#endif // _AHCI_PORT_H
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