Fix building the pci bus manager. Still quite stubbed out though.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26035 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
François Revol
parent
10a01828a1
commit
22531ab80f
@ -13,6 +13,20 @@
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#include "pci_controller.h"
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/*
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* Here we fake a PCI bus that maps the physical memory
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* (which is also I/O on 68k), and fake some system devices.
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* Some other devices are faked as ISA because they need DMA
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* notification.
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*
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* TODO: anything to be done to support VME cards ?
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* I don't think they are PnP at all anyway.
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*
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* TODO: On Hades/Milan clones a real PCI bus is accessible
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* through PAE-like extra bits in page descriptors. This one
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* should be handled in a separate file.
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*/
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//XXX:find one and put in shared priv header!
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// 0x68xx is free according to pci.ids
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// 68fx (f=fake) x = 0:amiga, 1:apple, 2:atari
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@ -28,7 +42,7 @@
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// default bist
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#define DB 0
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#define PEI {0}
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#define PEI 0
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#define INVV 0xffff //0x0000 ??
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#define INVD 0xffff
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@ -41,15 +55,20 @@ struct fake_pci_device {
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static struct fake_pci_device gFakePCIDevices[] = {
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{ {FAKEV, 0x0000, BN, 0, 0, 0, 0xff, PCI_host, PCI_bridge, DLL, DL, DB, 0, PEI }}, /* cpu */
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{ {FAKEV, 0x0001, BN, 1, 0, 0, 0xff, 0x68/*fake*/, PCI_processor, DLL, DL, DB, 0, PEI }}, /* cpu */
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{ {FAKEV, 0x0002, BN, 2, 0, 0, 0xff, PCI_display_other, PCI_display, DLL, DL, DB, 0, $FFFF8200, PEI }}, /* gfx */
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{ {FAKEV, 0x0003, BN, 3, 0, 0, 0xff, PCI_ide, PCI_mass_storage, DLL, DL, DB, 0, $FFF00000, PEI }}, /* ide */
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{ {FAKEV, 0x0002, BN, 2, 0, 0, 0xff, PCI_display_other, PCI_display, DLL, DL, DB, 0, 0xFFFF8200, PEI }}, /* gfx */
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{ {FAKEV, 0x0003, BN, 3, 0, 0, 0xff, PCI_ide, PCI_mass_storage, DLL, DL, DB, 0, 0xFFF00000, PEI }}, /* ide */
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{ {FAKEV, 0x0004, BN, 4, 0, 0, 0xff, PCI_scsi, PCI_mass_storage, DLL, DL, DB, 0, PEI }}, /* scsi */
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{ {FAKEV, 0x0005, BN, 5, 0, 0, 0xff, 0x, PCI_multimedia, DLL, DL, DB, 0x00, 0, $FFFF8900, PEI }}, /* snd */
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{ {FAKEV, 0x0005, BN, 5, 0, 0, 0xff, 0x0/*CHANGEME*/, PCI_multimedia, DLL, DL, DB, 0x00, 0, 0xFFFF8900, PEI }}, /* snd */
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//UART ?
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//centronics?
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{ {INVV, INVD} }
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};
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#define FAKE_DEVICES_COUNT ((sizeof(gFakePCIDevices)/sizeof(struct fake_pci_device)-1)
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#define FAKE_DEVICES_COUNT (sizeof(gFakePCIDevices)/sizeof(struct fake_pci_device)-1)
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struct m68k_atari_fake_host_bridge {
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uint32 bus;
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};
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#define out8rb(address, value) m68k_out8((vuint8*)(address), value)
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#define out16rb(address, value) m68k_out16_reverse((vuint16*)(address), value)
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@ -59,7 +78,7 @@ static struct fake_pci_device gFakePCIDevices[] = {
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#define in32rb(address) m68k_in32_reverse((const vuint32*)(address))
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static int m68k_atari_enable_config(struct m68k_atari_host_bridge *bridge,
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static int m68k_atari_enable_config(struct m68k_atari_fake_host_bridge *bridge,
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uint8 bus, uint8 slot, uint8 function, uint8 offset);
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static status_t m68k_atari_read_pci_config(void *cookie, uint8 bus, uint8 device,
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@ -102,7 +121,8 @@ m68k_atari_read_pci_config(void *cookie, uint8 bus, uint8 device, uint8 function
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if (size != s) { \
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panic("invalid pci config size %d for offset %d", size, offset); \
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return EINVAL; \
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*value = dev->n; \
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} \
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*value = dev->info.n; \
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return B_OK
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if (1) {
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@ -125,30 +145,33 @@ m68k_atari_read_pci_config(void *cookie, uint8 bus, uint8 device, uint8 function
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#define PCI_status 0x06 /* (2 byte) status */
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#endif
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if (dev->header_type == 0x00 || dev->header_type == 0x01) {
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if (dev->info.header_type == 0x00 || dev->info.header_type == 0x01) {
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switch (offset) {
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case PCI_base_registers:
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return EINVAL;
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O(PCI_interrupt_line, h0.interrupt_line, 1);
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O(PCI_interrupt_pin, h0.interrupt_pin, 1);
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default:
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break;
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O(PCI_interrupt_line, u.h0.interrupt_line, 1);
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O(PCI_interrupt_pin, u.h0.interrupt_pin, 1);
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default:
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break;
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}
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}
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if (dev->header_type == 0x00) {
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if (dev->info.header_type == 0x00) {
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switch (offset) {
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default:
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break;
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default:
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break;
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}
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}
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if (dev->header_type == 0x01) {
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if (dev->info.header_type == 0x01) {
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switch (offset) {
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O(PCI_primary_bus, h1.primary_bus, 1);
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O(PCI_secondary_bus, h1.secondary_bus, 1);
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O(PCI_subordinate_bus, h1.subordinate_bus, 1);
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O(PCI_secondary_latency, h1.secondary_latency, 1);
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default:
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break;
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O(PCI_primary_bus, u.h1.primary_bus, 1);
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O(PCI_secondary_bus, u.h1.secondary_bus, 1);
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O(PCI_subordinate_bus, u.h1.subordinate_bus, 1);
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O(PCI_secondary_latency, u.h1.secondary_latency, 1);
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default:
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break;
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}
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}
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*value = 0xffffffff;
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@ -158,7 +181,8 @@ m68k_atari_read_pci_config(void *cookie, uint8 bus, uint8 device, uint8 function
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}
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static status_t m68k_atari_write_pci_config(void *cookie, uint8 bus, uint8 device,
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static status_t
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m68k_atari_write_pci_config(void *cookie, uint8 bus, uint8 device,
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uint8 function, uint8 offset, uint8 size, uint32 value)
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{
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#if 0
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@ -181,27 +205,33 @@ static status_t m68k_atari_write_pci_config(void *cookie, uint8 bus, uint8 devic
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#endif
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panic("write pci config dev %d offset %d", device, offset);
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return B_ERROR;
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return B_OK;
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}
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static status_t m68k_atari_get_max_bus_devices(void *cookie, int32 *count)
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static status_t
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m68k_atari_get_max_bus_devices(void *cookie, int32 *count)
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{
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*count = 32;
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return B_OK;
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}
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static status_t m68k_atari_read_pci_irq(void *cookie, uint8 bus, uint8 device,
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static status_t
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m68k_atari_read_pci_irq(void *cookie, uint8 bus, uint8 device,
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uint8 function, uint8 pin, uint8 *irq)
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{
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#warning M68K: WRITEME
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return B_ERROR;
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}
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static status_t m68k_atari_write_pci_irq(void *cookie, uint8 bus, uint8 device,
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static status_t
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m68k_atari_write_pci_irq(void *cookie, uint8 bus, uint8 device,
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uint8 function, uint8 pin, uint8 irq)
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{
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#warning M68K: WRITEME
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return B_ERROR;
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}
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@ -210,35 +240,11 @@ static status_t m68k_atari_write_pci_irq(void *cookie, uint8 bus, uint8 device,
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static int
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m68k_atari_enable_config(struct m68k_atari_host_bridge *bridge, uint8 bus,
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m68k_atari_enable_config(struct m68k_atari_fake_host_bridge *bridge, uint8 bus,
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uint8 slot, uint8 function, uint8 offset)
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{
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// uint32 pass;
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// if (resource_int_value(device_get_name(sc->sc_dev),
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// device_get_unit(sc->sc_dev), "skipslot", &pass) == 0) {
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// if (pass == slot)
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// return (0);
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// }
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uint32 cfgval;
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if (bridge->bus == bus) {
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/*
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* No slots less than 11 on the primary bus
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*/
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if (slot < 11)
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return (0);
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cfgval = (1 << slot) | (function << 8) | (offset & 0xfc);
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} else {
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cfgval = (bus << 16) | (slot << 11) | (function << 8) |
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(offset & 0xfc) | 1;
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}
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do {
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out32rb(bridge->address_registers, cfgval);
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} while (in32rb(bridge->address_registers) != cfgval);
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return (1);
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#warning M68K: WRITEME
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return 0;
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}
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@ -250,9 +256,20 @@ m68k_atari_enable_config(struct m68k_atari_host_bridge *bridge, uint8 bus,
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status_t
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m68k_atari_pci_controller_init(void)
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{
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status_t error = pci_controller_add(&sM68kAtariPCIController, /*cookie*/);
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/* if (error != B_OK)
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free(bridge);*/
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struct m68k_atari_fake_host_bridge *bridge;
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bridge = (struct m68k_atari_fake_host_bridge *)
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malloc(sizeof(struct m68k_atari_fake_host_bridge));
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if (!bridge)
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return B_NO_MEMORY;
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bridge->bus = 0;
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status_t error = pci_controller_add(&sM68kAtariPCIController, bridge);
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if (error != B_OK)
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free(bridge);
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// TODO: probe Hades & Milan bridges
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return error;
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}
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