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intel_extreme: Cleanup pipe enablement ordering

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This commit is contained in:
Alexander von Gluck IV 2015-11-13 14:56:03 -06:00
parent fa45565eb7
commit 21e840d154
2 changed files with 13 additions and 3 deletions
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12
src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp
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@ -94,9 +94,6 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
return; return;
} }
// Enable display pipe
_Enable(true);
// Wait for the clocks to stabilize // Wait for the clocks to stabilize
spin(150); spin(150);
@ -123,6 +120,11 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_POS), 0); write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_POS), 0);
// This is useful for debugging: it sets the border to red, so you
// can see what is border and what is porch (black area around the
// sync)
//write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_RED), 0x00FF0000);
// TODO: Review these // TODO: Review these
write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE), write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE),
((uint32)(target->virtual_width - 1) << 16) ((uint32)(target->virtual_width - 1) << 16)
@ -138,6 +140,10 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
? DISPLAY_MONITOR_POSITIVE_HSYNC : 0) ? DISPLAY_MONITOR_POSITIVE_HSYNC : 0)
| ((target->timing.flags & B_POSITIVE_VSYNC) != 0 | ((target->timing.flags & B_POSITIVE_VSYNC) != 0
? DISPLAY_MONITOR_POSITIVE_VSYNC : 0)); ? DISPLAY_MONITOR_POSITIVE_VSYNC : 0));
// Enable display pipe
_Enable(true);
} }

4
src/add-ons/accelerants/intel_extreme/Ports.cpp
View File

@ -100,6 +100,10 @@ Port::AssignPipe(pipe_index pipeIndex)
if (fDisplayPipe == NULL) if (fDisplayPipe == NULL)
return B_NO_MEMORY; return B_NO_MEMORY;
// Disable display pipe until modesetting enables it
if (fDisplayPipe->IsEnabled())
fDisplayPipe->Disable();
read32(portRegister); read32(portRegister);
return B_OK; return B_OK;