intel_extreme: Cleanup pipe enablement ordering
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fa45565eb7
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21e840d154
@ -94,9 +94,6 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
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return;
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}
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// Enable display pipe
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_Enable(true);
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// Wait for the clocks to stabilize
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spin(150);
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@ -123,6 +120,11 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_POS), 0);
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// This is useful for debugging: it sets the border to red, so you
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// can see what is border and what is porch (black area around the
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// sync)
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//write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_RED), 0x00FF0000);
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// TODO: Review these
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE),
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((uint32)(target->virtual_width - 1) << 16)
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@ -138,6 +140,10 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
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? DISPLAY_MONITOR_POSITIVE_HSYNC : 0)
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| ((target->timing.flags & B_POSITIVE_VSYNC) != 0
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? DISPLAY_MONITOR_POSITIVE_VSYNC : 0));
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// Enable display pipe
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_Enable(true);
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}
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@ -100,6 +100,10 @@ Port::AssignPipe(pipe_index pipeIndex)
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if (fDisplayPipe == NULL)
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return B_NO_MEMORY;
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// Disable display pipe until modesetting enables it
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if (fDisplayPipe->IsEnabled())
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fDisplayPipe->Disable();
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read32(portRegister);
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return B_OK;
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