* On i865, the i915_GTT_BASE is not available. For some reason, though, the
method FreeBSD and Linux are using does not work here; I didn't find out why, but I've added a fallback method to use the known GTT base then. * This should fix #2764. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@29060 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -1,5 +1,5 @@
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/*
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* Copyright 2008, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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* Copyright 2008-2009, Axel Dörfler, axeld@pinc-software.de.
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* Distributed under the terms of the MIT License.
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*/
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@ -81,7 +81,7 @@ struct intel_info {
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size_t gtt_entries;
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size_t gtt_stolen_entries;
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uint32 *registers;
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vuint32 *registers;
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area_id registers_area;
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addr_t aperture_base;
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@ -233,17 +233,6 @@ intel_unmap(intel_info &info)
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static status_t
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intel_map(intel_info &info)
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{
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info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4);
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size_t gttSize, stolenSize;
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determine_memory_sizes(info, gttSize, stolenSize);
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info.gtt_entries = gttSize / 4096;
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info.gtt_stolen_entries = stolenSize / 4096;
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TRACE("GTT base %lx, size %lu, entries %lu, stolen %lu\n", info.gtt_physical_base,
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gttSize, info.gtt_entries, stolenSize);
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int fbIndex = 0;
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int mmioIndex = 1;
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if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
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@ -253,15 +242,6 @@ intel_map(intel_info &info)
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fbIndex = 2;
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}
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AreaKeeper gttMapper;
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info.gtt_area = gttMapper.Map("intel GMCH gtt",
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(void *)info.gtt_physical_base, gttSize, B_ANY_KERNEL_ADDRESS,
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B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void **)&info.gtt_base);
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if (gttMapper.InitCheck() < B_OK) {
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dprintf("agp_intel: could not map GTT!\n");
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return info.gtt_area;
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}
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AreaKeeper mmioMapper;
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info.registers_area = mmioMapper.Map("intel GMCH mmio",
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(void *)info.display.u.h0.base_registers[mmioIndex],
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@ -272,6 +252,11 @@ intel_map(intel_info &info)
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return info.registers_area;
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}
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// make sure bus master, memory-mapped I/O, and frame buffer is enabled
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set_pci_config(info.display, PCI_command, 2,
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get_pci_config(info.display, PCI_command, 2)
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| PCI_command_io | PCI_command_memory | PCI_command_master);
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void *scratchAddress;
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AreaKeeper scratchCreator;
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info.scratch_area = scratchCreator.Create("intel GMCH scratch",
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@ -286,14 +271,46 @@ intel_map(intel_info &info)
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if (get_memory_map(scratchAddress, B_PAGE_SIZE, &entry, 1) != B_OK)
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return B_ERROR;
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if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx)
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info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4);
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else {
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info.gtt_physical_base = read32(info.registers
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+ INTEL_PAGE_TABLE_CONTROL) & ~PAGE_TABLE_ENABLED;
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if (info.gtt_physical_base == 0) {
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// TODO: not sure how this is supposed to work under Linux/FreeBSD,
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// but on my i865, this code is needed for Haiku.
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dprintf("intel_gart: Use GTT address fallback.\n");
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info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex]
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+ i830_GTT_BASE;
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}
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}
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size_t gttSize, stolenSize;
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determine_memory_sizes(info, gttSize, stolenSize);
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info.gtt_entries = gttSize / 4096;
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info.gtt_stolen_entries = stolenSize / 4096;
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TRACE("GTT base %lx, size %lu, entries %lu, stolen %lu\n", info.gtt_physical_base,
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gttSize, info.gtt_entries, stolenSize);
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AreaKeeper gttMapper;
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info.gtt_area = gttMapper.Map("intel GMCH gtt",
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(void *)info.gtt_physical_base, gttSize, B_ANY_KERNEL_ADDRESS,
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B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void **)&info.gtt_base);
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if (gttMapper.InitCheck() < B_OK) {
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dprintf("intel_gart: could not map GTT!\n");
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return info.gtt_area;
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}
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info.aperture_physical_base = info.display.u.h0.base_registers[fbIndex];
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info.aperture_stolen_size = stolenSize;
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if (info.aperture_size == 0)
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info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex];
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dprintf("intel_gart: detected %ld MB of stolen memory, aperture size %ld "
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"MB, GTT size %ld KB\n", stolenSize >> 20, info.aperture_size >> 20,
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gttSize >> 10);
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dprintf("intel_gart: detected %ld MB of stolen memory, aperture "
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"size %ld MB, GTT size %ld KB\n", (stolenSize + (1023 << 10)) >> 20,
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info.aperture_size >> 20, gttSize >> 10);
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AreaKeeper apertureMapper;
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info.aperture_area = apertureMapper.Map("intel graphics aperture",
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@ -348,7 +365,7 @@ intel_create_aperture(uint8 bus, uint8 device, uint8 function, size_t size,
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INTEL_GRAPHICS_MEMORY_CONTROL, 2) | MEMORY_CONTROL_ENABLED;
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set_pci_config(sInfo.bridge, INTEL_GRAPHICS_MEMORY_CONTROL, 2, gmchControl);
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write32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL,
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write32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL,
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sInfo.gtt_physical_base | PAGE_TABLE_ENABLED);
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read32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL);
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@ -398,7 +415,7 @@ intel_set_aperture_size(void *aperture, size_t size)
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static status_t
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intel_bind_page(void *aperture, uint32 offset, addr_t physicalAddress)
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{
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TRACE("bind_page(offset %lx, physical %lx)\n", offset, physicalAddress);
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//TRACE("bind_page(offset %lx, physical %lx)\n", offset, physicalAddress);
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set_gtt_entry(sInfo, offset, physicalAddress);
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return B_OK;
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@ -408,7 +425,7 @@ intel_bind_page(void *aperture, uint32 offset, addr_t physicalAddress)
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static status_t
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intel_unbind_page(void *aperture, uint32 offset)
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{
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TRACE("unbind_page(offset %lx)\n", offset);
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//TRACE("unbind_page(offset %lx)\n", offset);
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if (sInfo.scratch_page != 0)
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set_gtt_entry(sInfo, offset, sInfo.scratch_page);
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