diff --git a/src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp b/src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp
index ee1ccbf9ba..e9f23846fd 100644
--- a/src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp
+++ b/src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp
@@ -86,6 +86,15 @@ AHCIController::Init()
 	TRACE("pcicmd new 0x%04x\n", pcicmd);
 	gPCI->write_pci_config(fPCIDevice, PCI_command, 2, pcicmd);
 
+	if (fPCIVendorID == PCI_VENDOR_JMICRON) {
+		uint32 ctrl = gPCI->read_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4);
+		TRACE("Jmicron controller control 1 old 0x%08lx\n", ctrl);
+		ctrl &= ~((1 << 9) | (1 << 12) | (1 << 14));	// disable SFF 8038i emulation
+		ctrl |= (1 << 8) | (1 << 13) | (1 << 15);		// enable AHCI controller
+		TRACE("Jmicron controller control 1 new 0x%08lx\n", ctrl);
+		gPCI->write_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4, ctrl);
+	}
+
 	void *addr = (void *)pciInfo.u.h0.base_registers[5];
 	size_t size = pciInfo.u.h0.base_register_sizes[5];
 
@@ -243,7 +252,7 @@ AHCIController::ResetController()
 	fRegs->pi = savePI;
 	FlushPostedWrites();
 
-	if (fPCIVendorID == 0x8086) {
+	if (fPCIVendorID == PCI_VENDOR_INTEL) {
 		// Intel PCS—Port Control and Status
 		// In AHCI enabled systems, bits[3:0] must always be set
 		gPCI->write_pci_config(fPCIDevice, 0x92, 2, 
diff --git a/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h b/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h
index fe8768e233..28b7ae6045 100644
--- a/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h
+++ b/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h
@@ -223,6 +223,10 @@ extern scsi_for_sim_interface *gSCSI;
 #define PCI_PCICMD_MSE	0x02
 #define PCI_PCICMD_BME	0x04
 
+#define PCI_VENDOR_INTEL	0x8086
+#define PCI_VENDOR_JMICRON	0x197b
+#define PCI_JMICRON_CONTROLLER_CONTROL_1	0x40
+
 #ifdef __cplusplus
 
 template <class T>