* Make the operational register memory a uint8 * instead of a uint32 * so the
driver has at least a chance of working (it previously always used wrong offsets for register access). * Remove the hash approach for now (I'm going to explore a few other ways of doing that first). * Reorder some stuff and check for errors in some more places. * More cleanup (mostly whitespace again). git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25538 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz
parent
2b9cc6d877
commit
20bbb1bf28
@ -77,8 +77,6 @@ OHCI::OHCI(pci_info *info, Stack *stack)
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fFinishTransfersSem(-1),
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fFinishThread(-1),
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fStopFinishThread(false),
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fHashGenericTable(NULL),
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fHashIsochronousTable(NULL),
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fRootHub(NULL),
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fRootHubAddress(0),
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fPortCount(0)
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@ -138,35 +136,17 @@ OHCI::OHCI(pci_info *info, Stack *stack)
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memset(fHcca, 0, sizeof(ohci_hcca));
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// Allocate hash tables
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fHashGenericTable = (ohci_general_td **)
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malloc(sizeof(ohci_general_td *) * OHCI_HASH_SIZE);
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if (fHashGenericTable == NULL) {
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TRACE_ERROR(("usb_ohci: unable to allocate hash generic table\n"));
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return;
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}
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fHashIsochronousTable = (ohci_isochronous_td **)
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malloc(sizeof(ohci_isochronous_td *) * OHCI_HASH_SIZE);
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if (fHashIsochronousTable == NULL) {
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free(fHashGenericTable);
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TRACE_ERROR(("usb_ohci: unable to allocate hash isochronous table\n"));
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return;
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}
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// Set Up Host controller
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// Dummy endpoints
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fDummyControl = _AllocateEndpoint();
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if (!fDummyControl)
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return;
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fDummyControl->flags |= OHCI_ENDPOINT_SKIP;
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fDummyBulk = _AllocateEndpoint();
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if (!fDummyBulk) {
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_FreeEndpoint(fDummyControl);
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return;
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}
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fDummyBulk->flags |= OHCI_ENDPOINT_SKIP;
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fDummyIsochronous = _AllocateEndpoint();
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if (!fDummyIsochronous) {
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@ -174,7 +154,6 @@ OHCI::OHCI(pci_info *info, Stack *stack)
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_FreeEndpoint(fDummyBulk);
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return;
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}
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fDummyIsochronous->flags |= OHCI_ENDPOINT_SKIP;
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// Static endpoints that get linked in the HCCA
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fInterruptEndpoints = new(std::nothrow)
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@ -202,7 +181,6 @@ OHCI::OHCI(pci_info *info, Stack *stack)
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}
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// Make them point all to the dummy isochronous endpoint
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fInterruptEndpoints[i]->flags |= OHCI_ENDPOINT_SKIP;
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fInterruptEndpoints[i]->next_physical_endpoint
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= fDummyIsochronous->physical_address;
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}
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@ -341,9 +319,6 @@ OHCI::~OHCI()
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if (fRegisterArea >= B_OK)
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delete_area(fRegisterArea);
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free(fHashGenericTable);
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free(fHashIsochronousTable);
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_FreeEndpoint(fDummyControl);
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_FreeEndpoint(fDummyBulk);
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_FreeEndpoint(fDummyIsochronous);
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@ -365,9 +340,11 @@ OHCI::Start()
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{
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TRACE(("usb_ohci: starting OHCI Host Controller\n"));
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if ((_ReadReg(OHCI_CONTROL) & OHCI_HC_FUNCTIONAL_STATE_MASK)
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uint32 control = _ReadReg(OHCI_CONTROL);
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if ((control & OHCI_HC_FUNCTIONAL_STATE_MASK)
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!= OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL) {
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TRACE_ERROR(("usb_ohci: Controller not started!\n"));
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TRACE_ERROR(("usb_ohci: Controller not started (0x%08lx)!\n",
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control));
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return B_ERROR;
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} else
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TRACE(("usb_ohci: Controller is operational!\n"));
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@ -578,7 +555,7 @@ OHCI::AddTo(Stack *stack)
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status_t
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OHCI::GetPortStatus(uint8 index, usb_port_status *status)
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{
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TRACE(("usb_ohci::%s(%ud, )\n", __FUNCTION__, index));
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TRACE(("usb_ohci: get port status %ud\n", index));
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if (index >= fPortCount)
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return B_BAD_INDEX;
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@ -857,7 +834,7 @@ OHCI::_FinishTransfers()
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ohci_isochronous_td *isoCurrent = NULL;
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ohci_isochronous_td *isoTop = NULL;
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while (doneList != 0) {
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current = _FindDescriptorInHash(doneList);
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current = NULL; //_FindDescriptorInHash(doneList);
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if (current != NULL) {
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doneList = current->next_physical_descriptor;
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current->next_done_descriptor = (void *)top;
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@ -865,7 +842,7 @@ OHCI::_FinishTransfers()
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continue;
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}
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isoCurrent = _FindIsoDescriptorInHash(doneList);
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isoCurrent = NULL; //_FindIsoDescriptorInHash(doneList);
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if (isoCurrent != NULL) {
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doneList = isoCurrent->next_physical_descriptor;
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isoCurrent->next_done_descriptor = (void *)isoTop;
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@ -1135,11 +1112,14 @@ OHCI::_AllocateEndpoint()
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return NULL;
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}
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endpoint->flags = OHCI_ENDPOINT_SKIP;
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endpoint->physical_address = (addr_t)physicalAddress;
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endpoint->head_logical_descriptor = NULL;
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endpoint->head_physical_descriptor = 0;
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endpoint->tail_logical_descriptor = NULL;
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endpoint->tail_physical_descriptor = 0;
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endpoint->next_logical_endpoint = NULL;
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endpoint->next_physical_endpoint = 0;
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return endpoint;
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}
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@ -1214,27 +1194,32 @@ OHCI::_InsertEndpointForPipe(Pipe *pipe)
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endpoint->flags = flags;
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// Add the endpoint to the appropriate list
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ohci_endpoint_descriptor *head = NULL;
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uint32 type = pipe->Type();
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ohci_endpoint_descriptor *head = NULL;
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if (type & USB_OBJECT_CONTROL_PIPE)
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head = fDummyControl;
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else if (type & USB_OBJECT_BULK_PIPE)
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head = fDummyBulk;
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else if (type & USB_OBJECT_INTERRUPT_PIPE)
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head = _FindInterruptEndpoint(pipe->Interval());
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else if (type & USB_OBJECT_ISO_PIPE) {
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// Set the isochronous bit format
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endpoint->flags |= OHCI_ENDPOINT_ISOCHRONOUS_FORMAT;
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else if (type & USB_OBJECT_ISO_PIPE)
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head = fDummyIsochronous;
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} else {
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else
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TRACE_ERROR(("usb_ohci: unknown pipe type\n"));
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if (head == NULL) {
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TRACE_ERROR(("usb_ohci: no list found for endpoint\n"));
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_FreeEndpoint(endpoint);
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return B_BAD_VALUE;
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return B_ERROR;
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}
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// Create (necessary) dummy descriptor
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if (pipe->Type() & USB_OBJECT_ISO_PIPE) {
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// Set the isochronous bit format
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endpoint->flags |= OHCI_ENDPOINT_ISOCHRONOUS_FORMAT;
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// TODO
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_FreeEndpoint(endpoint);
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return B_ERROR;
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} else {
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ohci_general_td *dummy = _CreateGeneralDescriptor(0);
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dummy->next_logical_descriptor = NULL;
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@ -1245,15 +1230,23 @@ OHCI::_InsertEndpointForPipe(Pipe *pipe)
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endpoint->tail_physical_descriptor = dummy->physical_address;
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}
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// TODO: Change lock lo LockEndpoint()
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Lock();
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if (!Lock()) {
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if (endpoint->head_logical_descriptor) {
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_FreeGeneralDescriptor(
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(ohci_general_td *)endpoint->head_logical_descriptor);
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}
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_FreeEndpoint(endpoint);
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return B_ERROR;
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}
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pipe->SetControllerCookie((void *)endpoint);
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endpoint->next_logical_endpoint = head->next_logical_endpoint;
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endpoint->next_physical_endpoint = head->next_physical_endpoint;
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head->next_logical_endpoint = (void *)endpoint;
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head->next_physical_endpoint = (uint32)endpoint->physical_address;
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Unlock();
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Unlock();
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return B_OK;
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}
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@ -1422,50 +1415,6 @@ OHCI::_FreeIsochronousDescriptor(ohci_isochronous_td *descriptor)
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}
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void
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OHCI::_AddDescriptorToHash(ohci_general_td *descriptor)
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{
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// TODO
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}
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void
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OHCI::_RemoveDescriptorFromHash(ohci_general_td *descriptor)
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{
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// TODO
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}
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ohci_general_td*
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OHCI::_FindDescriptorInHash(uint32 physicalAddress)
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{
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// TODO
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return NULL;
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}
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void
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OHCI::_AddIsoDescriptorToHash(ohci_isochronous_td *descriptor)
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{
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// TODO
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}
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void
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OHCI::_RemoveIsoDescriptorFromHash(ohci_isochronous_td *descriptor)
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{
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// TODO
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}
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ohci_isochronous_td*
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OHCI::_FindIsoDescriptorInHash(uint32 physicalAddress)
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{
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// TODO
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return NULL;
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}
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inline void
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OHCI::_WriteReg(uint32 reg, uint32 value)
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{
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@ -3,8 +3,9 @@
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Jan-Rixt Van Hoye
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* Salvatore Benedetto <salvatore.benedetto@gmail.com>
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* Jan-Rixt Van Hoye
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* Salvatore Benedetto <salvatore.benedetto@gmail.com>
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* Michael Lotz <mmlr@mlotz.ch>
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*/
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#ifndef OHCI_H
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@ -28,49 +29,14 @@ typedef struct transfer_data_s {
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transfer_data_s *link;
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} transfer_data;
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// --------------------------------------
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// OHCI:: Software isonchronous
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// transfer descriptor
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// --------------------------------------
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typedef struct hcd_soft_itransfer
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{
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ohci_isochronous_td itd;
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struct hcd_soft_itransfer *nextitd; // mirrors nexttd in ITD
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struct hcd_soft_itransfer *dnext; // next in done list
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addr_t physaddr; // physical address to the host controller isonchronous transfer
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//LIST_ENTRY(hcd_soft_itransfer) hnext;
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uint16 flags; // flags
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#ifdef DIAGNOSTIC
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char isdone; // is the transfer done?
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#endif
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}hcd_soft_itransfer;
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#define OHCI_SITD_SIZE ((sizeof (struct hcd_soft_itransfer) + OHCI_ITD_ALIGN - 1) / OHCI_ITD_ALIGN * OHCI_ITD_ALIGN)
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#define OHCI_SITD_CHUNK 64
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#define OHCI_NUMBER_OF_ENDPOINTS (2 * OHCI_NUMBER_OF_INTERRUPTS - 1)
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// Note: the controller returns only the physical
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// address of the first processed descriptor of
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// an heterogeneous list (isochronous + generic). Unfortunately
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// we don't have a way to know whether the descriptor is
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// generic or isochronous, either way to translate the address back to
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// kernel address. The physical address is used as the hash value.
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// (Kindly borrowed from *BSD)
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#define OHCI_HASH_SIZE 128
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#define HASH(x) (((x) >> 4) % OHCI_HASH_SIZE)
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class OHCI : public BusManager
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{
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class OHCI : public BusManager {
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public:
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OHCI(pci_info *info, Stack *stack);
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~OHCI();
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status_t Start();
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virtual status_t SubmitTransfer(Transfer *transfer);
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virtual status_t SubmitTransfer(Transfer *transfer);
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virtual status_t CancelQueuedTransfers(Pipe *pipe,
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bool force);
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@ -80,8 +46,8 @@ virtual status_t NotifyPipeChange(Pipe *pipe,
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static status_t AddTo(Stack *stack);
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// Port operations
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uint8 PortCount() { return fPortCount; };
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status_t GetPortStatus(uint8 index,
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uint8 PortCount() { return fPortCount; };
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status_t GetPortStatus(uint8 index,
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usb_port_status *status);
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status_t SetPortFeature(uint8 index, uint16 feature);
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status_t ClearPortFeature(uint8 index, uint16 feature);
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@ -152,31 +118,15 @@ static int32 _FinishThread(void *data);
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void _FreeIsochronousDescriptor(
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ohci_isochronous_td *descriptor);
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// Hash tables related methods
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void _AddDescriptorToHash(
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ohci_general_td *descriptor);
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void _RemoveDescriptorFromHash(
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ohci_general_td *descriptor);
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ohci_general_td *_FindDescriptorInHash(
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uint32 physicalAddress);
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void _AddIsoDescriptorToHash(
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ohci_isochronous_td *descriptor);
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void _RemoveIsoDescriptorFromHash(
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ohci_isochronous_td *descriptor);
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ohci_isochronous_td *_FindIsoDescriptorInHash(
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uint32 physicalAddress);
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// Register functions
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inline void _WriteReg(uint32 reg, uint32 value);
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inline uint32 _ReadReg(uint32 reg);
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static pci_module_info *sPCIModule;
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pci_info *fPCIInfo;
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pci_info *fPCIInfo;
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Stack *fStack;
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uint32 *fOperationalRegisters;
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uint8 *fOperationalRegisters;
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area_id fRegisterArea;
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// Host Controller Communication Area related stuff
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@ -196,12 +146,8 @@ static pci_module_info *sPCIModule;
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thread_id fFinishThread;
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bool fStopFinishThread;
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// Hash table
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ohci_general_td **fHashGenericTable;
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ohci_isochronous_td **fHashIsochronousTable;
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// Root Hub
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OHCIRootHub *fRootHub;
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OHCIRootHub *fRootHub;
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uint8 fRootHubAddress;
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// Port management
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@ -214,7 +160,7 @@ public:
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OHCIRootHub(Object *rootObject,
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int8 deviceAddress);
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static status_t ProcessTransfer(OHCI *ohci,
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static status_t ProcessTransfer(OHCI *ohci,
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Transfer *transfer);
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};
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@ -5,6 +5,7 @@
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* Authors:
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* Jan-Rixt Van Hoye
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* Salvatore Benedetto <salvatore.benedetto@gmail.com>
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* Michael Lotz <mmlr@mlotz.ch>
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*/
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#ifndef OHCI_HARDWARE_H
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@ -271,15 +272,14 @@
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#define OHCI_NUMBER_OF_INTERRUPTS 32
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typedef struct ohci_hcca
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{
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typedef struct {
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uint32 interrupt_table[OHCI_NUMBER_OF_INTERRUPTS];
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uint32 current_frame_number;
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uint32 done_head;
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// The following is 120 instead of 116 because the spec
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// only specifies 252 bytes
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uint8 reserved_for_hc[120];
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};
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} ohci_hcca;
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#define OHCI_DONE_INTERRUPTS 1
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#define OHCI_HCCA_SIZE 256
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@ -292,20 +292,18 @@ typedef struct ohci_hcca
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// Endpoint descriptor structure (section 4.2)
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// --------------------------------
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typedef struct ohci_endpoint_descriptor
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{
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typedef struct {
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// Hardware part
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uint32 flags; // Flags field
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uint32 tail_physical_descriptor; // Queue tail physical pointer
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uint32 head_physical_descriptor; // Queue head physical pointer
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uint32 next_physical_endpoint; // Physical pointer to the next endpoint
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// Software part
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// TODO: What about type, state and interval (only interrupts) ?
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addr_t physical_address; // Physical pointer to this address
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void *tail_logical_descriptor; // Queue tail logical pointer
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void *head_logical_descriptor; // Queue head logical pointer
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void *next_logical_endpoint; // Logical pointer to the next endpoint
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};
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} ohci_endpoint_descriptor;
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#define OHCI_ENDPOINT_ADDRESS_MASK 0x0000007f
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#define OHCI_ENDPOINT_GET_DEVICE_ADDRESS(s) ((s) & 0x7f)
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@ -333,8 +331,7 @@ typedef struct ohci_endpoint_descriptor
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// General transfer descriptor structure (section 4.3.1)
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// --------------------------------
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typedef struct ohci_general_td
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{
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typedef struct {
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// Hardware part 16 bytes
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uint32 flags; // Flags field
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uint32 buffer_physical; // Physical buffer pointer
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@ -348,7 +345,7 @@ typedef struct ohci_general_td
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size_t buffer_size; // Size of the buffer
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void *transfer; // Pointer to the transfer_data
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bool is_last; // Last descriptor of the transfer
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};
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} ohci_general_td;
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#define OHCI_BUFFER_ROUNDING 0x00040000
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#define OHCI_TD_DIRECTION_PID_MASK 0x00180000
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@ -374,8 +371,7 @@ typedef struct ohci_general_td
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// --------------------------------
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#define OHCI_ITD_NOFFSET 8
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typedef struct ohci_isochronous_td
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{
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typedef struct {
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// Hardware part 32 byte
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uint32 flags;
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uint32 buffer_page_byte_0; // Physical page number of byte 0
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@ -386,7 +382,7 @@ typedef struct ohci_isochronous_td
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addr_t physical_address; // Physical address of this descriptor
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void *next_logical_descriptor; // Logical pointer next descriptor
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void *next_done_descriptor; // Used for collision in the hash table
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};
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} ohci_isochronous_td;
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#define OHCI_ITD_GET_STARTING_FRAME(x) ((x) & 0x0000ffff)
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#define OHCI_ITD_SET_STARTING_FRAME(x) ((x) & 0xffff)
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