Refactored MTRR code a bit: there is now a generic base that is used by
all CPU specific implementations as much as possible. AMD and Intel are now separated again, even though they are currently equivalent besides the CPU vendor detection. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15567 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
parent
d0d37bdfd1
commit
2058e6c1d4
@ -4,7 +4,7 @@ UsePrivateHeaders kernel ;
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KernelAddon generic_x86 : kernel cpu :
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generic_x86.cpp
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amd.cpp
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intel.cpp
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# amd.cpp
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via.cpp
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;
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@ -8,26 +8,15 @@
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#include "amd.h"
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#include "generic_x86.h"
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#include <OS.h>
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static uint32
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amd_count_mtrrs(void)
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static void
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amd_init_mtrrs(void)
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{
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return 0;
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}
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static status_t
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amd_set_mtrr(uint32 index, addr_t base, addr_t length, uint32 type)
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{
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return B_OK;
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}
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static status_t
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amd_unset_mtrr(uint32 index)
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{
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return B_OK;
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generic_init_mtrrs(generic_count_mtrrs());
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}
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@ -41,13 +30,9 @@ amd_init(void)
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if ((info.cpu_type & B_CPU_x86_VENDOR_MASK) != B_CPU_AMD_x86)
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return B_ERROR;
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return B_OK;
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}
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generic_mtrr_compute_physical_mask();
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generic_dump_mtrrs(generic_count_mtrrs());
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static status_t
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amd_uninit(void)
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{
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return B_OK;
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}
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@ -59,7 +44,7 @@ amd_stdops(int32 op, ...)
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case B_MODULE_INIT:
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return amd_init();
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case B_MODULE_UNINIT:
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return amd_uninit();
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return B_OK;
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}
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return B_ERROR;
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@ -73,7 +58,9 @@ x86_cpu_module_info gAMDModule = {
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amd_stdops,
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},
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amd_count_mtrrs,
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amd_set_mtrr,
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amd_unset_mtrr,
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generic_count_mtrrs,
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amd_init_mtrrs,
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generic_set_mtrr,
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generic_get_mtrr,
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};
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@ -7,14 +7,170 @@
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*/
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#include "generic_x86.h"
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#include "intel.h"
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#include "amd.h"
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#include "via.h"
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//#define TRACE_MTRR
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#ifdef TRACE_MTRR
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# define TRACE(x) dprintf x
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#else
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# define TRACE(x) ;
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#endif
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#define IA32_MTRR_ENABLE (1UL << 11)
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#define IA32_MTRR_ENABLE_FIXED (1UL << 10)
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#define IA32_MTRR_VALID_RANGE (1UL << 11)
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struct mtrr_capabilities {
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mtrr_capabilities(uint64 value) { *(uint64 *)this = value; }
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uint64 variable_ranges : 8;
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uint64 supports_fixed : 1;
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uint64 _reserved0 : 1;
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uint64 supports_write_combined : 1;
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uint64 _reserved1 : 53;
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};
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uint64 gPhysicalMask = 0;
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uint32
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generic_count_mtrrs(void)
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{
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cpuid_info cpuInfo;
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if (get_cpuid(&cpuInfo, 1, 0) != B_OK
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|| (cpuInfo.eax_1.features & IA32_FEATURE_MTRR) == 0)
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return 0;
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mtrr_capabilities capabilities(x86_read_msr(IA32_MSR_MTRR_CAPABILITIES));
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TRACE(("cpu has %ld variable range MTRs.\n", capabilities.variable_ranges));
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return capabilities.variable_ranges;
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}
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void
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generic_init_mtrrs(uint32 count)
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{
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// disable and clear all MTRRs
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// (we leave the fixed MTRRs as is)
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// TODO: check if the fixed MTRRs are set on all CPUs identically?
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x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE,
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x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE) & ~IA32_MTRR_ENABLE);
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for (uint32 i = count; i-- > 0;) {
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if (x86_read_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + i * 2) & IA32_MTRR_VALID_RANGE)
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + i * 2, 0);
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}
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// but turn on variable MTRR functionality
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x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE,
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x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE) | IA32_MTRR_ENABLE);
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}
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void
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generic_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type)
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{
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index *= 2;
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// there are two registers per slot
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uint64 mask = length - 1;
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mask = ~mask & gPhysicalMask;
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TRACE(("MTRR %ld: new mask %Lx)\n", index, mask));
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TRACE((" mask test base: %Lx)\n", mask & base));
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TRACE((" mask test middle: %Lx)\n", mask & (base + length / 2)));
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TRACE((" mask test end: %Lx)\n", mask & (base + length)));
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// First, disable MTRR
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index, 0);
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if (base != 0 || mask != 0 || type != 0) {
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// then fill in the new values, and enable it again
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index,
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(base & ~(B_PAGE_SIZE - 1)) | type);
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index,
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mask | IA32_MTRR_VALID_RANGE);
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} else {
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// reset base as well
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index, 0);
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}
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}
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status_t
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generic_get_mtrr(uint32 index, uint64 *_base, uint64 *_length, uint8 *_type)
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{
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uint64 mask = x86_read_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index * 2);
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if ((mask & IA32_MTRR_VALID_RANGE) == 0)
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return B_ERROR;
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uint64 base = x86_read_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index * 2);
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*_base = base & ~(B_PAGE_SIZE - 1);
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*_length = (~mask & gPhysicalMask) + 1;
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*_type = base & 0xff;
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return B_OK;
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}
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status_t
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generic_mtrr_compute_physical_mask(void)
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{
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uint32 bits = 36;
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cpuid_info cpuInfo;
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if (get_cpuid(&cpuInfo, 0x80000000, 0) == B_OK
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&& cpuInfo.eax_0.max_eax & 0xff >= 8) {
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get_cpuid(&cpuInfo, 0x80000008, 0);
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bits = cpuInfo.regs.eax & 0xff;
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}
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gPhysicalMask = ((1ULL << bits) - 1) & ~(B_PAGE_SIZE - 1);
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TRACE(("CPU has %ld physical address bits, physical mask is %016Lx\n",
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bits, gPhysicalMask));
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return B_OK;
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}
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void
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generic_dump_mtrrs(uint32 count)
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{
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if (x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE) & IA32_MTRR_ENABLE) {
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TRACE(("MTRR enabled\n"));
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} else {
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TRACE(("MTRR disabled\n"));
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}
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for (uint32 i = 0; i < count; i++) {
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uint64 base;
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uint64 length;
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uint8 type;
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if (generic_get_mtrr(i, &base, &length, &type) == B_OK) {
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TRACE((" %ld: 0x%Lx, 0x%Lx, %u\n", i, base, length, type));
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} else {
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TRACE((" %ld: empty\n", i));
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}
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}
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}
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module_info *modules[] = {
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(module_info *)&gIntelModule,
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// (module_info *)&gAMDModule,
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(module_info *)&gAMDModule,
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(module_info *)&gVIAModule,
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NULL
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};
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34
src/add-ons/kernel/cpu/x86/generic_x86.h
Normal file
34
src/add-ons/kernel/cpu/x86/generic_x86.h
Normal file
@ -0,0 +1,34 @@
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/*
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* Copyright 2005, Haiku, Inc.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Axel Dörfler, axeld@pinc-software.de
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*/
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#ifndef CPU_GENERIC_x86_H
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#define CPU_GENERIC_x86_H
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#include <SupportDefs.h>
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extern uint64 gPhysicalMask;
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern uint32 generic_count_mtrrs(void);
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extern void generic_init_mtrrs(uint32 count);
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extern void generic_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type);
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extern status_t generic_get_mtrr(uint32 index, uint64 *_base, uint64 *_length,
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uint8 *_type);
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extern status_t generic_mtrr_compute_physical_mask(void);
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extern void generic_dump_mtrrs(uint32 count);
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#ifdef __cplusplus
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}
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#endif
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#endif // CPU_GENERIC_x86_H
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@ -8,121 +8,15 @@
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#include "intel.h"
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#include "generic_x86.h"
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#include <KernelExport.h>
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#include <OS.h>
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#include <arch_cpu.h>
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//#define TRACE_MTRR
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#ifdef TRACE_MTRR
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# define TRACE(x) dprintf x
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#else
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# define TRACE(x) ;
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#endif
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#define IA32_MTRR_ENABLE (1UL << 11)
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#define IA32_MTRR_ENABLE_FIXED (1UL << 10)
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#define IA32_MTRR_VALID_RANGE (1UL << 11)
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struct mtrr_capabilities {
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mtrr_capabilities(uint64 value) { *(uint64 *)this = value; }
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uint64 variable_ranges : 8;
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uint64 supports_fixed : 1;
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uint64 _reserved0 : 1;
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uint64 supports_write_combined : 1;
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uint64 _reserved1 : 53;
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};
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static uint64 sPhysicalMask = 0;
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static uint32
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intel_count_mtrrs(void)
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{
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cpuid_info cpuInfo;
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if (get_cpuid(&cpuInfo, 1, 0) != B_OK
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|| (cpuInfo.eax_1.features & IA32_FEATURE_MTRR) == 0)
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return 0;
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mtrr_capabilities capabilities(x86_read_msr(IA32_MSR_MTRR_CAPABILITIES));
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TRACE(("cpu has %ld variable range MTRs.\n", capabilities.variable_ranges));
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return capabilities.variable_ranges;
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}
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static void
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intel_init_mtrrs(void)
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{
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// disable and clear all MTRRs
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// (we leave the fixed MTRRs as is)
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// TODO: check if the fixed MTRRs are set on all CPUs identically?
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x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE,
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x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE) & ~IA32_MTRR_ENABLE);
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for (uint32 i = intel_count_mtrrs(); i-- > 0;) {
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if (x86_read_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + i * 2) & IA32_MTRR_VALID_RANGE)
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + i * 2, 0);
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}
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// but turn on variable MTRR functionality
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x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE,
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x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE) | IA32_MTRR_ENABLE);
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}
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static void
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intel_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type)
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{
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index *= 2;
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// there are two registers per slot
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uint64 mask = length - 1;
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mask = ~mask & sPhysicalMask;
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TRACE(("MTRR %ld: new mask %Lx)\n", index, mask));
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TRACE((" mask test base: %Lx)\n", mask & base));
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TRACE((" mask test middle: %Lx)\n", mask & (base + length / 2)));
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TRACE((" mask test end: %Lx)\n", mask & (base + length)));
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// First, disable MTRR
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index, 0);
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if (base != 0 || mask != 0 || type != 0) {
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// then fill in the new values, and enable it again
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index,
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(base & ~(B_PAGE_SIZE - 1)) | type);
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index,
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mask | IA32_MTRR_VALID_RANGE);
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} else {
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// reset base as well
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x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index, 0);
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}
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}
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static status_t
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intel_get_mtrr(uint32 index, uint64 *_base, uint64 *_length, uint8 *_type)
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{
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uint64 mask = x86_read_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index * 2);
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if ((mask & IA32_MTRR_VALID_RANGE) == 0)
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return B_ERROR;
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uint64 base = x86_read_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index * 2);
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*_base = base & ~(B_PAGE_SIZE - 1);
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*_length = (~mask & sPhysicalMask) + 1;
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*_type = base & 0xff;
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return B_OK;
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generic_init_mtrrs(generic_count_mtrrs());
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}
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@ -133,52 +27,12 @@ intel_init(void)
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if (get_system_info(&info) != B_OK)
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return B_ERROR;
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if ((info.cpu_type & B_CPU_x86_VENDOR_MASK) != B_CPU_INTEL_x86
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&& (info.cpu_type & B_CPU_x86_VENDOR_MASK) != B_CPU_AMD_x86)
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if ((info.cpu_type & B_CPU_x86_VENDOR_MASK) != B_CPU_INTEL_x86)
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return B_ERROR;
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if (x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE) & IA32_MTRR_ENABLE) {
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TRACE(("MTRR enabled\n"));
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} else {
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TRACE(("MTRR disabled\n"));
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}
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generic_mtrr_compute_physical_mask();
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generic_dump_mtrrs(generic_count_mtrrs());
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for (uint32 i = 0; i < intel_count_mtrrs(); i++) {
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uint64 base;
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uint64 length;
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uint8 type;
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if (intel_get_mtrr(i, &base, &length, &type) == B_OK) {
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TRACE((" %ld: 0x%Lx, 0x%Lx, %u\n", i, base, length, type));
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} else {
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TRACE((" %ld: empty\n", i));
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}
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}
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// TODO: dump fixed ranges as well
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// get number of physical address bits
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uint32 bits = 36;
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cpuid_info cpuInfo;
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if (get_cpuid(&cpuInfo, 0x80000000, 0) == B_OK
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&& cpuInfo.eax_0.max_eax & 0xff >= 8) {
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get_cpuid(&cpuInfo, 0x80000008, 0);
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bits = cpuInfo.regs.eax & 0xff;
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}
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sPhysicalMask = ((1ULL << bits) - 1) & ~(B_PAGE_SIZE - 1);
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TRACE(("CPU has %ld physical address bits, physical mask is %016Lx\n",
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bits, sPhysicalMask));
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return B_OK;
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}
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static status_t
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intel_uninit(void)
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{
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return B_OK;
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}
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@ -190,7 +44,7 @@ intel_stdops(int32 op, ...)
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case B_MODULE_INIT:
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return intel_init();
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case B_MODULE_UNINIT:
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return intel_uninit();
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return B_OK;
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}
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return B_ERROR;
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@ -204,9 +58,9 @@ x86_cpu_module_info gIntelModule = {
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intel_stdops,
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},
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||||
|
||||
intel_count_mtrrs,
|
||||
generic_count_mtrrs,
|
||||
intel_init_mtrrs,
|
||||
|
||||
intel_set_mtrr,
|
||||
intel_get_mtrr,
|
||||
generic_set_mtrr,
|
||||
generic_get_mtrr,
|
||||
};
|
||||
|
||||
@ -8,26 +8,9 @@
|
||||
|
||||
|
||||
#include "via.h"
|
||||
#include "generic_x86.h"
|
||||
|
||||
#include <KernelExport.h>
|
||||
#include <OS.h>
|
||||
#include <arch_cpu.h>
|
||||
|
||||
|
||||
#define TRACE_MTRR
|
||||
#ifdef TRACE_MTRR
|
||||
# define TRACE(x) dprintf x
|
||||
#else
|
||||
# define TRACE(x) ;
|
||||
#endif
|
||||
|
||||
|
||||
#define IA32_MTRR_ENABLE (1UL << 11)
|
||||
#define IA32_MTRR_ENABLE_FIXED (1UL << 10)
|
||||
#define IA32_MTRR_VALID_RANGE (1UL << 11)
|
||||
|
||||
|
||||
static uint64 kPhysicalMask = ((1ULL << 36) - 1) & ~(B_PAGE_SIZE - 1);;
|
||||
|
||||
|
||||
static uint32
|
||||
@ -46,71 +29,7 @@ via_count_mtrrs(void)
|
||||
static void
|
||||
via_init_mtrrs(void)
|
||||
{
|
||||
// disable and clear all MTRRs
|
||||
// (we leave the fixed MTRRs as is)
|
||||
// TODO: check if the fixed MTRRs are set on all CPUs identically?
|
||||
|
||||
x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE,
|
||||
x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE) & ~IA32_MTRR_ENABLE);
|
||||
|
||||
for (uint32 i = via_count_mtrrs(); i-- > 0;) {
|
||||
if (x86_read_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + i * 2) & IA32_MTRR_VALID_RANGE)
|
||||
x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + i * 2, 0);
|
||||
}
|
||||
|
||||
// but turn on variable MTRR functionality
|
||||
|
||||
x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE,
|
||||
x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE) | IA32_MTRR_ENABLE);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
via_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type)
|
||||
{
|
||||
index *= 2;
|
||||
// there are two registers per slot
|
||||
|
||||
uint64 mask = length - 1;
|
||||
mask = ~mask & kPhysicalMask;
|
||||
|
||||
TRACE(("MTRR %ld: new mask %Lx)\n", index, mask));
|
||||
TRACE((" mask test base: %Lx)\n", mask & base));
|
||||
TRACE((" mask test middle: %Lx)\n", mask & (base + length / 2)));
|
||||
TRACE((" mask test end: %Lx)\n", mask & (base + length)));
|
||||
|
||||
// First, disable MTRR
|
||||
|
||||
x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index, 0);
|
||||
|
||||
if (base != 0 || mask != 0 || type != 0) {
|
||||
// then fill in the new values, and enable it again
|
||||
|
||||
x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index,
|
||||
(base & ~(B_PAGE_SIZE - 1)) | type);
|
||||
x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index,
|
||||
mask | IA32_MTRR_VALID_RANGE);
|
||||
} else {
|
||||
// reset base as well
|
||||
x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static status_t
|
||||
via_get_mtrr(uint32 index, uint64 *_base, uint64 *_length, uint8 *_type)
|
||||
{
|
||||
uint64 mask = x86_read_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index * 2);
|
||||
if ((mask & IA32_MTRR_VALID_RANGE) == 0)
|
||||
return B_ERROR;
|
||||
|
||||
uint64 base = x86_read_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index * 2);
|
||||
|
||||
*_base = base & ~(B_PAGE_SIZE - 1);
|
||||
*_length = (~mask & kPhysicalMask) + 1;
|
||||
*_type = base & 0xff;
|
||||
|
||||
return B_OK;
|
||||
generic_init_mtrrs(via_count_mtrrs());
|
||||
}
|
||||
|
||||
|
||||
@ -124,32 +43,10 @@ via_init(void)
|
||||
if ((info.cpu_type & B_CPU_x86_VENDOR_MASK) != B_CPU_VIA_IDT_x86)
|
||||
return B_ERROR;
|
||||
|
||||
if (x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE) & IA32_MTRR_ENABLE) {
|
||||
TRACE(("MTRR enabled\n"));
|
||||
} else {
|
||||
TRACE(("MTRR disabled\n"));
|
||||
}
|
||||
// current VIA CPUs have always 36 bit (or less?)
|
||||
gPhysicalMask = ((1ULL << 36) - 1) & ~(B_PAGE_SIZE - 1);
|
||||
|
||||
for (uint32 i = 0; i < via_count_mtrrs(); i++) {
|
||||
uint64 base;
|
||||
uint64 length;
|
||||
uint8 type;
|
||||
if (via_get_mtrr(i, &base, &length, &type) == B_OK) {
|
||||
TRACE((" %ld: 0x%Lx, 0x%Lx, %u\n", i, base, length, type));
|
||||
} else {
|
||||
TRACE((" %ld: empty\n", i));
|
||||
}
|
||||
}
|
||||
|
||||
// TODO: dump fixed ranges as well
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
static status_t
|
||||
via_uninit(void)
|
||||
{
|
||||
generic_dump_mtrrs(generic_count_mtrrs());
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
@ -161,7 +58,7 @@ via_stdops(int32 op, ...)
|
||||
case B_MODULE_INIT:
|
||||
return via_init();
|
||||
case B_MODULE_UNINIT:
|
||||
return via_uninit();
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
return B_ERROR;
|
||||
@ -178,6 +75,6 @@ x86_cpu_module_info gVIAModule = {
|
||||
via_count_mtrrs,
|
||||
via_init_mtrrs,
|
||||
|
||||
via_set_mtrr,
|
||||
via_get_mtrr,
|
||||
generic_set_mtrr,
|
||||
generic_get_mtrr,
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user