From 1f1a4dff417ca9d62addb01d8dc08730c4f2426b Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Tue, 31 Aug 2004 12:34:16 +0000 Subject: [PATCH] fixed small typo. Erazor 3 (TNT2) indeed still operational exactly as before. git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8747 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/nvidia/engine/nv_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_info.c b/src/add-ons/accelerants/nvidia/engine/nv_info.c index 8c7de0c25a..f976b0b524 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_info.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_info.c @@ -519,7 +519,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size) adress += 1; or_in = *((uint8*)(&(rom[adress]))); adress += 1; - LOG(8,("cmd 'RD 8bit indexed ISA I/O REG $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", + LOG(8,("cmd 'RD 8bit idx ISA I/O REG $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", index, reg, and_out, or_in)); //fixme? this is for ISA I/O registers. Looks like they are in mapped range // as well (confirm or update code!)