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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22344 a95241bf-73f2-0310-859d-f6bbb57e9c96
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Marcus Overhagen
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363
headers/private/drivers/ide_types.h
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363
headers/private/drivers/ide_types.h
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/*
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** Copyright 2002/03, Thomas Kurschel. All rights reserved.
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** Distributed under the terms of the OpenBeOS License.
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*/
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/*
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Part of Open IDE bus manager
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IDE bus manager interface
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*/
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#ifndef __IDE_H__
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#define __IDE_H__
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#include <bus_manager.h>
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#include <iovec.h>
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#include <lendian_bitfield.h>
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#include <device_manager.h>
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#include <KernelExport.h>
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// IDE task file.
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// contains the command block interpreted under different conditions with
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// first byte being first command register, second byte second command register
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// etc.; for lba48, registers must be written twice, therefore there
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// are twice as many bytes as registers - the first eight bytes are those
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// that must be written first, the second eight bytes are those that
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// must be written second.
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typedef union {
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struct {
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uint8 features;
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uint8 sector_count;
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uint8 sector_number;
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uint8 cylinder_0_7;
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uint8 cylinder_8_15;
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LBITFIELD8_3(
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head : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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} chs;
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struct {
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uint8 features;
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uint8 sector_count;
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uint8 lba_0_7;
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uint8 lba_8_15;
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uint8 lba_16_23;
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LBITFIELD8_3(
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lba_24_27 : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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} lba;
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struct {
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LBITFIELD8_3(
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dma : 1,
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ovl : 1,
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_0_res2 : 6
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);
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LBITFIELD8_2(
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_1_res0 : 3,
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tag : 5
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);
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uint8 _2_res;
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uint8 byte_count_0_7;
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uint8 byte_count_8_15;
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LBITFIELD8_6(
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lun : 3,
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_5_res3 : 1,
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device : 1,
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_5_one5 : 1,
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_5_res6 : 1,
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_5_one7 : 1
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);
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uint8 command;
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} packet;
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struct {
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LBITFIELD8_5(
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ili : 1,
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eom : 1,
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abrt : 1,
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_0_res3 : 1,
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sense_key : 4
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);
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LBITFIELD8_4(
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cmd_or_data : 1, // 1 - cmd, 0 - data
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input_or_output : 1, // 0 - input (to device), 1 - output
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release : 1,
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tag : 5
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);
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uint8 _2_res;
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uint8 byte_count_0_7;
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uint8 byte_count_8_15;
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LBITFIELD8_5(
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_4_res0 : 4,
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device : 1,
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_4_obs5 : 1,
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_4_res6 : 1,
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_4_obs7 : 1
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);
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LBITFIELD8_7(
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chk : 1,
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_7_res1 : 2,
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drq : 1,
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serv : 1,
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dmrd : 1,
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drdy : 1,
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bsy : 1
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);
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} packet_res;
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struct {
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uint8 sector_count;
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LBITFIELD8_4( // only <tag> is defined for write
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cmd_or_data : 1, // 1 - cmd, 0 - data
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input_or_output : 1, // 0 - input (to device), 1 - output
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release : 1,
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tag : 5
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);
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uint8 lba_0_7;
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uint8 lba_8_15;
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uint8 lba_16_23;
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LBITFIELD8_3(
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lba_24_27 : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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} queued;
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struct {
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// low order bytes
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uint8 features;
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uint8 sector_count_0_7;
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uint8 lba_0_7;
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uint8 lba_8_15;
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uint8 lba_16_23;
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LBITFIELD8_3(
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_5low_res0 : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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// high order bytes
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uint8 _0high_res;
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uint8 sector_count_8_15;
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uint8 lba_24_31;
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uint8 lba_32_39;
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uint8 lba_40_47;
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} lba48;
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struct {
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// low order bytes
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uint8 sector_count_0_7;
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LBITFIELD8_4(
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cmd_or_data : 1, // 1 - cmd, 0 - data
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input_or_output : 1, // 0 - input (to device), 1 - output
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release : 1,
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tag : 5
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);
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uint8 lba_0_7;
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uint8 lba_8_15;
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uint8 lba_16_23;
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LBITFIELD8_3(
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_5low_res0 : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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// high order bytes
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uint8 sector_count_8_15;
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uint8 _1high_res;
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uint8 lba_24_31;
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uint8 lba_32_39;
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uint8 lba_40_47;
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} queued48;
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struct {
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uint8 _0_res[3];
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uint8 ver; // RMSN version
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LBITFIELD8_3(
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pena : 1, // previously enabled
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lock : 1, // capable of locking
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pej : 1 // can physically eject
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);
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} set_MSN_res;
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struct {
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uint8 r[7+5];
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} raw;
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struct {
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uint8 features;
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uint8 sector_count;
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uint8 sector_number;
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uint8 cylinder_low;
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uint8 cylinder_high;
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uint8 device_head;
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uint8 command;
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} write;
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struct {
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uint8 error;
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uint8 sector_count;
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uint8 sector_number;
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uint8 cylinder_low;
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uint8 cylinder_high;
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uint8 device_head;
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uint8 status;
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} read;
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} ide_task_file;
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// content of "mode" field
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enum {
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ide_mode_chs = 5,
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ide_mode_lba = 7
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};
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// mask for ide_task_file fields to be written
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typedef enum {
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ide_mask_features = 0x01,
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ide_mask_sector_count = 0x02,
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// CHS
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ide_mask_sector_number = 0x04,
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ide_mask_cylinder_low = 0x08,
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ide_mask_cylinder_high = 0x10,
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// LBA
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ide_mask_LBA_low = 0x04,
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ide_mask_LBA_mid = 0x08,
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ide_mask_LBA_high = 0x10,
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// packet
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ide_mask_byte_count = 0x18,
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// packet and dma queued result
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ide_mask_error = 0x01,
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ide_mask_ireason = 0x02,
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ide_mask_device_head = 0x20,
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ide_mask_command = 0x40,
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ide_mask_status = 0x40,
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// for 48 bits, the following flags tell which registers to load twice
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ide_mask_features_48 = 0x80 | ide_mask_features,
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ide_mask_sector_count_48 = 0x80 | ide_mask_sector_count,
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ide_mask_LBA_low_48 = 0x100 | ide_mask_LBA_low,
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ide_mask_LBA_mid_48 = 0x200 | ide_mask_LBA_mid,
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ide_mask_LBA_high_48 = 0x400 | ide_mask_LBA_high,
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ide_mask_HOB = 0x780
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//ide_mask_all = 0x7f
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} ide_reg_mask;
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// status register
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enum {
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ide_status_err = 0x01, // error
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ide_status_index = 0x02, // obsolete
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ide_status_corr = 0x04, // obsolete
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ide_status_drq = 0x08, // data request
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ide_status_dsc = 0x10, // reserved
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ide_status_service = 0x10, // ready to service device
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ide_status_dwf = 0x20, // reserved
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ide_status_dma = 0x20, // reserved
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ide_status_dmrd = 0x20, // packet: DMA ready
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ide_status_df = 0x20, // packet: disk failure
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ide_status_drdy = 0x40, // device ready
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ide_status_bsy = 0x80 // busy
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} ide_status_mask;
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// device control register
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enum {
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// bit 0 must be zero
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ide_devctrl_nien = 0x02, // disable INTRQ
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ide_devctrl_srst = 0x04, // software device reset
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ide_devctrl_bit3 = 0x08, // don't know, but must be set
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// bits inbetween are reserved
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ide_devctrl_hob = 0x80 // read high order byte (for 48-bit lba)
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} ide_devcntrl_mask;
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// error register - most bits are command specific
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enum {
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// always used
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ide_error_abrt = 0x04, // command aborted
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// used for Ultra DMA modes
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ide_error_icrc = 0x80, // interface CRC error
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// used by reading data transfers
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ide_error_unc = 0x40, // uncorrectable data error
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// used by writing data transfers
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ide_error_wp = 0x40, // media write protect
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// used by all data transfer commands
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ide_error_mc = 0x20, // medium changed
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ide_error_idnf = 0x10, // CHS translation not init./ invalid CHS address
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ide_error_mcr = 0x08, // media change requested
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ide_error_nm = 0x02, // no media (for removable media devices)
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} ide_error_mask;
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typedef struct ide_channel_info *ide_channel_cookie;
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// Controller Driver Node
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// attributes:
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// node type
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#define IDE_BUS_TYPE_NAME "bus/ide/v1"
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// maximum number of devices connected to controller (uint8, optional, default:2)
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#define IDE_CONTROLLER_MAX_DEVICES_ITEM "ide/max_devices"
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// set to not-0 if DMA is supported (uint8, optional, default:0)
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// (if so, publish necessary blkdev restriction too)
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#define IDE_CONTROLLER_CAN_DMA_ITEM "ide/can_DMA"
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// set to not-0 if CQ is supported (uint8, optional, default:1)
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#define IDE_CONTROLLER_CAN_CQ_ITEM "ide/can_CQ"
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// name of controller (string, required)
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#define IDE_CONTROLLER_CONTROLLER_NAME_ITEM "ide/controller_name"
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// interface of controller driver
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typedef struct {
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driver_module_info info;
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status_t (*write_command_block_regs)
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(void *channel_cookie, ide_task_file *tf, ide_reg_mask mask);
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status_t (*read_command_block_regs)
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(void *channel_cookie, ide_task_file *tf, ide_reg_mask mask);
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uint8 (*get_altstatus) (void *channel_cookie);
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status_t (*write_device_control) (void *channel_cookie, uint8 val);
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status_t (*write_pio) (void *channel_cookie, uint16 *data, int count, bool force_16bit );
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status_t (*read_pio) (void *channel_cookie, uint16 *data, int count, bool force_16bit );
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status_t (*prepare_dma)(void *channel_cookie,
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const physical_entry *sg_list, size_t sg_list_count,
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bool write);
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status_t (*start_dma)(void *channel_cookie);
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status_t (*finish_dma)(void *channel_cookie);
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} ide_controller_interface;
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// channel cookie, issued by ide bus manager
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typedef struct ide_bus_info *ide_channel;
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// Interface for Controller Driver
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// interface of bus manager as seen from controller driver
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// use this interface as the fixed consumer of your controller driver
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typedef struct {
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driver_module_info info;
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// status - status read from controller (_not_ alt_status, as reading
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// normal status acknowledges IRQ request of device)
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status_t (*irq_handler)( ide_channel channel, uint8 status );
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} ide_for_controller_interface;
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#define IDE_FOR_CONTROLLER_MODULE_NAME "bus_managers/ide/controller/v1"
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#endif /* __IDE_H__ */
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