diff --git a/headers/private/graphics/radeon_hd/car_reg.h b/headers/private/graphics/radeon_hd/car_reg.h new file mode 100644 index 0000000000..f745a38d7d --- /dev/null +++ b/headers/private/graphics/radeon_hd/car_reg.h @@ -0,0 +1,7648 @@ +/* + * DCE_11_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_11_0_D_H +#define DCE_11_0_D_H + +#define CAR_mmPIPE0_PG_CONFIG 0x2c0 +#define CAR_mmPIPE0_PG_ENABLE 0x2c1 +#define CAR_mmPIPE0_PG_STATUS 0x2c2 +#define CAR_mmPIPE1_PG_CONFIG 0x2c3 +#define CAR_mmPIPE1_PG_ENABLE 0x2c4 +#define CAR_mmPIPE1_PG_STATUS 0x2c5 +#define CAR_mmPIPE2_PG_CONFIG 0x2c6 +#define CAR_mmPIPE2_PG_ENABLE 0x2c7 +#define CAR_mmPIPE2_PG_STATUS 0x2c8 +#define CAR_mmDCFEV0_PG_CONFIG 0x2db +#define CAR_mmDCFEV0_PG_ENABLE 0x2dc +#define CAR_mmDCFEV0_PG_STATUS 0x2dd +#define CAR_mmDCPG_INTERRUPT_STATUS 0x2de +#define CAR_mmDCPG_INTERRUPT_CONTROL 0x2df +#define CAR_mmDC_IP_REQUEST_CNTL 0x2d2 +#define CAR_mmDC_PGFSM_CONFIG_REG 0x2d3 +#define CAR_mmDC_PGFSM_WRITE_REG 0x2d4 +#define CAR_mmDC_PGCNTL_STATUS_REG 0x2d5 +#define CAR_mmDCPG_TEST_DEBUG_INDEX 0x2d6 +#define CAR_mmDCPG_TEST_DEBUG_DATA 0x2d7 +#define CAR_mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define CAR_mmBL1_PWM_USER_LEVEL 0x1629 +#define CAR_mmBL1_PWM_TARGET_ABM_LEVEL 0x162a +#define CAR_mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b +#define CAR_mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c +#define CAR_mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d +#define CAR_mmBL1_PWM_ABM_CNTL 0x162e +#define CAR_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f +#define CAR_mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define CAR_mmDC_ABM1_CNTL 0x1638 +#define CAR_mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a +#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b +#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c +#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d +#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e +#define CAR_mmDC_ABM1_ACE_THRES_12 0x163f +#define CAR_mmDC_ABM1_ACE_THRES_34 0x1640 +#define CAR_mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define CAR_mmDC_ABM1_DEBUG_MISC 0x1649 +#define CAR_mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a +#define CAR_mmDC_ABM1_HG_MISC_CTRL 0x164b +#define CAR_mmDC_ABM1_LS_SUM_OF_LUMA 0x164c +#define CAR_mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d +#define CAR_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e +#define CAR_mmDC_ABM1_LS_PIXEL_COUNT 0x164f +#define CAR_mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define CAR_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define CAR_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define CAR_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define CAR_mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define CAR_mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define CAR_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define CAR_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define CAR_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define CAR_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define CAR_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a +#define CAR_mmDC_ABM1_HG_RESULT_1 0x165b +#define CAR_mmDC_ABM1_HG_RESULT_2 0x165c +#define CAR_mmDC_ABM1_HG_RESULT_3 0x165d +#define CAR_mmDC_ABM1_HG_RESULT_4 0x165e +#define CAR_mmDC_ABM1_HG_RESULT_5 0x165f +#define CAR_mmDC_ABM1_HG_RESULT_6 0x1660 +#define CAR_mmDC_ABM1_HG_RESULT_7 0x1661 +#define CAR_mmDC_ABM1_HG_RESULT_8 0x1662 +#define CAR_mmDC_ABM1_HG_RESULT_9 0x1663 +#define CAR_mmDC_ABM1_HG_RESULT_10 0x1664 +#define CAR_mmDC_ABM1_HG_RESULT_11 0x1665 +#define CAR_mmDC_ABM1_HG_RESULT_12 0x1666 +#define CAR_mmDC_ABM1_HG_RESULT_13 0x1667 +#define CAR_mmDC_ABM1_HG_RESULT_14 0x1668 +#define CAR_mmDC_ABM1_HG_RESULT_15 0x1669 +#define CAR_mmDC_ABM1_HG_RESULT_16 0x166a +#define CAR_mmDC_ABM1_HG_RESULT_17 0x166b +#define CAR_mmDC_ABM1_HG_RESULT_18 0x166c +#define CAR_mmDC_ABM1_HG_RESULT_19 0x166d +#define CAR_mmDC_ABM1_HG_RESULT_20 0x166e +#define CAR_mmDC_ABM1_HG_RESULT_21 0x166f +#define CAR_mmDC_ABM1_HG_RESULT_22 0x1670 +#define CAR_mmDC_ABM1_HG_RESULT_23 0x1671 +#define CAR_mmDC_ABM1_HG_RESULT_24 0x1672 +#define CAR_mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b +#define CAR_mmDC_ABM1_BL_MASTER_LOCK 0x169c +#define CAR_mmABM_TEST_DEBUG_INDEX 0x169e +#define CAR_mmABM_TEST_DEBUG_DATA 0x169f +#define CAR_mmCRTC_H_BLANK_EARLY_NUM 0x1b7d +#define CAR_mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d +#define CAR_mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d +#define CAR_mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d +#define CAR_mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d +#define CAR_mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d +#define CAR_mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d +#define CAR_mmCRTC_H_TOTAL 0x1b80 +#define CAR_mmCRTC0_CRTC_H_TOTAL 0x1b80 +#define CAR_mmCRTC1_CRTC_H_TOTAL 0x1d80 +#define CAR_mmCRTC2_CRTC_H_TOTAL 0x1f80 +#define CAR_mmCRTC3_CRTC_H_TOTAL 0x4180 +#define CAR_mmCRTC4_CRTC_H_TOTAL 0x4380 +#define CAR_mmCRTC5_CRTC_H_TOTAL 0x4580 +#define CAR_mmCRTC_H_BLANK_START_END 0x1b81 +#define CAR_mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 +#define CAR_mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 +#define CAR_mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 +#define CAR_mmCRTC3_CRTC_H_BLANK_START_END 0x4181 +#define CAR_mmCRTC4_CRTC_H_BLANK_START_END 0x4381 +#define CAR_mmCRTC5_CRTC_H_BLANK_START_END 0x4581 +#define CAR_mmCRTC_H_SYNC_A 0x1b82 +#define CAR_mmCRTC0_CRTC_H_SYNC_A 0x1b82 +#define CAR_mmCRTC1_CRTC_H_SYNC_A 0x1d82 +#define CAR_mmCRTC2_CRTC_H_SYNC_A 0x1f82 +#define CAR_mmCRTC3_CRTC_H_SYNC_A 0x4182 +#define CAR_mmCRTC4_CRTC_H_SYNC_A 0x4382 +#define CAR_mmCRTC5_CRTC_H_SYNC_A 0x4582 +#define CAR_mmCRTC_H_SYNC_A_CNTL 0x1b83 +#define CAR_mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 +#define CAR_mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 +#define CAR_mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 +#define CAR_mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 +#define CAR_mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 +#define CAR_mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 +#define CAR_mmCRTC_H_SYNC_B 0x1b84 +#define CAR_mmCRTC0_CRTC_H_SYNC_B 0x1b84 +#define CAR_mmCRTC1_CRTC_H_SYNC_B 0x1d84 +#define CAR_mmCRTC2_CRTC_H_SYNC_B 0x1f84 +#define CAR_mmCRTC3_CRTC_H_SYNC_B 0x4184 +#define CAR_mmCRTC4_CRTC_H_SYNC_B 0x4384 +#define CAR_mmCRTC5_CRTC_H_SYNC_B 0x4584 +#define CAR_mmCRTC_H_SYNC_B_CNTL 0x1b85 +#define CAR_mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 +#define CAR_mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 +#define CAR_mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 +#define CAR_mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 +#define CAR_mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 +#define CAR_mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 +#define CAR_mmCRTC_VBI_END 0x1b86 +#define CAR_mmCRTC0_CRTC_VBI_END 0x1b86 +#define CAR_mmCRTC1_CRTC_VBI_END 0x1d86 +#define CAR_mmCRTC2_CRTC_VBI_END 0x1f86 +#define CAR_mmCRTC3_CRTC_VBI_END 0x4186 +#define CAR_mmCRTC4_CRTC_VBI_END 0x4386 +#define CAR_mmCRTC5_CRTC_VBI_END 0x4586 +#define CAR_mmCRTC_V_TOTAL 0x1b87 +#define CAR_mmCRTC0_CRTC_V_TOTAL 0x1b87 +#define CAR_mmCRTC1_CRTC_V_TOTAL 0x1d87 +#define CAR_mmCRTC2_CRTC_V_TOTAL 0x1f87 +#define CAR_mmCRTC3_CRTC_V_TOTAL 0x4187 +#define CAR_mmCRTC4_CRTC_V_TOTAL 0x4387 +#define CAR_mmCRTC5_CRTC_V_TOTAL 0x4587 +#define CAR_mmCRTC_V_TOTAL_MIN 0x1b88 +#define CAR_mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 +#define CAR_mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 +#define CAR_mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 +#define CAR_mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 +#define CAR_mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 +#define CAR_mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 +#define CAR_mmCRTC_V_TOTAL_MAX 0x1b89 +#define CAR_mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 +#define CAR_mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 +#define CAR_mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 +#define CAR_mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 +#define CAR_mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 +#define CAR_mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 +#define CAR_mmCRTC_V_TOTAL_CONTROL 0x1b8a +#define CAR_mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a +#define CAR_mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a +#define CAR_mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a +#define CAR_mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a +#define CAR_mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a +#define CAR_mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a +#define CAR_mmCRTC_V_TOTAL_INT_STATUS 0x1b8b +#define CAR_mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b +#define CAR_mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b +#define CAR_mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b +#define CAR_mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b +#define CAR_mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b +#define CAR_mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b +#define CAR_mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define CAR_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define CAR_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c +#define CAR_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c +#define CAR_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c +#define CAR_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c +#define CAR_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c +#define CAR_mmCRTC_V_BLANK_START_END 0x1b8d +#define CAR_mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d +#define CAR_mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d +#define CAR_mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d +#define CAR_mmCRTC3_CRTC_V_BLANK_START_END 0x418d +#define CAR_mmCRTC4_CRTC_V_BLANK_START_END 0x438d +#define CAR_mmCRTC5_CRTC_V_BLANK_START_END 0x458d +#define CAR_mmCRTC_V_SYNC_A 0x1b8e +#define CAR_mmCRTC0_CRTC_V_SYNC_A 0x1b8e +#define CAR_mmCRTC1_CRTC_V_SYNC_A 0x1d8e +#define CAR_mmCRTC2_CRTC_V_SYNC_A 0x1f8e +#define CAR_mmCRTC3_CRTC_V_SYNC_A 0x418e +#define CAR_mmCRTC4_CRTC_V_SYNC_A 0x438e +#define CAR_mmCRTC5_CRTC_V_SYNC_A 0x458e +#define CAR_mmCRTC_V_SYNC_A_CNTL 0x1b8f +#define CAR_mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f +#define CAR_mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f +#define CAR_mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f +#define CAR_mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f +#define CAR_mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f +#define CAR_mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f +#define CAR_mmCRTC_V_SYNC_B 0x1b90 +#define CAR_mmCRTC0_CRTC_V_SYNC_B 0x1b90 +#define CAR_mmCRTC1_CRTC_V_SYNC_B 0x1d90 +#define CAR_mmCRTC2_CRTC_V_SYNC_B 0x1f90 +#define CAR_mmCRTC3_CRTC_V_SYNC_B 0x4190 +#define CAR_mmCRTC4_CRTC_V_SYNC_B 0x4390 +#define CAR_mmCRTC5_CRTC_V_SYNC_B 0x4590 +#define CAR_mmCRTC_V_SYNC_B_CNTL 0x1b91 +#define CAR_mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 +#define CAR_mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 +#define CAR_mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 +#define CAR_mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 +#define CAR_mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 +#define CAR_mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 +#define CAR_mmCRTC_DTMTEST_CNTL 0x1b92 +#define CAR_mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 +#define CAR_mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 +#define CAR_mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 +#define CAR_mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 +#define CAR_mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 +#define CAR_mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 +#define CAR_mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define CAR_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define CAR_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 +#define CAR_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 +#define CAR_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define CAR_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 +#define CAR_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 +#define CAR_mmCRTC_TRIGA_CNTL 0x1b94 +#define CAR_mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 +#define CAR_mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 +#define CAR_mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 +#define CAR_mmCRTC3_CRTC_TRIGA_CNTL 0x4194 +#define CAR_mmCRTC4_CRTC_TRIGA_CNTL 0x4394 +#define CAR_mmCRTC5_CRTC_TRIGA_CNTL 0x4594 +#define CAR_mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define CAR_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define CAR_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 +#define CAR_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 +#define CAR_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define CAR_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 +#define CAR_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 +#define CAR_mmCRTC_TRIGB_CNTL 0x1b96 +#define CAR_mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 +#define CAR_mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 +#define CAR_mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 +#define CAR_mmCRTC3_CRTC_TRIGB_CNTL 0x4196 +#define CAR_mmCRTC4_CRTC_TRIGB_CNTL 0x4396 +#define CAR_mmCRTC5_CRTC_TRIGB_CNTL 0x4596 +#define CAR_mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define CAR_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define CAR_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 +#define CAR_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 +#define CAR_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define CAR_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 +#define CAR_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 +#define CAR_mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define CAR_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define CAR_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 +#define CAR_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 +#define CAR_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define CAR_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 +#define CAR_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 +#define CAR_mmCRTC_FLOW_CONTROL 0x1b99 +#define CAR_mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 +#define CAR_mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 +#define CAR_mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 +#define CAR_mmCRTC3_CRTC_FLOW_CONTROL 0x4199 +#define CAR_mmCRTC4_CRTC_FLOW_CONTROL 0x4399 +#define CAR_mmCRTC5_CRTC_FLOW_CONTROL 0x4599 +#define CAR_mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define CAR_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define CAR_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a +#define CAR_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a +#define CAR_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a +#define CAR_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a +#define CAR_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a +#define CAR_mmCRTC_AVSYNC_COUNTER 0x1b9b +#define CAR_mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b +#define CAR_mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b +#define CAR_mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b +#define CAR_mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b +#define CAR_mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b +#define CAR_mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b +#define CAR_mmCRTC_CONTROL 0x1b9c +#define CAR_mmCRTC0_CRTC_CONTROL 0x1b9c +#define CAR_mmCRTC1_CRTC_CONTROL 0x1d9c +#define CAR_mmCRTC2_CRTC_CONTROL 0x1f9c +#define CAR_mmCRTC3_CRTC_CONTROL 0x419c +#define CAR_mmCRTC4_CRTC_CONTROL 0x439c +#define CAR_mmCRTC5_CRTC_CONTROL 0x459c +#define CAR_mmCRTC_BLANK_CONTROL 0x1b9d +#define CAR_mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d +#define CAR_mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d +#define CAR_mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d +#define CAR_mmCRTC3_CRTC_BLANK_CONTROL 0x419d +#define CAR_mmCRTC4_CRTC_BLANK_CONTROL 0x439d +#define CAR_mmCRTC5_CRTC_BLANK_CONTROL 0x459d +#define CAR_mmCRTC_INTERLACE_CONTROL 0x1b9e +#define CAR_mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e +#define CAR_mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e +#define CAR_mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e +#define CAR_mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e +#define CAR_mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e +#define CAR_mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e +#define CAR_mmCRTC_INTERLACE_STATUS 0x1b9f +#define CAR_mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f +#define CAR_mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f +#define CAR_mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f +#define CAR_mmCRTC3_CRTC_INTERLACE_STATUS 0x419f +#define CAR_mmCRTC4_CRTC_INTERLACE_STATUS 0x439f +#define CAR_mmCRTC5_CRTC_INTERLACE_STATUS 0x459f +#define CAR_mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define CAR_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define CAR_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 +#define CAR_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 +#define CAR_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 +#define CAR_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 +#define CAR_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 +#define CAR_mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define CAR_mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define CAR_mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 +#define CAR_mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 +#define CAR_mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 +#define CAR_mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 +#define CAR_mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 +#define CAR_mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define CAR_mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define CAR_mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 +#define CAR_mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 +#define CAR_mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 +#define CAR_mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 +#define CAR_mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 +#define CAR_mmCRTC_STATUS 0x1ba3 +#define CAR_mmCRTC0_CRTC_STATUS 0x1ba3 +#define CAR_mmCRTC1_CRTC_STATUS 0x1da3 +#define CAR_mmCRTC2_CRTC_STATUS 0x1fa3 +#define CAR_mmCRTC3_CRTC_STATUS 0x41a3 +#define CAR_mmCRTC4_CRTC_STATUS 0x43a3 +#define CAR_mmCRTC5_CRTC_STATUS 0x45a3 +#define CAR_mmCRTC_STATUS_POSITION 0x1ba4 +#define CAR_mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 +#define CAR_mmCRTC1_CRTC_STATUS_POSITION 0x1da4 +#define CAR_mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 +#define CAR_mmCRTC3_CRTC_STATUS_POSITION 0x41a4 +#define CAR_mmCRTC4_CRTC_STATUS_POSITION 0x43a4 +#define CAR_mmCRTC5_CRTC_STATUS_POSITION 0x45a4 +#define CAR_mmCRTC_NOM_VERT_POSITION 0x1ba5 +#define CAR_mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 +#define CAR_mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 +#define CAR_mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 +#define CAR_mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 +#define CAR_mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 +#define CAR_mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 +#define CAR_mmCRTC_STATUS_FRAME_COUNT 0x1ba6 +#define CAR_mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 +#define CAR_mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 +#define CAR_mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 +#define CAR_mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 +#define CAR_mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 +#define CAR_mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 +#define CAR_mmCRTC_STATUS_VF_COUNT 0x1ba7 +#define CAR_mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 +#define CAR_mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 +#define CAR_mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 +#define CAR_mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 +#define CAR_mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 +#define CAR_mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 +#define CAR_mmCRTC_STATUS_HV_COUNT 0x1ba8 +#define CAR_mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 +#define CAR_mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 +#define CAR_mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 +#define CAR_mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 +#define CAR_mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 +#define CAR_mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 +#define CAR_mmCRTC_COUNT_CONTROL 0x1ba9 +#define CAR_mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 +#define CAR_mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 +#define CAR_mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 +#define CAR_mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 +#define CAR_mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 +#define CAR_mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 +#define CAR_mmCRTC_COUNT_RESET 0x1baa +#define CAR_mmCRTC0_CRTC_COUNT_RESET 0x1baa +#define CAR_mmCRTC1_CRTC_COUNT_RESET 0x1daa +#define CAR_mmCRTC2_CRTC_COUNT_RESET 0x1faa +#define CAR_mmCRTC3_CRTC_COUNT_RESET 0x41aa +#define CAR_mmCRTC4_CRTC_COUNT_RESET 0x43aa +#define CAR_mmCRTC5_CRTC_COUNT_RESET 0x45aa +#define CAR_mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define CAR_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define CAR_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab +#define CAR_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab +#define CAR_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab +#define CAR_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab +#define CAR_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab +#define CAR_mmCRTC_VERT_SYNC_CONTROL 0x1bac +#define CAR_mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac +#define CAR_mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac +#define CAR_mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac +#define CAR_mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac +#define CAR_mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac +#define CAR_mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac +#define CAR_mmCRTC_STEREO_STATUS 0x1bad +#define CAR_mmCRTC0_CRTC_STEREO_STATUS 0x1bad +#define CAR_mmCRTC1_CRTC_STEREO_STATUS 0x1dad +#define CAR_mmCRTC2_CRTC_STEREO_STATUS 0x1fad +#define CAR_mmCRTC3_CRTC_STEREO_STATUS 0x41ad +#define CAR_mmCRTC4_CRTC_STEREO_STATUS 0x43ad +#define CAR_mmCRTC5_CRTC_STEREO_STATUS 0x45ad +#define CAR_mmCRTC_STEREO_CONTROL 0x1bae +#define CAR_mmCRTC0_CRTC_STEREO_CONTROL 0x1bae +#define CAR_mmCRTC1_CRTC_STEREO_CONTROL 0x1dae +#define CAR_mmCRTC2_CRTC_STEREO_CONTROL 0x1fae +#define CAR_mmCRTC3_CRTC_STEREO_CONTROL 0x41ae +#define CAR_mmCRTC4_CRTC_STEREO_CONTROL 0x43ae +#define CAR_mmCRTC5_CRTC_STEREO_CONTROL 0x45ae +#define CAR_mmCRTC_SNAPSHOT_STATUS 0x1baf +#define CAR_mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf +#define CAR_mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf +#define CAR_mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf +#define CAR_mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af +#define CAR_mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af +#define CAR_mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af +#define CAR_mmCRTC_SNAPSHOT_CONTROL 0x1bb0 +#define CAR_mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 +#define CAR_mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 +#define CAR_mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 +#define CAR_mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 +#define CAR_mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 +#define CAR_mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 +#define CAR_mmCRTC_SNAPSHOT_POSITION 0x1bb1 +#define CAR_mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 +#define CAR_mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 +#define CAR_mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 +#define CAR_mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 +#define CAR_mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 +#define CAR_mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 +#define CAR_mmCRTC_SNAPSHOT_FRAME 0x1bb2 +#define CAR_mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 +#define CAR_mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 +#define CAR_mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 +#define CAR_mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 +#define CAR_mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 +#define CAR_mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 +#define CAR_mmCRTC_START_LINE_CONTROL 0x1bb3 +#define CAR_mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 +#define CAR_mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 +#define CAR_mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 +#define CAR_mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 +#define CAR_mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 +#define CAR_mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 +#define CAR_mmCRTC_INTERRUPT_CONTROL 0x1bb4 +#define CAR_mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 +#define CAR_mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 +#define CAR_mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 +#define CAR_mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 +#define CAR_mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 +#define CAR_mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 +#define CAR_mmCRTC_UPDATE_LOCK 0x1bb5 +#define CAR_mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 +#define CAR_mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 +#define CAR_mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 +#define CAR_mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 +#define CAR_mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 +#define CAR_mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 +#define CAR_mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define CAR_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define CAR_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 +#define CAR_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 +#define CAR_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 +#define CAR_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 +#define CAR_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 +#define CAR_mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define CAR_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define CAR_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 +#define CAR_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 +#define CAR_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 +#define CAR_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 +#define CAR_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 +#define CAR_mmCRTC_TEST_PATTERN_CONTROL 0x1bba +#define CAR_mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba +#define CAR_mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba +#define CAR_mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba +#define CAR_mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba +#define CAR_mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba +#define CAR_mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba +#define CAR_mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define CAR_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define CAR_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb +#define CAR_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb +#define CAR_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb +#define CAR_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb +#define CAR_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb +#define CAR_mmCRTC_TEST_PATTERN_COLOR 0x1bbc +#define CAR_mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc +#define CAR_mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc +#define CAR_mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc +#define CAR_mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc +#define CAR_mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc +#define CAR_mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc +#define CAR_mmCRTC_MASTER_UPDATE_LOCK 0x1bbd +#define CAR_mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x1bbd +#define CAR_mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x1dbd +#define CAR_mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x1fbd +#define CAR_mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x41bd +#define CAR_mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x43bd +#define CAR_mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x45bd +#define CAR_mmCRTC_MASTER_UPDATE_MODE 0x1bbe +#define CAR_mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x1bbe +#define CAR_mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x1dbe +#define CAR_mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x1fbe +#define CAR_mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x41be +#define CAR_mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x43be +#define CAR_mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x45be +#define CAR_mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define CAR_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define CAR_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf +#define CAR_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf +#define CAR_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf +#define CAR_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf +#define CAR_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf +#define CAR_mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define CAR_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define CAR_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 +#define CAR_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 +#define CAR_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 +#define CAR_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 +#define CAR_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 +#define CAR_mmCRTC_MVP_STATUS 0x1bc1 +#define CAR_mmCRTC0_CRTC_MVP_STATUS 0x1bc1 +#define CAR_mmCRTC1_CRTC_MVP_STATUS 0x1dc1 +#define CAR_mmCRTC2_CRTC_MVP_STATUS 0x1fc1 +#define CAR_mmCRTC3_CRTC_MVP_STATUS 0x41c1 +#define CAR_mmCRTC4_CRTC_MVP_STATUS 0x43c1 +#define CAR_mmCRTC5_CRTC_MVP_STATUS 0x45c1 +#define CAR_mmCRTC_MASTER_EN 0x1bc2 +#define CAR_mmCRTC0_CRTC_MASTER_EN 0x1bc2 +#define CAR_mmCRTC1_CRTC_MASTER_EN 0x1dc2 +#define CAR_mmCRTC2_CRTC_MASTER_EN 0x1fc2 +#define CAR_mmCRTC3_CRTC_MASTER_EN 0x41c2 +#define CAR_mmCRTC4_CRTC_MASTER_EN 0x43c2 +#define CAR_mmCRTC5_CRTC_MASTER_EN 0x45c2 +#define CAR_mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define CAR_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define CAR_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 +#define CAR_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 +#define CAR_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 +#define CAR_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 +#define CAR_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 +#define CAR_mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define CAR_mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define CAR_mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 +#define CAR_mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 +#define CAR_mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 +#define CAR_mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 +#define CAR_mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 +#define CAR_mmCRTC_OVERSCAN_COLOR 0x1bc8 +#define CAR_mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 +#define CAR_mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 +#define CAR_mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 +#define CAR_mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 +#define CAR_mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 +#define CAR_mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 +#define CAR_mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define CAR_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define CAR_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 +#define CAR_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 +#define CAR_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 +#define CAR_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 +#define CAR_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 +#define CAR_mmCRTC_BLANK_DATA_COLOR 0x1bca +#define CAR_mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca +#define CAR_mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca +#define CAR_mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca +#define CAR_mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca +#define CAR_mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca +#define CAR_mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca +#define CAR_mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define CAR_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define CAR_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb +#define CAR_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb +#define CAR_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb +#define CAR_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb +#define CAR_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb +#define CAR_mmCRTC_BLACK_COLOR 0x1bcc +#define CAR_mmCRTC0_CRTC_BLACK_COLOR 0x1bcc +#define CAR_mmCRTC1_CRTC_BLACK_COLOR 0x1dcc +#define CAR_mmCRTC2_CRTC_BLACK_COLOR 0x1fcc +#define CAR_mmCRTC3_CRTC_BLACK_COLOR 0x41cc +#define CAR_mmCRTC4_CRTC_BLACK_COLOR 0x43cc +#define CAR_mmCRTC5_CRTC_BLACK_COLOR 0x45cc +#define CAR_mmCRTC_BLACK_COLOR_EXT 0x1bcd +#define CAR_mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd +#define CAR_mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd +#define CAR_mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd +#define CAR_mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd +#define CAR_mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd +#define CAR_mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd +#define CAR_mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce +#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce +#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce +#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce +#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce +#define CAR_mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf +#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf +#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf +#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf +#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf +#define CAR_mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 +#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 +#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 +#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 +#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 +#define CAR_mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 +#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 +#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 +#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 +#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 +#define CAR_mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 +#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 +#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 +#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 +#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 +#define CAR_mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 +#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 +#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 +#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 +#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 +#define CAR_mmCRTC_CRC_CNTL 0x1bd4 +#define CAR_mmCRTC0_CRTC_CRC_CNTL 0x1bd4 +#define CAR_mmCRTC1_CRTC_CRC_CNTL 0x1dd4 +#define CAR_mmCRTC2_CRTC_CRC_CNTL 0x1fd4 +#define CAR_mmCRTC3_CRTC_CRC_CNTL 0x41d4 +#define CAR_mmCRTC4_CRTC_CRC_CNTL 0x43d4 +#define CAR_mmCRTC5_CRTC_CRC_CNTL 0x45d4 +#define CAR_mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define CAR_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define CAR_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 +#define CAR_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 +#define CAR_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 +#define CAR_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 +#define CAR_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 +#define CAR_mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define CAR_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define CAR_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 +#define CAR_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 +#define CAR_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 +#define CAR_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 +#define CAR_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 +#define CAR_mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define CAR_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define CAR_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 +#define CAR_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 +#define CAR_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 +#define CAR_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 +#define CAR_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 +#define CAR_mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define CAR_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define CAR_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 +#define CAR_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 +#define CAR_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 +#define CAR_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 +#define CAR_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 +#define CAR_mmCRTC_CRC0_DATA_RG 0x1bd9 +#define CAR_mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 +#define CAR_mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 +#define CAR_mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 +#define CAR_mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 +#define CAR_mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 +#define CAR_mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 +#define CAR_mmCRTC_CRC0_DATA_B 0x1bda +#define CAR_mmCRTC0_CRTC_CRC0_DATA_B 0x1bda +#define CAR_mmCRTC1_CRTC_CRC0_DATA_B 0x1dda +#define CAR_mmCRTC2_CRTC_CRC0_DATA_B 0x1fda +#define CAR_mmCRTC3_CRTC_CRC0_DATA_B 0x41da +#define CAR_mmCRTC4_CRTC_CRC0_DATA_B 0x43da +#define CAR_mmCRTC5_CRTC_CRC0_DATA_B 0x45da +#define CAR_mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define CAR_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define CAR_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb +#define CAR_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb +#define CAR_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db +#define CAR_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db +#define CAR_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db +#define CAR_mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define CAR_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define CAR_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc +#define CAR_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc +#define CAR_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc +#define CAR_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc +#define CAR_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc +#define CAR_mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define CAR_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define CAR_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd +#define CAR_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd +#define CAR_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd +#define CAR_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd +#define CAR_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd +#define CAR_mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define CAR_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define CAR_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde +#define CAR_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde +#define CAR_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de +#define CAR_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de +#define CAR_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de +#define CAR_mmCRTC_CRC1_DATA_RG 0x1bdf +#define CAR_mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf +#define CAR_mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf +#define CAR_mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf +#define CAR_mmCRTC3_CRTC_CRC1_DATA_RG 0x41df +#define CAR_mmCRTC4_CRTC_CRC1_DATA_RG 0x43df +#define CAR_mmCRTC5_CRTC_CRC1_DATA_RG 0x45df +#define CAR_mmCRTC_CRC1_DATA_B 0x1be0 +#define CAR_mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 +#define CAR_mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 +#define CAR_mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 +#define CAR_mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 +#define CAR_mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 +#define CAR_mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 +#define CAR_mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define CAR_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define CAR_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 +#define CAR_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 +#define CAR_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 +#define CAR_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 +#define CAR_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 +#define CAR_mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define CAR_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define CAR_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 +#define CAR_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 +#define CAR_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define CAR_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 +#define CAR_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 +#define CAR_mmCRTC_GSL_VSYNC_GAP 0x1b79 +#define CAR_mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 +#define CAR_mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 +#define CAR_mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 +#define CAR_mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 +#define CAR_mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 +#define CAR_mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 +#define CAR_mmCRTC_GSL_WINDOW 0x1b7a +#define CAR_mmCRTC0_CRTC_GSL_WINDOW 0x1b7a +#define CAR_mmCRTC1_CRTC_GSL_WINDOW 0x1d7a +#define CAR_mmCRTC2_CRTC_GSL_WINDOW 0x1f7a +#define CAR_mmCRTC3_CRTC_GSL_WINDOW 0x417a +#define CAR_mmCRTC4_CRTC_GSL_WINDOW 0x437a +#define CAR_mmCRTC5_CRTC_GSL_WINDOW 0x457a +#define CAR_mmCRTC_GSL_CONTROL 0x1b7b +#define CAR_mmCRTC0_CRTC_GSL_CONTROL 0x1b7b +#define CAR_mmCRTC1_CRTC_GSL_CONTROL 0x1d7b +#define CAR_mmCRTC2_CRTC_GSL_CONTROL 0x1f7b +#define CAR_mmCRTC3_CRTC_GSL_CONTROL 0x417b +#define CAR_mmCRTC4_CRTC_GSL_CONTROL 0x437b +#define CAR_mmCRTC5_CRTC_GSL_CONTROL 0x457b +#define CAR_mmCRTC_TEST_DEBUG_INDEX 0x1bc6 +#define CAR_mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 +#define CAR_mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 +#define CAR_mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 +#define CAR_mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 +#define CAR_mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 +#define CAR_mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 +#define CAR_mmCRTC_TEST_DEBUG_DATA 0x1bc7 +#define CAR_mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 +#define CAR_mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 +#define CAR_mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 +#define CAR_mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 +#define CAR_mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 +#define CAR_mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 +#define CAR_mmDAC_ENABLE 0x16aa +#define CAR_mmDAC_SOURCE_SELECT 0x16ab +#define CAR_mmDAC_CRC_EN 0x16ac +#define CAR_mmDAC_CRC_CONTROL 0x16ad +#define CAR_mmDAC_CRC_SIG_RGB_MASK 0x16ae +#define CAR_mmDAC_CRC_SIG_CONTROL_MASK 0x16af +#define CAR_mmDAC_CRC_SIG_RGB 0x16b0 +#define CAR_mmDAC_CRC_SIG_CONTROL 0x16b1 +#define CAR_mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 +#define CAR_mmDAC_STEREOSYNC_SELECT 0x16b3 +#define CAR_mmDAC_AUTODETECT_CONTROL 0x16b4 +#define CAR_mmDAC_AUTODETECT_CONTROL2 0x16b5 +#define CAR_mmDAC_AUTODETECT_CONTROL3 0x16b6 +#define CAR_mmDAC_AUTODETECT_STATUS 0x16b7 +#define CAR_mmDAC_AUTODETECT_INT_CONTROL 0x16b8 +#define CAR_mmDAC_FORCE_OUTPUT_CNTL 0x16b9 +#define CAR_mmDAC_FORCE_DATA 0x16ba +#define CAR_mmDAC_POWERDOWN 0x16bb +#define CAR_mmDAC_CONTROL 0x16bc +#define CAR_mmDAC_COMPARATOR_ENABLE 0x16bd +#define CAR_mmDAC_COMPARATOR_OUTPUT 0x16be +#define CAR_mmDAC_PWR_CNTL 0x16bf +#define CAR_mmDAC_DFT_CONFIG 0x16c0 +#define CAR_mmDAC_FIFO_STATUS 0x16c1 +#define CAR_mmDAC_TEST_DEBUG_INDEX 0x16c2 +#define CAR_mmDAC_TEST_DEBUG_DATA 0x16c3 +#define CAR_mmPERFCOUNTER_CNTL 0x170 +#define CAR_mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 +#define CAR_mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364 +#define CAR_mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8 +#define CAR_mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24 +#define CAR_mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24 +#define CAR_mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24 +#define CAR_mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124 +#define CAR_mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324 +#define CAR_mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524 +#define CAR_mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724 +#define CAR_mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0 +#define CAR_mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68 +#define CAR_mmPERFCOUNTER_STATE 0x171 +#define CAR_mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 +#define CAR_mmDC_PERFMON1_PERFCOUNTER_STATE 0x365 +#define CAR_mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9 +#define CAR_mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25 +#define CAR_mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25 +#define CAR_mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25 +#define CAR_mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125 +#define CAR_mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325 +#define CAR_mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525 +#define CAR_mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725 +#define CAR_mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1 +#define CAR_mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69 +#define CAR_mmPERFMON_CNTL 0x173 +#define CAR_mmDC_PERFMON0_PERFMON_CNTL 0x173 +#define CAR_mmDC_PERFMON1_PERFMON_CNTL 0x367 +#define CAR_mmDC_PERFMON2_PERFMON_CNTL 0x18cb +#define CAR_mmDC_PERFMON3_PERFMON_CNTL 0x1b27 +#define CAR_mmDC_PERFMON4_PERFMON_CNTL 0x1d27 +#define CAR_mmDC_PERFMON5_PERFMON_CNTL 0x1f27 +#define CAR_mmDC_PERFMON6_PERFMON_CNTL 0x4127 +#define CAR_mmDC_PERFMON7_PERFMON_CNTL 0x4327 +#define CAR_mmDC_PERFMON8_PERFMON_CNTL 0x4527 +#define CAR_mmDC_PERFMON9_PERFMON_CNTL 0x4727 +#define CAR_mmDC_PERFMON10_PERFMON_CNTL 0x59a3 +#define CAR_mmDC_PERFMON11_PERFMON_CNTL 0x5f6b +#define CAR_mmPERFMON_CNTL2 0x17a +#define CAR_mmDC_PERFMON0_PERFMON_CNTL2 0x17a +#define CAR_mmDC_PERFMON1_PERFMON_CNTL2 0x36e +#define CAR_mmDC_PERFMON2_PERFMON_CNTL2 0x18d2 +#define CAR_mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e +#define CAR_mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e +#define CAR_mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e +#define CAR_mmDC_PERFMON6_PERFMON_CNTL2 0x412e +#define CAR_mmDC_PERFMON7_PERFMON_CNTL2 0x432e +#define CAR_mmDC_PERFMON8_PERFMON_CNTL2 0x452e +#define CAR_mmDC_PERFMON9_PERFMON_CNTL2 0x472e +#define CAR_mmDC_PERFMON10_PERFMON_CNTL2 0x59aa +#define CAR_mmDC_PERFMON11_PERFMON_CNTL2 0x5f72 +#define CAR_mmPERFMON_CVALUE_INT_MISC 0x172 +#define CAR_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 +#define CAR_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366 +#define CAR_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca +#define CAR_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26 +#define CAR_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26 +#define CAR_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26 +#define CAR_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126 +#define CAR_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326 +#define CAR_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526 +#define CAR_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726 +#define CAR_mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2 +#define CAR_mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a +#define CAR_mmPERFMON_CVALUE_LOW 0x174 +#define CAR_mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 +#define CAR_mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368 +#define CAR_mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc +#define CAR_mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28 +#define CAR_mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28 +#define CAR_mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28 +#define CAR_mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128 +#define CAR_mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328 +#define CAR_mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528 +#define CAR_mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728 +#define CAR_mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4 +#define CAR_mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c +#define CAR_mmPERFMON_HI 0x175 +#define CAR_mmDC_PERFMON0_PERFMON_HI 0x175 +#define CAR_mmDC_PERFMON1_PERFMON_HI 0x369 +#define CAR_mmDC_PERFMON2_PERFMON_HI 0x18cd +#define CAR_mmDC_PERFMON3_PERFMON_HI 0x1b29 +#define CAR_mmDC_PERFMON4_PERFMON_HI 0x1d29 +#define CAR_mmDC_PERFMON5_PERFMON_HI 0x1f29 +#define CAR_mmDC_PERFMON6_PERFMON_HI 0x4129 +#define CAR_mmDC_PERFMON7_PERFMON_HI 0x4329 +#define CAR_mmDC_PERFMON8_PERFMON_HI 0x4529 +#define CAR_mmDC_PERFMON9_PERFMON_HI 0x4729 +#define CAR_mmDC_PERFMON10_PERFMON_HI 0x59a5 +#define CAR_mmDC_PERFMON11_PERFMON_HI 0x5f6d +#define CAR_mmPERFMON_LOW 0x176 +#define CAR_mmDC_PERFMON0_PERFMON_LOW 0x176 +#define CAR_mmDC_PERFMON1_PERFMON_LOW 0x36a +#define CAR_mmDC_PERFMON2_PERFMON_LOW 0x18ce +#define CAR_mmDC_PERFMON3_PERFMON_LOW 0x1b2a +#define CAR_mmDC_PERFMON4_PERFMON_LOW 0x1d2a +#define CAR_mmDC_PERFMON5_PERFMON_LOW 0x1f2a +#define CAR_mmDC_PERFMON6_PERFMON_LOW 0x412a +#define CAR_mmDC_PERFMON7_PERFMON_LOW 0x432a +#define CAR_mmDC_PERFMON8_PERFMON_LOW 0x452a +#define CAR_mmDC_PERFMON9_PERFMON_LOW 0x472a +#define CAR_mmDC_PERFMON10_PERFMON_LOW 0x59a6 +#define CAR_mmDC_PERFMON11_PERFMON_LOW 0x5f6e +#define CAR_mmPERFMON_TEST_DEBUG_INDEX 0x177 +#define CAR_mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 +#define CAR_mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b +#define CAR_mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf +#define CAR_mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b +#define CAR_mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b +#define CAR_mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b +#define CAR_mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b +#define CAR_mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b +#define CAR_mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b +#define CAR_mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b +#define CAR_mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7 +#define CAR_mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f +#define CAR_mmPERFMON_TEST_DEBUG_DATA 0x178 +#define CAR_mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 +#define CAR_mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c +#define CAR_mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0 +#define CAR_mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c +#define CAR_mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c +#define CAR_mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c +#define CAR_mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c +#define CAR_mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c +#define CAR_mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c +#define CAR_mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c +#define CAR_mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8 +#define CAR_mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70 +#define CAR_mmREFCLK_CNTL 0x109 +#define CAR_mmDCCG_CBUS_WRCMD_DELAY 0x110 +#define CAR_mmDPREFCLK_CNTL 0x118 +#define CAR_mmDCE_VERSION 0x11e +#define CAR_mmAVSYNC_COUNTER_WRITE 0x12a +#define CAR_mmAVSYNC_COUNTER_CONTROL 0x12b +#define CAR_mmAVSYNC_COUNTER_READ 0x12f +#define CAR_mmDCCG_GTC_CNTL 0x120 +#define CAR_mmDCCG_GTC_DTO_INCR 0x121 +#define CAR_mmDCCG_GTC_DTO_MODULO 0x122 +#define CAR_mmDCCG_GTC_CURRENT 0x123 +#define CAR_mmDCCG_DS_DTO_INCR 0x113 +#define CAR_mmDCCG_DS_DTO_MODULO 0x114 +#define CAR_mmDCCG_DS_CNTL 0x115 +#define CAR_mmDCCG_DS_HW_CAL_INTERVAL 0x116 +#define CAR_mmDCCG_DS_DEBUG_CNTL 0x112 +#define CAR_mmDMCU_SMU_INTERRUPT_CNTL 0x12c +#define CAR_mmSMU_CONTROL 0x12d +#define CAR_mmSMU_INTERRUPT_CONTROL 0x12e +#define CAR_mmDAC_CLK_ENABLE 0x128 +#define CAR_mmDVO_CLK_ENABLE 0x129 +#define CAR_mmDCCG_GATE_DISABLE_CNTL 0x134 +#define CAR_mmDCCG_GATE_DISABLE_CNTL2 0x13c +#define CAR_mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 +#define CAR_mmSCLK_CGTT_BLK_CTRL_REG 0x136 +#define CAR_mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 +#define CAR_mmREFCLK_CGTT_BLK_CTRL_REG 0x10b +#define CAR_mmSYMCLK_CGTT_BLK_CTRL_REG 0x13d +#define CAR_mmDCCG_CAC_STATUS 0x137 +#define CAR_mmPIXCLK1_RESYNC_CNTL 0x138 +#define CAR_mmPIXCLK2_RESYNC_CNTL 0x139 +#define CAR_mmPIXCLK0_RESYNC_CNTL 0x13a +#define CAR_mmPHYPLL_PIXCLK_CNTL 0x13e +#define CAR_mmMICROSECOND_TIME_BASE_DIV 0x13b +#define CAR_mmDCCG_DISP_CNTL_REG 0x13f +#define CAR_mmMILLISECOND_TIME_BASE_DIV 0x130 +#define CAR_mmDISPCLK_FREQ_CHANGE_CNTL 0x131 +#define CAR_mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 +#define CAR_mmDCCG_PERFMON_CNTL 0x133 +#define CAR_mmDCCG_PERFMON_CNTL2 0x10e +#define CAR_mmCRTC0_PIXEL_RATE_CNTL 0x140 +#define CAR_mmDP_DTO0_PHASE 0x141 +#define CAR_mmDP_DTO0_MODULO 0x142 +#define CAR_mmCRTC1_PIXEL_RATE_CNTL 0x144 +#define CAR_mmDP_DTO1_PHASE 0x145 +#define CAR_mmDP_DTO1_MODULO 0x146 +#define CAR_mmCRTC2_PIXEL_RATE_CNTL 0x148 +#define CAR_mmDP_DTO2_PHASE 0x149 +#define CAR_mmDP_DTO2_MODULO 0x14a +#define CAR_mmCRTC3_PIXEL_RATE_CNTL 0x14c +#define CAR_mmDP_DTO3_PHASE 0x14d +#define CAR_mmDP_DTO3_MODULO 0x14e +#define CAR_mmCRTC4_PIXEL_RATE_CNTL 0x150 +#define CAR_mmDP_DTO4_PHASE 0x151 +#define CAR_mmDP_DTO4_MODULO 0x152 +#define CAR_mmCRTC5_PIXEL_RATE_CNTL 0x154 +#define CAR_mmDP_DTO5_PHASE 0x155 +#define CAR_mmDP_DTO5_MODULO 0x156 +#define CAR_mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x104 +#define CAR_mmDCCG_SOFT_RESET 0x15f +#define CAR_mmSYMCLKA_CLOCK_ENABLE 0x160 +#define CAR_mmSYMCLKB_CLOCK_ENABLE 0x161 +#define CAR_mmSYMCLKC_CLOCK_ENABLE 0x162 +#define CAR_mmSYMCLKD_CLOCK_ENABLE 0x163 +#define CAR_mmSYMCLKE_CLOCK_ENABLE 0x164 +#define CAR_mmSYMCLKF_CLOCK_ENABLE 0x165 +#define CAR_mmSYMCLKG_CLOCK_ENABLE 0x117 +#define CAR_mmDPDBG_CLK_FORCE_CONTROL 0x10d +#define CAR_mmDCCG_AUDIO_DTO_SOURCE 0x16b +#define CAR_mmDCCG_AUDIO_DTO0_PHASE 0x16c +#define CAR_mmDCCG_AUDIO_DTO0_MODULE 0x16d +#define CAR_mmDCCG_AUDIO_DTO1_PHASE 0x16e +#define CAR_mmDCCG_AUDIO_DTO1_MODULE 0x16f +#define CAR_mmDCCG_TEST_DEBUG_INDEX 0x17c +#define CAR_mmDCCG_TEST_DEBUG_DATA 0x17d +#define CAR_mmDCCG_TEST_CLK_SEL 0x17e +#define CAR_mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 +#define CAR_mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 +#define CAR_mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 +#define CAR_mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 +#define CAR_mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 +#define CAR_mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 +#define CAR_mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa +#define CAR_mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb +#define CAR_mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc +#define CAR_mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd +#define CAR_mmCPLL_MACRO_CNTL_RESERVED10 0x5fda +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe +#define CAR_mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 +#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 +#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff +#define CAR_mmPLL_MACRO_CNTL_RESERVED0 0x1700 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 +#define CAR_mmPLL_MACRO_CNTL_RESERVED1 0x1701 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 +#define CAR_mmPLL_MACRO_CNTL_RESERVED2 0x1702 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 +#define CAR_mmPLL_MACRO_CNTL_RESERVED3 0x1703 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 +#define CAR_mmPLL_MACRO_CNTL_RESERVED4 0x1704 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 +#define CAR_mmPLL_MACRO_CNTL_RESERVED5 0x1705 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 +#define CAR_mmPLL_MACRO_CNTL_RESERVED6 0x1706 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a +#define CAR_mmPLL_MACRO_CNTL_RESERVED7 0x1707 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b +#define CAR_mmPLL_MACRO_CNTL_RESERVED8 0x1708 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c +#define CAR_mmPLL_MACRO_CNTL_RESERVED9 0x1709 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d +#define CAR_mmPLL_MACRO_CNTL_RESERVED10 0x170a +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e +#define CAR_mmPLL_MACRO_CNTL_RESERVED11 0x170b +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f +#define CAR_mmPLL_MACRO_CNTL_RESERVED12 0x170c +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 +#define CAR_mmPLL_MACRO_CNTL_RESERVED13 0x170d +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 +#define CAR_mmPLL_MACRO_CNTL_RESERVED14 0x170e +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 +#define CAR_mmPLL_MACRO_CNTL_RESERVED15 0x170f +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 +#define CAR_mmPLL_MACRO_CNTL_RESERVED16 0x1710 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 +#define CAR_mmPLL_MACRO_CNTL_RESERVED17 0x1711 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 +#define CAR_mmPLL_MACRO_CNTL_RESERVED18 0x1712 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 +#define CAR_mmPLL_MACRO_CNTL_RESERVED19 0x1713 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 +#define CAR_mmPLL_MACRO_CNTL_RESERVED20 0x1714 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 +#define CAR_mmPLL_MACRO_CNTL_RESERVED21 0x1715 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 +#define CAR_mmPLL_MACRO_CNTL_RESERVED22 0x1716 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a +#define CAR_mmPLL_MACRO_CNTL_RESERVED23 0x1717 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b +#define CAR_mmPLL_MACRO_CNTL_RESERVED24 0x1718 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c +#define CAR_mmPLL_MACRO_CNTL_RESERVED25 0x1719 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d +#define CAR_mmPLL_MACRO_CNTL_RESERVED26 0x171a +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e +#define CAR_mmPLL_MACRO_CNTL_RESERVED27 0x171b +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f +#define CAR_mmPLL_MACRO_CNTL_RESERVED28 0x171c +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 +#define CAR_mmPLL_MACRO_CNTL_RESERVED29 0x171d +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 +#define CAR_mmPLL_MACRO_CNTL_RESERVED30 0x171e +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 +#define CAR_mmPLL_MACRO_CNTL_RESERVED31 0x171f +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 +#define CAR_mmPLL_MACRO_CNTL_RESERVED32 0x1720 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 +#define CAR_mmPLL_MACRO_CNTL_RESERVED33 0x1721 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 +#define CAR_mmPLL_MACRO_CNTL_RESERVED34 0x1722 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 +#define CAR_mmPLL_MACRO_CNTL_RESERVED35 0x1723 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 +#define CAR_mmPLL_MACRO_CNTL_RESERVED36 0x1724 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 +#define CAR_mmPLL_MACRO_CNTL_RESERVED37 0x1725 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 +#define CAR_mmPLL_MACRO_CNTL_RESERVED38 0x1726 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a +#define CAR_mmPLL_MACRO_CNTL_RESERVED39 0x1727 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b +#define CAR_mmPLL_MACRO_CNTL_RESERVED40 0x1728 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c +#define CAR_mmPLL_MACRO_CNTL_RESERVED41 0x1729 +#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 +#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 +#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d +#define CAR_mmDENTIST_DISPCLK_CNTL 0x124 +#define CAR_mmDCDEBUG_BUS_CLK1_SEL 0x16c4 +#define CAR_mmDCDEBUG_BUS_CLK2_SEL 0x16c5 +#define CAR_mmDCDEBUG_BUS_CLK3_SEL 0x16c6 +#define CAR_mmDCDEBUG_BUS_CLK4_SEL 0x16c7 +#define CAR_mmDCDEBUG_BUS_CLK5_SEL 0x16c8 +#define CAR_mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 +#define CAR_mmDCDEBUG_OUT_CNTL 0x16ca +#define CAR_mmDCDEBUG_OUT_DATA 0x16cb +#define CAR_mmDMIF_ADDR_CONFIG 0x2f5 +#define CAR_mmDMIF_CONTROL 0x2f6 +#define CAR_mmDMIF_STATUS 0x2f7 +#define CAR_mmDMIF_HW_DEBUG 0x2f8 +#define CAR_mmDMIF_ARBITRATION_CONTROL 0x2f9 +#define CAR_mmPIPE0_ARBITRATION_CONTROL3 0x2fa +#define CAR_mmPIPE1_ARBITRATION_CONTROL3 0x2fb +#define CAR_mmPIPE2_ARBITRATION_CONTROL3 0x2fc +#define CAR_mmPIPE3_ARBITRATION_CONTROL3 0x2fd +#define CAR_mmPIPE4_ARBITRATION_CONTROL3 0x2fe +#define CAR_mmPIPE5_ARBITRATION_CONTROL3 0x2ff +#define CAR_mmPIPE6_ARBITRATION_CONTROL3 0x32a +#define CAR_mmPIPE7_ARBITRATION_CONTROL3 0x32b +#define CAR_mmDMIF_P_VMID 0x300 +#define CAR_mmDMIF_URG_OVERRIDE 0x329 +#define CAR_mmDMIF_TEST_DEBUG_INDEX 0x301 +#define CAR_mmDMIF_TEST_DEBUG_DATA 0x302 +#define CAR_ixDMIF_DEBUG02_CORE0 0x2 +#define CAR_ixDMIF_DEBUG02_CORE1 0xa +#define CAR_mmDMIF_ADDR_CALC 0x303 +#define CAR_mmDMIF_STATUS2 0x304 +#define CAR_mmPIPE0_MAX_REQUESTS 0x305 +#define CAR_mmPIPE1_MAX_REQUESTS 0x306 +#define CAR_mmPIPE2_MAX_REQUESTS 0x307 +#define CAR_mmPIPE3_MAX_REQUESTS 0x308 +#define CAR_mmPIPE4_MAX_REQUESTS 0x309 +#define CAR_mmPIPE5_MAX_REQUESTS 0x30a +#define CAR_mmPIPE6_MAX_REQUESTS 0x32c +#define CAR_mmPIPE7_MAX_REQUESTS 0x32d +#define CAR_mmDVMM_REG_RD_STATUS 0x32e +#define CAR_mmDVMM_REG_RD_DATA 0x32f +#define CAR_mmDVMM_PTE_REQ 0x330 +#define CAR_mmDVMM_CNTL 0x331 +#define CAR_mmDVMM_FAULT_STATUS 0x332 +#define CAR_mmDVMM_FAULT_ADDR 0x333 +#define CAR_mmLOW_POWER_TILING_CONTROL 0x30b +#define CAR_mmMCIF_CONTROL 0x30c +#define CAR_mmMCIF_WRITE_COMBINE_CONTROL 0x30d +#define CAR_mmMCIF_TEST_DEBUG_INDEX 0x30e +#define CAR_mmMCIF_TEST_DEBUG_DATA 0x30f +#define CAR_ixIDDCCIF02_DBG_DCCIF_C 0x9 +#define CAR_ixIDDCCIF04_DBG_DCCIF_E 0xb +#define CAR_ixIDDCCIF05_DBG_DCCIF_F 0xc +#define CAR_mmMCIF_VMID 0x310 +#define CAR_mmMCIF_MEM_CONTROL 0x311 +#define CAR_mmCC_DC_PIPE_DIS 0x312 +#define CAR_mmMC_DC_INTERFACE_NACK_STATUS 0x313 +#define CAR_mmRBBMIF_TIMEOUT 0x314 +#define CAR_mmRBBMIF_STATUS 0x315 +#define CAR_mmRBBMIF_TIMEOUT_DIS 0x316 +#define CAR_mmRBBMIF_STATUS_FLAG 0x327 +#define CAR_mmDCI_MEM_PWR_STATUS 0x317 +#define CAR_mmDCI_MEM_PWR_STATUS2 0x318 +#define CAR_mmDCI_CLK_CNTL 0x319 +#define CAR_mmDCI_CLK_RAMP_CNTL 0x31a +#define CAR_mmDCI_MEM_PWR_CNTL 0x31b +#define CAR_mmDCI_MEM_PWR_CNTL2 0x31c +#define CAR_mmDCI_MEM_PWR_CNTL3 0x31d +#define CAR_mmDVMM_PTE_PGMEM_CONTROL 0x335 +#define CAR_mmDVMM_PTE_PGMEM_STATE 0x336 +#define CAR_mmDCI_SOFT_RESET 0x328 +#define CAR_mmDCI_MISC 0x334 +#define CAR_mmDCI_TEST_DEBUG_INDEX 0x31e +#define CAR_mmDCI_TEST_DEBUG_DATA 0x31f +#define CAR_mmDCI_DEBUG_CONFIG 0x320 +#define CAR_mmPIPE0_DMIF_BUFFER_CONTROL 0x321 +#define CAR_mmPIPE1_DMIF_BUFFER_CONTROL 0x322 +#define CAR_mmPIPE2_DMIF_BUFFER_CONTROL 0x323 +#define CAR_mmPIPE3_DMIF_BUFFER_CONTROL 0x324 +#define CAR_mmPIPE4_DMIF_BUFFER_CONTROL 0x325 +#define CAR_mmPIPE5_DMIF_BUFFER_CONTROL 0x326 +#define CAR_mmDC_GENERICA 0x4800 +#define CAR_mmDC_GENERICB 0x4801 +#define CAR_mmDC_PAD_EXTERN_SIG 0x4802 +#define CAR_mmDC_REF_CLK_CNTL 0x4803 +#define CAR_mmDC_GPIO_DEBUG 0x4804 +#define CAR_mmUNIPHYA_LINK_CNTL 0x4805 +#define CAR_mmUNIPHYB_LINK_CNTL 0x4807 +#define CAR_mmUNIPHYC_LINK_CNTL 0x4809 +#define CAR_mmUNIPHYD_LINK_CNTL 0x480b +#define CAR_mmUNIPHYE_LINK_CNTL 0x480d +#define CAR_mmUNIPHYF_LINK_CNTL 0x480f +#define CAR_mmUNIPHYG_LINK_CNTL 0x4811 +#define CAR_mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 +#define CAR_mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 +#define CAR_mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a +#define CAR_mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c +#define CAR_mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e +#define CAR_mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 +#define CAR_mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 +#define CAR_mmUNIPHYLPA_LINK_CNTL 0x4847 +#define CAR_mmUNIPHYLPB_LINK_CNTL 0x4848 +#define CAR_mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x4849 +#define CAR_mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x484a +#define CAR_mmUNIPHY_IMPCAL_LINKA 0x4838 +#define CAR_mmUNIPHY_IMPCAL_LINKB 0x4839 +#define CAR_mmUNIPHY_IMPCAL_LINKC 0x483f +#define CAR_mmUNIPHY_IMPCAL_LINKD 0x4840 +#define CAR_mmUNIPHY_IMPCAL_LINKE 0x4843 +#define CAR_mmUNIPHY_IMPCAL_LINKF 0x4844 +#define CAR_mmUNIPHY_IMPCAL_PERIOD 0x483a +#define CAR_mmAUXP_IMPCAL 0x483b +#define CAR_mmAUXN_IMPCAL 0x483c +#define CAR_mmDCIO_IMPCAL_CNTL 0x483d +#define CAR_mmUNIPHY_IMPCAL_PSW_AB 0x483e +#define CAR_mmDCIO_IMPCAL_CNTL_CD 0x4841 +#define CAR_mmUNIPHY_IMPCAL_PSW_CD 0x4842 +#define CAR_mmDCIO_IMPCAL_CNTL_EF 0x4845 +#define CAR_mmUNIPHY_IMPCAL_PSW_EF 0x4846 +#define CAR_mmDCIO_WRCMD_DELAY 0x4816 +#define CAR_mmDC_PINSTRAPS 0x4818 +#define CAR_mmDC_DVODATA_CONFIG 0x481a +#define CAR_mmLVTMA_PWRSEQ_CNTL 0x481b +#define CAR_mmLVTMA_PWRSEQ_STATE 0x481c +#define CAR_mmLVTMA_PWRSEQ_REF_DIV 0x481d +#define CAR_mmLVTMA_PWRSEQ_DELAY1 0x481e +#define CAR_mmLVTMA_PWRSEQ_DELAY2 0x481f +#define CAR_mmBL_PWM_CNTL 0x4820 +#define CAR_mmBL_PWM_CNTL2 0x4821 +#define CAR_mmBL_PWM_PERIOD_CNTL 0x4822 +#define CAR_mmBL_PWM_GRP1_REG_LOCK 0x4823 +#define CAR_mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 +#define CAR_mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 +#define CAR_mmDCIO_GSL0_CNTL 0x4826 +#define CAR_mmDCIO_GSL1_CNTL 0x4827 +#define CAR_mmDCIO_GSL2_CNTL 0x4828 +#define CAR_mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 +#define CAR_mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a +#define CAR_mmDC_GPU_TIMER_READ 0x482b +#define CAR_mmDC_GPU_TIMER_READ_CNTL 0x482c +#define CAR_mmDCIO_CLOCK_CNTL 0x482d +#define CAR_mmDCIO_DEBUG 0x482f +#define CAR_mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 +#define CAR_mmDBG_OUT_CNTL 0x4834 +#define CAR_mmDCIO_DEBUG_CONFIG 0x4835 +#define CAR_mmDCIO_SOFT_RESET 0x4836 +#define CAR_mmDCIO_DPHY_SEL 0x4837 +#define CAR_mmDCIO_TEST_DEBUG_INDEX 0x4831 +#define CAR_mmDCIO_TEST_DEBUG_DATA 0x4832 +#define CAR_ixDCIO_DEBUG1 0x1 +#define CAR_ixDCIO_DEBUG2 0x2 +#define CAR_ixDCIO_DEBUG3 0x3 +#define CAR_ixDCIO_DEBUG4 0x4 +#define CAR_ixDCIO_DEBUG5 0x5 +#define CAR_ixDCIO_DEBUG6 0x6 +#define CAR_ixDCIO_DEBUG7 0x7 +#define CAR_ixDCIO_DEBUG8 0x8 +#define CAR_ixDCIO_DEBUG9 0x9 +#define CAR_ixDCIO_DEBUGA 0xa +#define CAR_ixDCIO_DEBUGB 0xb +#define CAR_ixDCIO_DEBUGC 0xc +#define CAR_ixDCIO_DEBUGD 0xd +#define CAR_ixDCIO_DEBUGE 0xe +#define CAR_ixDCIO_DEBUGF 0xf +#define CAR_ixDCIO_DEBUG10 0x10 +#define CAR_ixDCIO_DEBUG11 0x11 +#define CAR_ixDCIO_DEBUG12 0x12 +#define CAR_ixDCIO_DEBUG13 0x13 +#define CAR_ixDCIO_DEBUG14 0x14 +#define CAR_ixDCIO_DEBUG15 0x15 +#define CAR_ixDCIO_DEBUG16 0x16 +#define CAR_ixDCIO_DEBUG17 0x17 +#define CAR_ixDCIO_DEBUG18 0x18 +#define CAR_ixDCIO_DEBUG19 0x19 +#define CAR_ixDCIO_DEBUG1A 0x1a +#define CAR_ixDCIO_DEBUG1B 0x1b +#define CAR_ixDCIO_DEBUG_ID 0x0 +#define CAR_mmDC_GPIO_GENERIC_MASK 0x4860 +#define CAR_mmDC_GPIO_GENERIC_A 0x4861 +#define CAR_mmDC_GPIO_GENERIC_EN 0x4862 +#define CAR_mmDC_GPIO_GENERIC_Y 0x4863 +#define CAR_mmDC_GPIO_DVODATA_MASK 0x4864 +#define CAR_mmDC_GPIO_DVODATA_A 0x4865 +#define CAR_mmDC_GPIO_DVODATA_EN 0x4866 +#define CAR_mmDC_GPIO_DVODATA_Y 0x4867 +#define CAR_mmDC_GPIO_DDC1_MASK 0x4868 +#define CAR_mmDC_GPIO_DDC1_A 0x4869 +#define CAR_mmDC_GPIO_DDC1_EN 0x486a +#define CAR_mmDC_GPIO_DDC1_Y 0x486b +#define CAR_mmDC_GPIO_DDC2_MASK 0x486c +#define CAR_mmDC_GPIO_DDC2_A 0x486d +#define CAR_mmDC_GPIO_DDC2_EN 0x486e +#define CAR_mmDC_GPIO_DDC2_Y 0x486f +#define CAR_mmDC_GPIO_DDC3_MASK 0x4870 +#define CAR_mmDC_GPIO_DDC3_A 0x4871 +#define CAR_mmDC_GPIO_DDC3_EN 0x4872 +#define CAR_mmDC_GPIO_DDC3_Y 0x4873 +#define CAR_mmDC_GPIO_DDC4_MASK 0x4874 +#define CAR_mmDC_GPIO_DDC4_A 0x4875 +#define CAR_mmDC_GPIO_DDC4_EN 0x4876 +#define CAR_mmDC_GPIO_DDC4_Y 0x4877 +#define CAR_mmDC_GPIO_DDC5_MASK 0x4878 +#define CAR_mmDC_GPIO_DDC5_A 0x4879 +#define CAR_mmDC_GPIO_DDC5_EN 0x487a +#define CAR_mmDC_GPIO_DDC5_Y 0x487b +#define CAR_mmDC_GPIO_DDC6_MASK 0x487c +#define CAR_mmDC_GPIO_DDC6_A 0x487d +#define CAR_mmDC_GPIO_DDC6_EN 0x487e +#define CAR_mmDC_GPIO_DDC6_Y 0x487f +#define CAR_mmDC_GPIO_DDCVGA_MASK 0x4880 +#define CAR_mmDC_GPIO_DDCVGA_A 0x4881 +#define CAR_mmDC_GPIO_DDCVGA_EN 0x4882 +#define CAR_mmDC_GPIO_DDCVGA_Y 0x4883 +#define CAR_mmDC_GPIO_SYNCA_MASK 0x4884 +#define CAR_mmDC_GPIO_SYNCA_A 0x4885 +#define CAR_mmDC_GPIO_SYNCA_EN 0x4886 +#define CAR_mmDC_GPIO_SYNCA_Y 0x4887 +#define CAR_mmDC_GPIO_GENLK_MASK 0x4888 +#define CAR_mmDC_GPIO_GENLK_A 0x4889 +#define CAR_mmDC_GPIO_GENLK_EN 0x488a +#define CAR_mmDC_GPIO_GENLK_Y 0x488b +#define CAR_mmDC_GPIO_HPD_MASK 0x488c +#define CAR_mmDC_GPIO_HPD_A 0x488d +#define CAR_mmDC_GPIO_HPD_EN 0x488e +#define CAR_mmDC_GPIO_HPD_Y 0x488f +#define CAR_mmDC_GPIO_PWRSEQ_MASK 0x4890 +#define CAR_mmDC_GPIO_PWRSEQ_A 0x4891 +#define CAR_mmDC_GPIO_PWRSEQ_EN 0x4892 +#define CAR_mmDC_GPIO_PWRSEQ_Y 0x4893 +#define CAR_mmDC_GPIO_PAD_STRENGTH_1 0x4894 +#define CAR_mmDC_GPIO_PAD_STRENGTH_2 0x4895 +#define CAR_mmPHY_AUX_CNTL 0x4897 +#define CAR_mmDC_GPIO_I2CPAD_MASK 0x4898 +#define CAR_mmDC_GPIO_I2CPAD_A 0x4899 +#define CAR_mmDC_GPIO_I2CPAD_EN 0x489a +#define CAR_mmDC_GPIO_I2CPAD_Y 0x489b +#define CAR_mmDC_GPIO_I2CPAD_STRENGTH 0x489c +#define CAR_mmDVO_VREF_CONTROL 0x489e +#define CAR_mmDVO_SKEW_ADJUST 0x489f +#define CAR_mmDAC_MACRO_CNTL_RESERVED0 0x48b8 +#define CAR_mmDAC_MACRO_CNTL_RESERVED1 0x48b9 +#define CAR_mmDAC_MACRO_CNTL_RESERVED2 0x48ba +#define CAR_mmDAC_MACRO_CNTL_RESERVED3 0x48bb +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 0x49c0 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x49e0 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 0x49c1 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x49e1 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 0x49c2 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x49e2 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 0x49c3 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x49e3 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 0x49c4 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x49e4 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 0x49c5 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x49e5 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 0x49c6 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x49e6 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 0x49c7 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x49e7 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 0x49c8 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x49e8 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 0x49c9 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x49e9 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 0x49ca +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x49ea +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 0x49cb +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x49eb +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 0x49cc +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x49ec +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 0x49cd +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x49ed +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 0x49ce +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x49ee +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 0x49cf +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x49ef +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 0x49d0 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x49f0 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 0x49d1 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x49f1 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 0x49d2 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x49f2 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 0x49d3 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x49f3 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 0x49d4 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x49f4 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 0x49d5 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x49f5 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 0x49d6 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x49f6 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 0x49d7 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x49f7 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 0x49d8 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x49f8 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9 +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919 +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939 +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959 +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999 +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 0x49d9 +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x49f9 +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 0x49da +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x49fa +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 0x49db +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x49fb +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 0x49dc +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x49fc +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 0x49dd +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x49fd +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 0x49de +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x49fe +#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff +#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f +#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f +#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f +#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f +#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f +#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 0x49df +#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x49ff +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe +#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff +#define CAR_mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a +#define CAR_mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b +#define CAR_mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c +#define CAR_mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d +#define CAR_mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e +#define CAR_mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f +#define CAR_mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED18 0x5daa +#define CAR_mmDPHY_MACRO_CNTL_RESERVED19 0x5dab +#define CAR_mmDPHY_MACRO_CNTL_RESERVED20 0x5dac +#define CAR_mmDPHY_MACRO_CNTL_RESERVED21 0x5dad +#define CAR_mmDPHY_MACRO_CNTL_RESERVED22 0x5dae +#define CAR_mmDPHY_MACRO_CNTL_RESERVED23 0x5daf +#define CAR_mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED34 0x5dba +#define CAR_mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb +#define CAR_mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc +#define CAR_mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd +#define CAR_mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe +#define CAR_mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf +#define CAR_mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED50 0x5dca +#define CAR_mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb +#define CAR_mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc +#define CAR_mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd +#define CAR_mmDPHY_MACRO_CNTL_RESERVED54 0x5dce +#define CAR_mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf +#define CAR_mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 +#define CAR_mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 +#define CAR_mmGRPH_ENABLE 0x1a00 +#define CAR_mmDCP0_GRPH_ENABLE 0x1a00 +#define CAR_mmDCP1_GRPH_ENABLE 0x1c00 +#define CAR_mmDCP2_GRPH_ENABLE 0x1e00 +#define CAR_mmDCP3_GRPH_ENABLE 0x4000 +#define CAR_mmDCP4_GRPH_ENABLE 0x4200 +#define CAR_mmDCP5_GRPH_ENABLE 0x4400 +#define CAR_mmGRPH_CONTROL 0x1a01 +#define CAR_mmDCP0_GRPH_CONTROL 0x1a01 +#define CAR_mmDCP1_GRPH_CONTROL 0x1c01 +#define CAR_mmDCP2_GRPH_CONTROL 0x1e01 +#define CAR_mmDCP3_GRPH_CONTROL 0x4001 +#define CAR_mmDCP4_GRPH_CONTROL 0x4201 +#define CAR_mmDCP5_GRPH_CONTROL 0x4401 +#define CAR_mmGRPH_LUT_10BIT_BYPASS 0x1a02 +#define CAR_mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 +#define CAR_mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 +#define CAR_mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 +#define CAR_mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 +#define CAR_mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 +#define CAR_mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 +#define CAR_mmGRPH_SWAP_CNTL 0x1a03 +#define CAR_mmDCP0_GRPH_SWAP_CNTL 0x1a03 +#define CAR_mmDCP1_GRPH_SWAP_CNTL 0x1c03 +#define CAR_mmDCP2_GRPH_SWAP_CNTL 0x1e03 +#define CAR_mmDCP3_GRPH_SWAP_CNTL 0x4003 +#define CAR_mmDCP4_GRPH_SWAP_CNTL 0x4203 +#define CAR_mmDCP5_GRPH_SWAP_CNTL 0x4403 +#define CAR_mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define CAR_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define CAR_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 +#define CAR_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 +#define CAR_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define CAR_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 +#define CAR_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 +#define CAR_mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define CAR_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define CAR_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 +#define CAR_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 +#define CAR_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define CAR_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 +#define CAR_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 +#define CAR_mmGRPH_PITCH 0x1a06 +#define CAR_mmDCP0_GRPH_PITCH 0x1a06 +#define CAR_mmDCP1_GRPH_PITCH 0x1c06 +#define CAR_mmDCP2_GRPH_PITCH 0x1e06 +#define CAR_mmDCP3_GRPH_PITCH 0x4006 +#define CAR_mmDCP4_GRPH_PITCH 0x4206 +#define CAR_mmDCP5_GRPH_PITCH 0x4406 +#define CAR_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define CAR_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define CAR_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 +#define CAR_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 +#define CAR_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define CAR_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 +#define CAR_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 +#define CAR_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define CAR_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define CAR_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 +#define CAR_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 +#define CAR_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define CAR_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 +#define CAR_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 +#define CAR_mmGRPH_SURFACE_OFFSET_X 0x1a09 +#define CAR_mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 +#define CAR_mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 +#define CAR_mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 +#define CAR_mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 +#define CAR_mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 +#define CAR_mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 +#define CAR_mmGRPH_SURFACE_OFFSET_Y 0x1a0a +#define CAR_mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a +#define CAR_mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a +#define CAR_mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a +#define CAR_mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a +#define CAR_mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a +#define CAR_mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a +#define CAR_mmGRPH_X_START 0x1a0b +#define CAR_mmDCP0_GRPH_X_START 0x1a0b +#define CAR_mmDCP1_GRPH_X_START 0x1c0b +#define CAR_mmDCP2_GRPH_X_START 0x1e0b +#define CAR_mmDCP3_GRPH_X_START 0x400b +#define CAR_mmDCP4_GRPH_X_START 0x420b +#define CAR_mmDCP5_GRPH_X_START 0x440b +#define CAR_mmGRPH_Y_START 0x1a0c +#define CAR_mmDCP0_GRPH_Y_START 0x1a0c +#define CAR_mmDCP1_GRPH_Y_START 0x1c0c +#define CAR_mmDCP2_GRPH_Y_START 0x1e0c +#define CAR_mmDCP3_GRPH_Y_START 0x400c +#define CAR_mmDCP4_GRPH_Y_START 0x420c +#define CAR_mmDCP5_GRPH_Y_START 0x440c +#define CAR_mmGRPH_X_END 0x1a0d +#define CAR_mmDCP0_GRPH_X_END 0x1a0d +#define CAR_mmDCP1_GRPH_X_END 0x1c0d +#define CAR_mmDCP2_GRPH_X_END 0x1e0d +#define CAR_mmDCP3_GRPH_X_END 0x400d +#define CAR_mmDCP4_GRPH_X_END 0x420d +#define CAR_mmDCP5_GRPH_X_END 0x440d +#define CAR_mmGRPH_Y_END 0x1a0e +#define CAR_mmDCP0_GRPH_Y_END 0x1a0e +#define CAR_mmDCP1_GRPH_Y_END 0x1c0e +#define CAR_mmDCP2_GRPH_Y_END 0x1e0e +#define CAR_mmDCP3_GRPH_Y_END 0x400e +#define CAR_mmDCP4_GRPH_Y_END 0x420e +#define CAR_mmDCP5_GRPH_Y_END 0x440e +#define CAR_mmINPUT_GAMMA_CONTROL 0x1a10 +#define CAR_mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 +#define CAR_mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 +#define CAR_mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 +#define CAR_mmDCP3_INPUT_GAMMA_CONTROL 0x4010 +#define CAR_mmDCP4_INPUT_GAMMA_CONTROL 0x4210 +#define CAR_mmDCP5_INPUT_GAMMA_CONTROL 0x4410 +#define CAR_mmGRPH_UPDATE 0x1a11 +#define CAR_mmDCP0_GRPH_UPDATE 0x1a11 +#define CAR_mmDCP1_GRPH_UPDATE 0x1c11 +#define CAR_mmDCP2_GRPH_UPDATE 0x1e11 +#define CAR_mmDCP3_GRPH_UPDATE 0x4011 +#define CAR_mmDCP4_GRPH_UPDATE 0x4211 +#define CAR_mmDCP5_GRPH_UPDATE 0x4411 +#define CAR_mmGRPH_FLIP_CONTROL 0x1a12 +#define CAR_mmDCP0_GRPH_FLIP_CONTROL 0x1a12 +#define CAR_mmDCP1_GRPH_FLIP_CONTROL 0x1c12 +#define CAR_mmDCP2_GRPH_FLIP_CONTROL 0x1e12 +#define CAR_mmDCP3_GRPH_FLIP_CONTROL 0x4012 +#define CAR_mmDCP4_GRPH_FLIP_CONTROL 0x4212 +#define CAR_mmDCP5_GRPH_FLIP_CONTROL 0x4412 +#define CAR_mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define CAR_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define CAR_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 +#define CAR_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 +#define CAR_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define CAR_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 +#define CAR_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 +#define CAR_mmGRPH_DFQ_CONTROL 0x1a14 +#define CAR_mmDCP0_GRPH_DFQ_CONTROL 0x1a14 +#define CAR_mmDCP1_GRPH_DFQ_CONTROL 0x1c14 +#define CAR_mmDCP2_GRPH_DFQ_CONTROL 0x1e14 +#define CAR_mmDCP3_GRPH_DFQ_CONTROL 0x4014 +#define CAR_mmDCP4_GRPH_DFQ_CONTROL 0x4214 +#define CAR_mmDCP5_GRPH_DFQ_CONTROL 0x4414 +#define CAR_mmGRPH_DFQ_STATUS 0x1a15 +#define CAR_mmDCP0_GRPH_DFQ_STATUS 0x1a15 +#define CAR_mmDCP1_GRPH_DFQ_STATUS 0x1c15 +#define CAR_mmDCP2_GRPH_DFQ_STATUS 0x1e15 +#define CAR_mmDCP3_GRPH_DFQ_STATUS 0x4015 +#define CAR_mmDCP4_GRPH_DFQ_STATUS 0x4215 +#define CAR_mmDCP5_GRPH_DFQ_STATUS 0x4415 +#define CAR_mmGRPH_INTERRUPT_STATUS 0x1a16 +#define CAR_mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 +#define CAR_mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 +#define CAR_mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 +#define CAR_mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 +#define CAR_mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 +#define CAR_mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 +#define CAR_mmGRPH_INTERRUPT_CONTROL 0x1a17 +#define CAR_mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 +#define CAR_mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 +#define CAR_mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 +#define CAR_mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 +#define CAR_mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 +#define CAR_mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 +#define CAR_mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define CAR_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define CAR_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 +#define CAR_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 +#define CAR_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define CAR_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 +#define CAR_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 +#define CAR_mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define CAR_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define CAR_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 +#define CAR_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 +#define CAR_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define CAR_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 +#define CAR_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 +#define CAR_mmGRPH_COMPRESS_PITCH 0x1a1a +#define CAR_mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a +#define CAR_mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a +#define CAR_mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a +#define CAR_mmDCP3_GRPH_COMPRESS_PITCH 0x401a +#define CAR_mmDCP4_GRPH_COMPRESS_PITCH 0x421a +#define CAR_mmDCP5_GRPH_COMPRESS_PITCH 0x441a +#define CAR_mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define CAR_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define CAR_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b +#define CAR_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b +#define CAR_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b +#define CAR_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b +#define CAR_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b +#define CAR_mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c +#define CAR_mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c +#define CAR_mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1c1c +#define CAR_mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1e1c +#define CAR_mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x401c +#define CAR_mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x421c +#define CAR_mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x441c +#define CAR_mmPRESCALE_GRPH_CONTROL 0x1a2d +#define CAR_mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d +#define CAR_mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d +#define CAR_mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d +#define CAR_mmDCP3_PRESCALE_GRPH_CONTROL 0x402d +#define CAR_mmDCP4_PRESCALE_GRPH_CONTROL 0x422d +#define CAR_mmDCP5_PRESCALE_GRPH_CONTROL 0x442d +#define CAR_mmPRESCALE_VALUES_GRPH_R 0x1a2e +#define CAR_mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e +#define CAR_mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e +#define CAR_mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e +#define CAR_mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e +#define CAR_mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e +#define CAR_mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e +#define CAR_mmPRESCALE_VALUES_GRPH_G 0x1a2f +#define CAR_mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f +#define CAR_mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f +#define CAR_mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f +#define CAR_mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f +#define CAR_mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f +#define CAR_mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f +#define CAR_mmPRESCALE_VALUES_GRPH_B 0x1a30 +#define CAR_mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 +#define CAR_mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 +#define CAR_mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 +#define CAR_mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 +#define CAR_mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 +#define CAR_mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 +#define CAR_mmINPUT_CSC_CONTROL 0x1a35 +#define CAR_mmDCP0_INPUT_CSC_CONTROL 0x1a35 +#define CAR_mmDCP1_INPUT_CSC_CONTROL 0x1c35 +#define CAR_mmDCP2_INPUT_CSC_CONTROL 0x1e35 +#define CAR_mmDCP3_INPUT_CSC_CONTROL 0x4035 +#define CAR_mmDCP4_INPUT_CSC_CONTROL 0x4235 +#define CAR_mmDCP5_INPUT_CSC_CONTROL 0x4435 +#define CAR_mmINPUT_CSC_C11_C12 0x1a36 +#define CAR_mmDCP0_INPUT_CSC_C11_C12 0x1a36 +#define CAR_mmDCP1_INPUT_CSC_C11_C12 0x1c36 +#define CAR_mmDCP2_INPUT_CSC_C11_C12 0x1e36 +#define CAR_mmDCP3_INPUT_CSC_C11_C12 0x4036 +#define CAR_mmDCP4_INPUT_CSC_C11_C12 0x4236 +#define CAR_mmDCP5_INPUT_CSC_C11_C12 0x4436 +#define CAR_mmINPUT_CSC_C13_C14 0x1a37 +#define CAR_mmDCP0_INPUT_CSC_C13_C14 0x1a37 +#define CAR_mmDCP1_INPUT_CSC_C13_C14 0x1c37 +#define CAR_mmDCP2_INPUT_CSC_C13_C14 0x1e37 +#define CAR_mmDCP3_INPUT_CSC_C13_C14 0x4037 +#define CAR_mmDCP4_INPUT_CSC_C13_C14 0x4237 +#define CAR_mmDCP5_INPUT_CSC_C13_C14 0x4437 +#define CAR_mmINPUT_CSC_C21_C22 0x1a38 +#define CAR_mmDCP0_INPUT_CSC_C21_C22 0x1a38 +#define CAR_mmDCP1_INPUT_CSC_C21_C22 0x1c38 +#define CAR_mmDCP2_INPUT_CSC_C21_C22 0x1e38 +#define CAR_mmDCP3_INPUT_CSC_C21_C22 0x4038 +#define CAR_mmDCP4_INPUT_CSC_C21_C22 0x4238 +#define CAR_mmDCP5_INPUT_CSC_C21_C22 0x4438 +#define CAR_mmINPUT_CSC_C23_C24 0x1a39 +#define CAR_mmDCP0_INPUT_CSC_C23_C24 0x1a39 +#define CAR_mmDCP1_INPUT_CSC_C23_C24 0x1c39 +#define CAR_mmDCP2_INPUT_CSC_C23_C24 0x1e39 +#define CAR_mmDCP3_INPUT_CSC_C23_C24 0x4039 +#define CAR_mmDCP4_INPUT_CSC_C23_C24 0x4239 +#define CAR_mmDCP5_INPUT_CSC_C23_C24 0x4439 +#define CAR_mmINPUT_CSC_C31_C32 0x1a3a +#define CAR_mmDCP0_INPUT_CSC_C31_C32 0x1a3a +#define CAR_mmDCP1_INPUT_CSC_C31_C32 0x1c3a +#define CAR_mmDCP2_INPUT_CSC_C31_C32 0x1e3a +#define CAR_mmDCP3_INPUT_CSC_C31_C32 0x403a +#define CAR_mmDCP4_INPUT_CSC_C31_C32 0x423a +#define CAR_mmDCP5_INPUT_CSC_C31_C32 0x443a +#define CAR_mmINPUT_CSC_C33_C34 0x1a3b +#define CAR_mmDCP0_INPUT_CSC_C33_C34 0x1a3b +#define CAR_mmDCP1_INPUT_CSC_C33_C34 0x1c3b +#define CAR_mmDCP2_INPUT_CSC_C33_C34 0x1e3b +#define CAR_mmDCP3_INPUT_CSC_C33_C34 0x403b +#define CAR_mmDCP4_INPUT_CSC_C33_C34 0x423b +#define CAR_mmDCP5_INPUT_CSC_C33_C34 0x443b +#define CAR_mmOUTPUT_CSC_CONTROL 0x1a3c +#define CAR_mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c +#define CAR_mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c +#define CAR_mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c +#define CAR_mmDCP3_OUTPUT_CSC_CONTROL 0x403c +#define CAR_mmDCP4_OUTPUT_CSC_CONTROL 0x423c +#define CAR_mmDCP5_OUTPUT_CSC_CONTROL 0x443c +#define CAR_mmOUTPUT_CSC_C11_C12 0x1a3d +#define CAR_mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d +#define CAR_mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d +#define CAR_mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d +#define CAR_mmDCP3_OUTPUT_CSC_C11_C12 0x403d +#define CAR_mmDCP4_OUTPUT_CSC_C11_C12 0x423d +#define CAR_mmDCP5_OUTPUT_CSC_C11_C12 0x443d +#define CAR_mmOUTPUT_CSC_C13_C14 0x1a3e +#define CAR_mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e +#define CAR_mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e +#define CAR_mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e +#define CAR_mmDCP3_OUTPUT_CSC_C13_C14 0x403e +#define CAR_mmDCP4_OUTPUT_CSC_C13_C14 0x423e +#define CAR_mmDCP5_OUTPUT_CSC_C13_C14 0x443e +#define CAR_mmOUTPUT_CSC_C21_C22 0x1a3f +#define CAR_mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f +#define CAR_mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f +#define CAR_mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f +#define CAR_mmDCP3_OUTPUT_CSC_C21_C22 0x403f +#define CAR_mmDCP4_OUTPUT_CSC_C21_C22 0x423f +#define CAR_mmDCP5_OUTPUT_CSC_C21_C22 0x443f +#define CAR_mmOUTPUT_CSC_C23_C24 0x1a40 +#define CAR_mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 +#define CAR_mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 +#define CAR_mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 +#define CAR_mmDCP3_OUTPUT_CSC_C23_C24 0x4040 +#define CAR_mmDCP4_OUTPUT_CSC_C23_C24 0x4240 +#define CAR_mmDCP5_OUTPUT_CSC_C23_C24 0x4440 +#define CAR_mmOUTPUT_CSC_C31_C32 0x1a41 +#define CAR_mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 +#define CAR_mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 +#define CAR_mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 +#define CAR_mmDCP3_OUTPUT_CSC_C31_C32 0x4041 +#define CAR_mmDCP4_OUTPUT_CSC_C31_C32 0x4241 +#define CAR_mmDCP5_OUTPUT_CSC_C31_C32 0x4441 +#define CAR_mmOUTPUT_CSC_C33_C34 0x1a42 +#define CAR_mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 +#define CAR_mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 +#define CAR_mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 +#define CAR_mmDCP3_OUTPUT_CSC_C33_C34 0x4042 +#define CAR_mmDCP4_OUTPUT_CSC_C33_C34 0x4242 +#define CAR_mmDCP5_OUTPUT_CSC_C33_C34 0x4442 +#define CAR_mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 +#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 +#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 +#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 +#define CAR_mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 +#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 +#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 +#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 +#define CAR_mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 +#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 +#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 +#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 +#define CAR_mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 +#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 +#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 +#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 +#define CAR_mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 +#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 +#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 +#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 +#define CAR_mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 +#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 +#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 +#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 +#define CAR_mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 +#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 +#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 +#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 +#define CAR_mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a +#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a +#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a +#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a +#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a +#define CAR_mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b +#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b +#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b +#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b +#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b +#define CAR_mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c +#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c +#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c +#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c +#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c +#define CAR_mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d +#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d +#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d +#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d +#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d +#define CAR_mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e +#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e +#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e +#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e +#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e +#define CAR_mmDENORM_CONTROL 0x1a50 +#define CAR_mmDCP0_DENORM_CONTROL 0x1a50 +#define CAR_mmDCP1_DENORM_CONTROL 0x1c50 +#define CAR_mmDCP2_DENORM_CONTROL 0x1e50 +#define CAR_mmDCP3_DENORM_CONTROL 0x4050 +#define CAR_mmDCP4_DENORM_CONTROL 0x4250 +#define CAR_mmDCP5_DENORM_CONTROL 0x4450 +#define CAR_mmOUT_ROUND_CONTROL 0x1a51 +#define CAR_mmDCP0_OUT_ROUND_CONTROL 0x1a51 +#define CAR_mmDCP1_OUT_ROUND_CONTROL 0x1c51 +#define CAR_mmDCP2_OUT_ROUND_CONTROL 0x1e51 +#define CAR_mmDCP3_OUT_ROUND_CONTROL 0x4051 +#define CAR_mmDCP4_OUT_ROUND_CONTROL 0x4251 +#define CAR_mmDCP5_OUT_ROUND_CONTROL 0x4451 +#define CAR_mmOUT_CLAMP_CONTROL_R_CR 0x1a52 +#define CAR_mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 +#define CAR_mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 +#define CAR_mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 +#define CAR_mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 +#define CAR_mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 +#define CAR_mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 +#define CAR_mmOUT_CLAMP_CONTROL_G_Y 0x1a9c +#define CAR_mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c +#define CAR_mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c +#define CAR_mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c +#define CAR_mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c +#define CAR_mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c +#define CAR_mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c +#define CAR_mmOUT_CLAMP_CONTROL_B_CB 0x1a9d +#define CAR_mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d +#define CAR_mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d +#define CAR_mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d +#define CAR_mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d +#define CAR_mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d +#define CAR_mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d +#define CAR_mmKEY_CONTROL 0x1a53 +#define CAR_mmDCP0_KEY_CONTROL 0x1a53 +#define CAR_mmDCP1_KEY_CONTROL 0x1c53 +#define CAR_mmDCP2_KEY_CONTROL 0x1e53 +#define CAR_mmDCP3_KEY_CONTROL 0x4053 +#define CAR_mmDCP4_KEY_CONTROL 0x4253 +#define CAR_mmDCP5_KEY_CONTROL 0x4453 +#define CAR_mmKEY_RANGE_ALPHA 0x1a54 +#define CAR_mmDCP0_KEY_RANGE_ALPHA 0x1a54 +#define CAR_mmDCP1_KEY_RANGE_ALPHA 0x1c54 +#define CAR_mmDCP2_KEY_RANGE_ALPHA 0x1e54 +#define CAR_mmDCP3_KEY_RANGE_ALPHA 0x4054 +#define CAR_mmDCP4_KEY_RANGE_ALPHA 0x4254 +#define CAR_mmDCP5_KEY_RANGE_ALPHA 0x4454 +#define CAR_mmKEY_RANGE_RED 0x1a55 +#define CAR_mmDCP0_KEY_RANGE_RED 0x1a55 +#define CAR_mmDCP1_KEY_RANGE_RED 0x1c55 +#define CAR_mmDCP2_KEY_RANGE_RED 0x1e55 +#define CAR_mmDCP3_KEY_RANGE_RED 0x4055 +#define CAR_mmDCP4_KEY_RANGE_RED 0x4255 +#define CAR_mmDCP5_KEY_RANGE_RED 0x4455 +#define CAR_mmKEY_RANGE_GREEN 0x1a56 +#define CAR_mmDCP0_KEY_RANGE_GREEN 0x1a56 +#define CAR_mmDCP1_KEY_RANGE_GREEN 0x1c56 +#define CAR_mmDCP2_KEY_RANGE_GREEN 0x1e56 +#define CAR_mmDCP3_KEY_RANGE_GREEN 0x4056 +#define CAR_mmDCP4_KEY_RANGE_GREEN 0x4256 +#define CAR_mmDCP5_KEY_RANGE_GREEN 0x4456 +#define CAR_mmKEY_RANGE_BLUE 0x1a57 +#define CAR_mmDCP0_KEY_RANGE_BLUE 0x1a57 +#define CAR_mmDCP1_KEY_RANGE_BLUE 0x1c57 +#define CAR_mmDCP2_KEY_RANGE_BLUE 0x1e57 +#define CAR_mmDCP3_KEY_RANGE_BLUE 0x4057 +#define CAR_mmDCP4_KEY_RANGE_BLUE 0x4257 +#define CAR_mmDCP5_KEY_RANGE_BLUE 0x4457 +#define CAR_mmDEGAMMA_CONTROL 0x1a58 +#define CAR_mmDCP0_DEGAMMA_CONTROL 0x1a58 +#define CAR_mmDCP1_DEGAMMA_CONTROL 0x1c58 +#define CAR_mmDCP2_DEGAMMA_CONTROL 0x1e58 +#define CAR_mmDCP3_DEGAMMA_CONTROL 0x4058 +#define CAR_mmDCP4_DEGAMMA_CONTROL 0x4258 +#define CAR_mmDCP5_DEGAMMA_CONTROL 0x4458 +#define CAR_mmGAMUT_REMAP_CONTROL 0x1a59 +#define CAR_mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 +#define CAR_mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 +#define CAR_mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 +#define CAR_mmDCP3_GAMUT_REMAP_CONTROL 0x4059 +#define CAR_mmDCP4_GAMUT_REMAP_CONTROL 0x4259 +#define CAR_mmDCP5_GAMUT_REMAP_CONTROL 0x4459 +#define CAR_mmGAMUT_REMAP_C11_C12 0x1a5a +#define CAR_mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a +#define CAR_mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a +#define CAR_mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a +#define CAR_mmDCP3_GAMUT_REMAP_C11_C12 0x405a +#define CAR_mmDCP4_GAMUT_REMAP_C11_C12 0x425a +#define CAR_mmDCP5_GAMUT_REMAP_C11_C12 0x445a +#define CAR_mmGAMUT_REMAP_C13_C14 0x1a5b +#define CAR_mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b +#define CAR_mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b +#define CAR_mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b +#define CAR_mmDCP3_GAMUT_REMAP_C13_C14 0x405b +#define CAR_mmDCP4_GAMUT_REMAP_C13_C14 0x425b +#define CAR_mmDCP5_GAMUT_REMAP_C13_C14 0x445b +#define CAR_mmGAMUT_REMAP_C21_C22 0x1a5c +#define CAR_mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c +#define CAR_mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c +#define CAR_mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c +#define CAR_mmDCP3_GAMUT_REMAP_C21_C22 0x405c +#define CAR_mmDCP4_GAMUT_REMAP_C21_C22 0x425c +#define CAR_mmDCP5_GAMUT_REMAP_C21_C22 0x445c +#define CAR_mmGAMUT_REMAP_C23_C24 0x1a5d +#define CAR_mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d +#define CAR_mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d +#define CAR_mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d +#define CAR_mmDCP3_GAMUT_REMAP_C23_C24 0x405d +#define CAR_mmDCP4_GAMUT_REMAP_C23_C24 0x425d +#define CAR_mmDCP5_GAMUT_REMAP_C23_C24 0x445d +#define CAR_mmGAMUT_REMAP_C31_C32 0x1a5e +#define CAR_mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e +#define CAR_mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e +#define CAR_mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e +#define CAR_mmDCP3_GAMUT_REMAP_C31_C32 0x405e +#define CAR_mmDCP4_GAMUT_REMAP_C31_C32 0x425e +#define CAR_mmDCP5_GAMUT_REMAP_C31_C32 0x445e +#define CAR_mmGAMUT_REMAP_C33_C34 0x1a5f +#define CAR_mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f +#define CAR_mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f +#define CAR_mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f +#define CAR_mmDCP3_GAMUT_REMAP_C33_C34 0x405f +#define CAR_mmDCP4_GAMUT_REMAP_C33_C34 0x425f +#define CAR_mmDCP5_GAMUT_REMAP_C33_C34 0x445f +#define CAR_mmDCP_SPATIAL_DITHER_CNTL 0x1a60 +#define CAR_mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 +#define CAR_mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 +#define CAR_mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 +#define CAR_mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define CAR_mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 +#define CAR_mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 +#define CAR_mmDCP_FP_CONVERTED_FIELD 0x1a65 +#define CAR_mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 +#define CAR_mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 +#define CAR_mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 +#define CAR_mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 +#define CAR_mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 +#define CAR_mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 +#define CAR_mmCUR_CONTROL 0x1a66 +#define CAR_mmDCP0_CUR_CONTROL 0x1a66 +#define CAR_mmDCP1_CUR_CONTROL 0x1c66 +#define CAR_mmDCP2_CUR_CONTROL 0x1e66 +#define CAR_mmDCP3_CUR_CONTROL 0x4066 +#define CAR_mmDCP4_CUR_CONTROL 0x4266 +#define CAR_mmDCP5_CUR_CONTROL 0x4466 +#define CAR_mmCUR_SURFACE_ADDRESS 0x1a67 +#define CAR_mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 +#define CAR_mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 +#define CAR_mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 +#define CAR_mmDCP3_CUR_SURFACE_ADDRESS 0x4067 +#define CAR_mmDCP4_CUR_SURFACE_ADDRESS 0x4267 +#define CAR_mmDCP5_CUR_SURFACE_ADDRESS 0x4467 +#define CAR_mmCUR_SIZE 0x1a68 +#define CAR_mmDCP0_CUR_SIZE 0x1a68 +#define CAR_mmDCP1_CUR_SIZE 0x1c68 +#define CAR_mmDCP2_CUR_SIZE 0x1e68 +#define CAR_mmDCP3_CUR_SIZE 0x4068 +#define CAR_mmDCP4_CUR_SIZE 0x4268 +#define CAR_mmDCP5_CUR_SIZE 0x4468 +#define CAR_mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define CAR_mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define CAR_mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 +#define CAR_mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 +#define CAR_mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define CAR_mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 +#define CAR_mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 +#define CAR_mmCUR_POSITION 0x1a6a +#define CAR_mmDCP0_CUR_POSITION 0x1a6a +#define CAR_mmDCP1_CUR_POSITION 0x1c6a +#define CAR_mmDCP2_CUR_POSITION 0x1e6a +#define CAR_mmDCP3_CUR_POSITION 0x406a +#define CAR_mmDCP4_CUR_POSITION 0x426a +#define CAR_mmDCP5_CUR_POSITION 0x446a +#define CAR_mmCUR_HOT_SPOT 0x1a6b +#define CAR_mmDCP0_CUR_HOT_SPOT 0x1a6b +#define CAR_mmDCP1_CUR_HOT_SPOT 0x1c6b +#define CAR_mmDCP2_CUR_HOT_SPOT 0x1e6b +#define CAR_mmDCP3_CUR_HOT_SPOT 0x406b +#define CAR_mmDCP4_CUR_HOT_SPOT 0x426b +#define CAR_mmDCP5_CUR_HOT_SPOT 0x446b +#define CAR_mmCUR_COLOR1 0x1a6c +#define CAR_mmDCP0_CUR_COLOR1 0x1a6c +#define CAR_mmDCP1_CUR_COLOR1 0x1c6c +#define CAR_mmDCP2_CUR_COLOR1 0x1e6c +#define CAR_mmDCP3_CUR_COLOR1 0x406c +#define CAR_mmDCP4_CUR_COLOR1 0x426c +#define CAR_mmDCP5_CUR_COLOR1 0x446c +#define CAR_mmCUR_COLOR2 0x1a6d +#define CAR_mmDCP0_CUR_COLOR2 0x1a6d +#define CAR_mmDCP1_CUR_COLOR2 0x1c6d +#define CAR_mmDCP2_CUR_COLOR2 0x1e6d +#define CAR_mmDCP3_CUR_COLOR2 0x406d +#define CAR_mmDCP4_CUR_COLOR2 0x426d +#define CAR_mmDCP5_CUR_COLOR2 0x446d +#define CAR_mmCUR_UPDATE 0x1a6e +#define CAR_mmDCP0_CUR_UPDATE 0x1a6e +#define CAR_mmDCP1_CUR_UPDATE 0x1c6e +#define CAR_mmDCP2_CUR_UPDATE 0x1e6e +#define CAR_mmDCP3_CUR_UPDATE 0x406e +#define CAR_mmDCP4_CUR_UPDATE 0x426e +#define CAR_mmDCP5_CUR_UPDATE 0x446e +#define CAR_mmCUR_REQUEST_FILTER_CNTL 0x1a99 +#define CAR_mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 +#define CAR_mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 +#define CAR_mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 +#define CAR_mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 +#define CAR_mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 +#define CAR_mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 +#define CAR_mmCUR_STEREO_CONTROL 0x1a9a +#define CAR_mmDCP0_CUR_STEREO_CONTROL 0x1a9a +#define CAR_mmDCP1_CUR_STEREO_CONTROL 0x1c9a +#define CAR_mmDCP2_CUR_STEREO_CONTROL 0x1e9a +#define CAR_mmDCP3_CUR_STEREO_CONTROL 0x409a +#define CAR_mmDCP4_CUR_STEREO_CONTROL 0x429a +#define CAR_mmDCP5_CUR_STEREO_CONTROL 0x449a +#define CAR_mmDC_LUT_RW_MODE 0x1a78 +#define CAR_mmDCP0_DC_LUT_RW_MODE 0x1a78 +#define CAR_mmDCP1_DC_LUT_RW_MODE 0x1c78 +#define CAR_mmDCP2_DC_LUT_RW_MODE 0x1e78 +#define CAR_mmDCP3_DC_LUT_RW_MODE 0x4078 +#define CAR_mmDCP4_DC_LUT_RW_MODE 0x4278 +#define CAR_mmDCP5_DC_LUT_RW_MODE 0x4478 +#define CAR_mmDC_LUT_RW_INDEX 0x1a79 +#define CAR_mmDCP0_DC_LUT_RW_INDEX 0x1a79 +#define CAR_mmDCP1_DC_LUT_RW_INDEX 0x1c79 +#define CAR_mmDCP2_DC_LUT_RW_INDEX 0x1e79 +#define CAR_mmDCP3_DC_LUT_RW_INDEX 0x4079 +#define CAR_mmDCP4_DC_LUT_RW_INDEX 0x4279 +#define CAR_mmDCP5_DC_LUT_RW_INDEX 0x4479 +#define CAR_mmDC_LUT_SEQ_COLOR 0x1a7a +#define CAR_mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a +#define CAR_mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a +#define CAR_mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a +#define CAR_mmDCP3_DC_LUT_SEQ_COLOR 0x407a +#define CAR_mmDCP4_DC_LUT_SEQ_COLOR 0x427a +#define CAR_mmDCP5_DC_LUT_SEQ_COLOR 0x447a +#define CAR_mmDC_LUT_PWL_DATA 0x1a7b +#define CAR_mmDCP0_DC_LUT_PWL_DATA 0x1a7b +#define CAR_mmDCP1_DC_LUT_PWL_DATA 0x1c7b +#define CAR_mmDCP2_DC_LUT_PWL_DATA 0x1e7b +#define CAR_mmDCP3_DC_LUT_PWL_DATA 0x407b +#define CAR_mmDCP4_DC_LUT_PWL_DATA 0x427b +#define CAR_mmDCP5_DC_LUT_PWL_DATA 0x447b +#define CAR_mmDC_LUT_30_COLOR 0x1a7c +#define CAR_mmDCP0_DC_LUT_30_COLOR 0x1a7c +#define CAR_mmDCP1_DC_LUT_30_COLOR 0x1c7c +#define CAR_mmDCP2_DC_LUT_30_COLOR 0x1e7c +#define CAR_mmDCP3_DC_LUT_30_COLOR 0x407c +#define CAR_mmDCP4_DC_LUT_30_COLOR 0x427c +#define CAR_mmDCP5_DC_LUT_30_COLOR 0x447c +#define CAR_mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define CAR_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define CAR_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d +#define CAR_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d +#define CAR_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d +#define CAR_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d +#define CAR_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d +#define CAR_mmDC_LUT_WRITE_EN_MASK 0x1a7e +#define CAR_mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e +#define CAR_mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e +#define CAR_mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e +#define CAR_mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e +#define CAR_mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e +#define CAR_mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e +#define CAR_mmDC_LUT_AUTOFILL 0x1a7f +#define CAR_mmDCP0_DC_LUT_AUTOFILL 0x1a7f +#define CAR_mmDCP1_DC_LUT_AUTOFILL 0x1c7f +#define CAR_mmDCP2_DC_LUT_AUTOFILL 0x1e7f +#define CAR_mmDCP3_DC_LUT_AUTOFILL 0x407f +#define CAR_mmDCP4_DC_LUT_AUTOFILL 0x427f +#define CAR_mmDCP5_DC_LUT_AUTOFILL 0x447f +#define CAR_mmDC_LUT_CONTROL 0x1a80 +#define CAR_mmDCP0_DC_LUT_CONTROL 0x1a80 +#define CAR_mmDCP1_DC_LUT_CONTROL 0x1c80 +#define CAR_mmDCP2_DC_LUT_CONTROL 0x1e80 +#define CAR_mmDCP3_DC_LUT_CONTROL 0x4080 +#define CAR_mmDCP4_DC_LUT_CONTROL 0x4280 +#define CAR_mmDCP5_DC_LUT_CONTROL 0x4480 +#define CAR_mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define CAR_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define CAR_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 +#define CAR_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 +#define CAR_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define CAR_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 +#define CAR_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 +#define CAR_mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define CAR_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define CAR_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 +#define CAR_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 +#define CAR_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define CAR_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 +#define CAR_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 +#define CAR_mmDC_LUT_BLACK_OFFSET_RED 0x1a83 +#define CAR_mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 +#define CAR_mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 +#define CAR_mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 +#define CAR_mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define CAR_mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 +#define CAR_mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 +#define CAR_mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define CAR_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define CAR_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 +#define CAR_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 +#define CAR_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define CAR_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 +#define CAR_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 +#define CAR_mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define CAR_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define CAR_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 +#define CAR_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 +#define CAR_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define CAR_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 +#define CAR_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 +#define CAR_mmDC_LUT_WHITE_OFFSET_RED 0x1a86 +#define CAR_mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 +#define CAR_mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 +#define CAR_mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 +#define CAR_mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define CAR_mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 +#define CAR_mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 +#define CAR_mmDCP_CRC_CONTROL 0x1a87 +#define CAR_mmDCP0_DCP_CRC_CONTROL 0x1a87 +#define CAR_mmDCP1_DCP_CRC_CONTROL 0x1c87 +#define CAR_mmDCP2_DCP_CRC_CONTROL 0x1e87 +#define CAR_mmDCP3_DCP_CRC_CONTROL 0x4087 +#define CAR_mmDCP4_DCP_CRC_CONTROL 0x4287 +#define CAR_mmDCP5_DCP_CRC_CONTROL 0x4487 +#define CAR_mmDCP_CRC_MASK 0x1a88 +#define CAR_mmDCP0_DCP_CRC_MASK 0x1a88 +#define CAR_mmDCP1_DCP_CRC_MASK 0x1c88 +#define CAR_mmDCP2_DCP_CRC_MASK 0x1e88 +#define CAR_mmDCP3_DCP_CRC_MASK 0x4088 +#define CAR_mmDCP4_DCP_CRC_MASK 0x4288 +#define CAR_mmDCP5_DCP_CRC_MASK 0x4488 +#define CAR_mmDCP_CRC_CURRENT 0x1a89 +#define CAR_mmDCP0_DCP_CRC_CURRENT 0x1a89 +#define CAR_mmDCP1_DCP_CRC_CURRENT 0x1c89 +#define CAR_mmDCP2_DCP_CRC_CURRENT 0x1e89 +#define CAR_mmDCP3_DCP_CRC_CURRENT 0x4089 +#define CAR_mmDCP4_DCP_CRC_CURRENT 0x4289 +#define CAR_mmDCP5_DCP_CRC_CURRENT 0x4489 +#define CAR_mmDVMM_PTE_CONTROL 0x1a8a +#define CAR_mmDCP0_DVMM_PTE_CONTROL 0x1a8a +#define CAR_mmDCP1_DVMM_PTE_CONTROL 0x1c8a +#define CAR_mmDCP2_DVMM_PTE_CONTROL 0x1e8a +#define CAR_mmDCP3_DVMM_PTE_CONTROL 0x408a +#define CAR_mmDCP4_DVMM_PTE_CONTROL 0x428a +#define CAR_mmDCP5_DVMM_PTE_CONTROL 0x448a +#define CAR_mmDCP_CRC_LAST 0x1a8b +#define CAR_mmDCP0_DCP_CRC_LAST 0x1a8b +#define CAR_mmDCP1_DCP_CRC_LAST 0x1c8b +#define CAR_mmDCP2_DCP_CRC_LAST 0x1e8b +#define CAR_mmDCP3_DCP_CRC_LAST 0x408b +#define CAR_mmDCP4_DCP_CRC_LAST 0x428b +#define CAR_mmDCP5_DCP_CRC_LAST 0x448b +#define CAR_mmDVMM_PTE_ARB_CONTROL 0x1a8c +#define CAR_mmDCP0_DVMM_PTE_ARB_CONTROL 0x1a8c +#define CAR_mmDCP1_DVMM_PTE_ARB_CONTROL 0x1c8c +#define CAR_mmDCP2_DVMM_PTE_ARB_CONTROL 0x1e8c +#define CAR_mmDCP3_DVMM_PTE_ARB_CONTROL 0x408c +#define CAR_mmDCP4_DVMM_PTE_ARB_CONTROL 0x428c +#define CAR_mmDCP5_DVMM_PTE_ARB_CONTROL 0x448c +#define CAR_mmDCP_DEBUG 0x1a8d +#define CAR_mmDCP0_DCP_DEBUG 0x1a8d +#define CAR_mmDCP1_DCP_DEBUG 0x1c8d +#define CAR_mmDCP2_DCP_DEBUG 0x1e8d +#define CAR_mmDCP3_DCP_DEBUG 0x408d +#define CAR_mmDCP4_DCP_DEBUG 0x428d +#define CAR_mmDCP5_DCP_DEBUG 0x448d +#define CAR_mmGRPH_FLIP_RATE_CNTL 0x1a8e +#define CAR_mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e +#define CAR_mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e +#define CAR_mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e +#define CAR_mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e +#define CAR_mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e +#define CAR_mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e +#define CAR_mmDCP_GSL_CONTROL 0x1a90 +#define CAR_mmDCP0_DCP_GSL_CONTROL 0x1a90 +#define CAR_mmDCP1_DCP_GSL_CONTROL 0x1c90 +#define CAR_mmDCP2_DCP_GSL_CONTROL 0x1e90 +#define CAR_mmDCP3_DCP_GSL_CONTROL 0x4090 +#define CAR_mmDCP4_DCP_GSL_CONTROL 0x4290 +#define CAR_mmDCP5_DCP_GSL_CONTROL 0x4490 +#define CAR_mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define CAR_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define CAR_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 +#define CAR_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 +#define CAR_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define CAR_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 +#define CAR_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 +#define CAR_mmDCP_DEBUG_SG 0x1a92 +#define CAR_mmDCP0_DCP_DEBUG_SG 0x1a92 +#define CAR_mmDCP1_DCP_DEBUG_SG 0x1c92 +#define CAR_mmDCP2_DCP_DEBUG_SG 0x1e92 +#define CAR_mmDCP3_DCP_DEBUG_SG 0x4092 +#define CAR_mmDCP4_DCP_DEBUG_SG 0x4292 +#define CAR_mmDCP5_DCP_DEBUG_SG 0x4492 +#define CAR_mmDCP_DEBUG_SG2 0x1a94 +#define CAR_mmDCP0_DCP_DEBUG_SG2 0x1a94 +#define CAR_mmDCP1_DCP_DEBUG_SG2 0x1c94 +#define CAR_mmDCP2_DCP_DEBUG_SG2 0x1e94 +#define CAR_mmDCP3_DCP_DEBUG_SG2 0x4094 +#define CAR_mmDCP4_DCP_DEBUG_SG2 0x4294 +#define CAR_mmDCP5_DCP_DEBUG_SG2 0x4494 +#define CAR_mmDCP_DVMM_DEBUG 0x1a93 +#define CAR_mmDCP0_DCP_DVMM_DEBUG 0x1a93 +#define CAR_mmDCP1_DCP_DVMM_DEBUG 0x1c93 +#define CAR_mmDCP2_DCP_DVMM_DEBUG 0x1e93 +#define CAR_mmDCP3_DCP_DVMM_DEBUG 0x4093 +#define CAR_mmDCP4_DCP_DVMM_DEBUG 0x4293 +#define CAR_mmDCP5_DCP_DVMM_DEBUG 0x4493 +#define CAR_mmDCP_TEST_DEBUG_INDEX 0x1a95 +#define CAR_mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 +#define CAR_mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 +#define CAR_mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 +#define CAR_mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 +#define CAR_mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 +#define CAR_mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 +#define CAR_mmDCP_TEST_DEBUG_DATA 0x1a96 +#define CAR_mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 +#define CAR_mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 +#define CAR_mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 +#define CAR_mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 +#define CAR_mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 +#define CAR_mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 +#define CAR_mmGRPH_STEREOSYNC_FLIP 0x1a97 +#define CAR_mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 +#define CAR_mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 +#define CAR_mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 +#define CAR_mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 +#define CAR_mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 +#define CAR_mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 +#define CAR_mmDCP_DEBUG2 0x1a98 +#define CAR_mmDCP0_DCP_DEBUG2 0x1a98 +#define CAR_mmDCP1_DCP_DEBUG2 0x1c98 +#define CAR_mmDCP2_DCP_DEBUG2 0x1e98 +#define CAR_mmDCP3_DCP_DEBUG2 0x4098 +#define CAR_mmDCP4_DCP_DEBUG2 0x4298 +#define CAR_mmDCP5_DCP_DEBUG2 0x4498 +#define CAR_mmHW_ROTATION 0x1a9e +#define CAR_mmDCP0_HW_ROTATION 0x1a9e +#define CAR_mmDCP1_HW_ROTATION 0x1c9e +#define CAR_mmDCP2_HW_ROTATION 0x1e9e +#define CAR_mmDCP3_HW_ROTATION 0x409e +#define CAR_mmDCP4_HW_ROTATION 0x429e +#define CAR_mmDCP5_HW_ROTATION 0x449e +#define CAR_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define CAR_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define CAR_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f +#define CAR_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f +#define CAR_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f +#define CAR_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f +#define CAR_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f +#define CAR_mmREGAMMA_CONTROL 0x1aa0 +#define CAR_mmDCP0_REGAMMA_CONTROL 0x1aa0 +#define CAR_mmDCP1_REGAMMA_CONTROL 0x1ca0 +#define CAR_mmDCP2_REGAMMA_CONTROL 0x1ea0 +#define CAR_mmDCP3_REGAMMA_CONTROL 0x40a0 +#define CAR_mmDCP4_REGAMMA_CONTROL 0x42a0 +#define CAR_mmDCP5_REGAMMA_CONTROL 0x44a0 +#define CAR_mmREGAMMA_LUT_INDEX 0x1aa1 +#define CAR_mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 +#define CAR_mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 +#define CAR_mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 +#define CAR_mmDCP3_REGAMMA_LUT_INDEX 0x40a1 +#define CAR_mmDCP4_REGAMMA_LUT_INDEX 0x42a1 +#define CAR_mmDCP5_REGAMMA_LUT_INDEX 0x44a1 +#define CAR_mmREGAMMA_LUT_DATA 0x1aa2 +#define CAR_mmDCP0_REGAMMA_LUT_DATA 0x1aa2 +#define CAR_mmDCP1_REGAMMA_LUT_DATA 0x1ca2 +#define CAR_mmDCP2_REGAMMA_LUT_DATA 0x1ea2 +#define CAR_mmDCP3_REGAMMA_LUT_DATA 0x40a2 +#define CAR_mmDCP4_REGAMMA_LUT_DATA 0x42a2 +#define CAR_mmDCP5_REGAMMA_LUT_DATA 0x44a2 +#define CAR_mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define CAR_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define CAR_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 +#define CAR_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 +#define CAR_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 +#define CAR_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 +#define CAR_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 +#define CAR_mmREGAMMA_CNTLA_START_CNTL 0x1aa4 +#define CAR_mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 +#define CAR_mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 +#define CAR_mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 +#define CAR_mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 +#define CAR_mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 +#define CAR_mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 +#define CAR_mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define CAR_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define CAR_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 +#define CAR_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 +#define CAR_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 +#define CAR_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 +#define CAR_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 +#define CAR_mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define CAR_mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define CAR_mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 +#define CAR_mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 +#define CAR_mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 +#define CAR_mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 +#define CAR_mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 +#define CAR_mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define CAR_mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define CAR_mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 +#define CAR_mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 +#define CAR_mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 +#define CAR_mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 +#define CAR_mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 +#define CAR_mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 +#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 +#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 +#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 +#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 +#define CAR_mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 +#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 +#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 +#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 +#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 +#define CAR_mmREGAMMA_CNTLA_REGION_4_5 0x1aaa +#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa +#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa +#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa +#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa +#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa +#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa +#define CAR_mmREGAMMA_CNTLA_REGION_6_7 0x1aab +#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab +#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab +#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab +#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab +#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab +#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab +#define CAR_mmREGAMMA_CNTLA_REGION_8_9 0x1aac +#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac +#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac +#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac +#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac +#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac +#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac +#define CAR_mmREGAMMA_CNTLA_REGION_10_11 0x1aad +#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad +#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad +#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead +#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad +#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad +#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad +#define CAR_mmREGAMMA_CNTLA_REGION_12_13 0x1aae +#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae +#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae +#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae +#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae +#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae +#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae +#define CAR_mmREGAMMA_CNTLA_REGION_14_15 0x1aaf +#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf +#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf +#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf +#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af +#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af +#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af +#define CAR_mmREGAMMA_CNTLB_START_CNTL 0x1ab0 +#define CAR_mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 +#define CAR_mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 +#define CAR_mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 +#define CAR_mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 +#define CAR_mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 +#define CAR_mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 +#define CAR_mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define CAR_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define CAR_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 +#define CAR_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 +#define CAR_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 +#define CAR_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 +#define CAR_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 +#define CAR_mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define CAR_mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define CAR_mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 +#define CAR_mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 +#define CAR_mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 +#define CAR_mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 +#define CAR_mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 +#define CAR_mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define CAR_mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define CAR_mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 +#define CAR_mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 +#define CAR_mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 +#define CAR_mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 +#define CAR_mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 +#define CAR_mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 +#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 +#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 +#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 +#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 +#define CAR_mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 +#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 +#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 +#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 +#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 +#define CAR_mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 +#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 +#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 +#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 +#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 +#define CAR_mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 +#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 +#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 +#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 +#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 +#define CAR_mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 +#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 +#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 +#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 +#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 +#define CAR_mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 +#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 +#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 +#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 +#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 +#define CAR_mmREGAMMA_CNTLB_REGION_12_13 0x1aba +#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba +#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba +#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba +#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba +#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba +#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba +#define CAR_mmREGAMMA_CNTLB_REGION_14_15 0x1abb +#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb +#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb +#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb +#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb +#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb +#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb +#define CAR_mmALPHA_CONTROL 0x1abc +#define CAR_mmDCP0_ALPHA_CONTROL 0x1abc +#define CAR_mmDCP1_ALPHA_CONTROL 0x1cbc +#define CAR_mmDCP2_ALPHA_CONTROL 0x1ebc +#define CAR_mmDCP3_ALPHA_CONTROL 0x40bc +#define CAR_mmDCP4_ALPHA_CONTROL 0x42bc +#define CAR_mmDCP5_ALPHA_CONTROL 0x44bc +#define CAR_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define CAR_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define CAR_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd +#define CAR_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd +#define CAR_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd +#define CAR_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd +#define CAR_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd +#define CAR_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define CAR_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define CAR_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe +#define CAR_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe +#define CAR_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be +#define CAR_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be +#define CAR_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be +#define CAR_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define CAR_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define CAR_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf +#define CAR_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf +#define CAR_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf +#define CAR_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf +#define CAR_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf +#define CAR_mmGRPH_SURFACE_COUNTER_CONTROL 0x1a0f +#define CAR_mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x1a0f +#define CAR_mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x1c0f +#define CAR_mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x1e0f +#define CAR_mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x400f +#define CAR_mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x420f +#define CAR_mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x440f +#define CAR_mmGRPH_SURFACE_COUNTER_OUTPUT 0x1a1d +#define CAR_mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x1a1d +#define CAR_mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x1c1d +#define CAR_mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x1e1d +#define CAR_mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x401d +#define CAR_mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x421d +#define CAR_mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x441d +#define CAR_mmDIG_FE_CNTL 0x4a00 +#define CAR_mmDIG0_DIG_FE_CNTL 0x4a00 +#define CAR_mmDIG1_DIG_FE_CNTL 0x4b00 +#define CAR_mmDIG2_DIG_FE_CNTL 0x4c00 +#define CAR_mmDIG3_DIG_FE_CNTL 0x4d00 +#define CAR_mmDIG4_DIG_FE_CNTL 0x4e00 +#define CAR_mmDIG5_DIG_FE_CNTL 0x4f00 +#define CAR_mmDIG6_DIG_FE_CNTL 0x5400 +#define CAR_mmDIG7_DIG_FE_CNTL 0x5600 +#define CAR_mmDIG8_DIG_FE_CNTL 0x5700 +#define CAR_mmDIG_OUTPUT_CRC_CNTL 0x4a01 +#define CAR_mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 +#define CAR_mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 +#define CAR_mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 +#define CAR_mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 +#define CAR_mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 +#define CAR_mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 +#define CAR_mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 +#define CAR_mmDIG7_DIG_OUTPUT_CRC_CNTL 0x5601 +#define CAR_mmDIG8_DIG_OUTPUT_CRC_CNTL 0x5701 +#define CAR_mmDIG_OUTPUT_CRC_RESULT 0x4a02 +#define CAR_mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 +#define CAR_mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 +#define CAR_mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 +#define CAR_mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 +#define CAR_mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 +#define CAR_mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 +#define CAR_mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 +#define CAR_mmDIG7_DIG_OUTPUT_CRC_RESULT 0x5602 +#define CAR_mmDIG8_DIG_OUTPUT_CRC_RESULT 0x5702 +#define CAR_mmDIG_CLOCK_PATTERN 0x4a03 +#define CAR_mmDIG0_DIG_CLOCK_PATTERN 0x4a03 +#define CAR_mmDIG1_DIG_CLOCK_PATTERN 0x4b03 +#define CAR_mmDIG2_DIG_CLOCK_PATTERN 0x4c03 +#define CAR_mmDIG3_DIG_CLOCK_PATTERN 0x4d03 +#define CAR_mmDIG4_DIG_CLOCK_PATTERN 0x4e03 +#define CAR_mmDIG5_DIG_CLOCK_PATTERN 0x4f03 +#define CAR_mmDIG6_DIG_CLOCK_PATTERN 0x5403 +#define CAR_mmDIG7_DIG_CLOCK_PATTERN 0x5603 +#define CAR_mmDIG8_DIG_CLOCK_PATTERN 0x5703 +#define CAR_mmDIG_TEST_PATTERN 0x4a04 +#define CAR_mmDIG0_DIG_TEST_PATTERN 0x4a04 +#define CAR_mmDIG1_DIG_TEST_PATTERN 0x4b04 +#define CAR_mmDIG2_DIG_TEST_PATTERN 0x4c04 +#define CAR_mmDIG3_DIG_TEST_PATTERN 0x4d04 +#define CAR_mmDIG4_DIG_TEST_PATTERN 0x4e04 +#define CAR_mmDIG5_DIG_TEST_PATTERN 0x4f04 +#define CAR_mmDIG6_DIG_TEST_PATTERN 0x5404 +#define CAR_mmDIG7_DIG_TEST_PATTERN 0x5604 +#define CAR_mmDIG8_DIG_TEST_PATTERN 0x5704 +#define CAR_mmDIG_RANDOM_PATTERN_SEED 0x4a05 +#define CAR_mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 +#define CAR_mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 +#define CAR_mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 +#define CAR_mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 +#define CAR_mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 +#define CAR_mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 +#define CAR_mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 +#define CAR_mmDIG7_DIG_RANDOM_PATTERN_SEED 0x5605 +#define CAR_mmDIG8_DIG_RANDOM_PATTERN_SEED 0x5705 +#define CAR_mmDIG_FIFO_STATUS 0x4a06 +#define CAR_mmDIG0_DIG_FIFO_STATUS 0x4a06 +#define CAR_mmDIG1_DIG_FIFO_STATUS 0x4b06 +#define CAR_mmDIG2_DIG_FIFO_STATUS 0x4c06 +#define CAR_mmDIG3_DIG_FIFO_STATUS 0x4d06 +#define CAR_mmDIG4_DIG_FIFO_STATUS 0x4e06 +#define CAR_mmDIG5_DIG_FIFO_STATUS 0x4f06 +#define CAR_mmDIG6_DIG_FIFO_STATUS 0x5406 +#define CAR_mmDIG7_DIG_FIFO_STATUS 0x5606 +#define CAR_mmDIG8_DIG_FIFO_STATUS 0x5706 +#define CAR_mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define CAR_mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define CAR_mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 +#define CAR_mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 +#define CAR_mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 +#define CAR_mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 +#define CAR_mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 +#define CAR_mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 +#define CAR_mmDIG7_DIG_DISPCLK_SWITCH_CNTL 0x5607 +#define CAR_mmDIG8_DIG_DISPCLK_SWITCH_CNTL 0x5707 +#define CAR_mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define CAR_mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define CAR_mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 +#define CAR_mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 +#define CAR_mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 +#define CAR_mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 +#define CAR_mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 +#define CAR_mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 +#define CAR_mmDIG7_DIG_DISPCLK_SWITCH_STATUS 0x5608 +#define CAR_mmDIG8_DIG_DISPCLK_SWITCH_STATUS 0x5708 +#define CAR_mmHDMI_CONTROL 0x4a09 +#define CAR_mmDIG0_HDMI_CONTROL 0x4a09 +#define CAR_mmDIG1_HDMI_CONTROL 0x4b09 +#define CAR_mmDIG2_HDMI_CONTROL 0x4c09 +#define CAR_mmDIG3_HDMI_CONTROL 0x4d09 +#define CAR_mmDIG4_HDMI_CONTROL 0x4e09 +#define CAR_mmDIG5_HDMI_CONTROL 0x4f09 +#define CAR_mmDIG6_HDMI_CONTROL 0x5409 +#define CAR_mmDIG7_HDMI_CONTROL 0x5609 +#define CAR_mmDIG8_HDMI_CONTROL 0x5709 +#define CAR_mmHDMI_STATUS 0x4a0a +#define CAR_mmDIG0_HDMI_STATUS 0x4a0a +#define CAR_mmDIG1_HDMI_STATUS 0x4b0a +#define CAR_mmDIG2_HDMI_STATUS 0x4c0a +#define CAR_mmDIG3_HDMI_STATUS 0x4d0a +#define CAR_mmDIG4_HDMI_STATUS 0x4e0a +#define CAR_mmDIG5_HDMI_STATUS 0x4f0a +#define CAR_mmDIG6_HDMI_STATUS 0x540a +#define CAR_mmDIG7_HDMI_STATUS 0x560a +#define CAR_mmDIG8_HDMI_STATUS 0x570a +#define CAR_mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define CAR_mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define CAR_mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b +#define CAR_mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b +#define CAR_mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b +#define CAR_mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b +#define CAR_mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b +#define CAR_mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b +#define CAR_mmDIG7_HDMI_AUDIO_PACKET_CONTROL 0x560b +#define CAR_mmDIG8_HDMI_AUDIO_PACKET_CONTROL 0x570b +#define CAR_mmHDMI_ACR_PACKET_CONTROL 0x4a0c +#define CAR_mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c +#define CAR_mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c +#define CAR_mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c +#define CAR_mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c +#define CAR_mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c +#define CAR_mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c +#define CAR_mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c +#define CAR_mmDIG7_HDMI_ACR_PACKET_CONTROL 0x560c +#define CAR_mmDIG8_HDMI_ACR_PACKET_CONTROL 0x570c +#define CAR_mmHDMI_VBI_PACKET_CONTROL 0x4a0d +#define CAR_mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d +#define CAR_mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d +#define CAR_mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d +#define CAR_mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d +#define CAR_mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d +#define CAR_mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d +#define CAR_mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d +#define CAR_mmDIG7_HDMI_VBI_PACKET_CONTROL 0x560d +#define CAR_mmDIG8_HDMI_VBI_PACKET_CONTROL 0x570d +#define CAR_mmHDMI_INFOFRAME_CONTROL0 0x4a0e +#define CAR_mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e +#define CAR_mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e +#define CAR_mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e +#define CAR_mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e +#define CAR_mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e +#define CAR_mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e +#define CAR_mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e +#define CAR_mmDIG7_HDMI_INFOFRAME_CONTROL0 0x560e +#define CAR_mmDIG8_HDMI_INFOFRAME_CONTROL0 0x570e +#define CAR_mmHDMI_INFOFRAME_CONTROL1 0x4a0f +#define CAR_mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f +#define CAR_mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f +#define CAR_mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f +#define CAR_mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f +#define CAR_mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f +#define CAR_mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f +#define CAR_mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f +#define CAR_mmDIG7_HDMI_INFOFRAME_CONTROL1 0x560f +#define CAR_mmDIG8_HDMI_INFOFRAME_CONTROL1 0x570f +#define CAR_mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define CAR_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define CAR_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 +#define CAR_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 +#define CAR_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 +#define CAR_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 +#define CAR_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 +#define CAR_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 +#define CAR_mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 0x5610 +#define CAR_mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 0x5710 +#define CAR_mmAFMT_INTERRUPT_STATUS 0x4a11 +#define CAR_mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 +#define CAR_mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 +#define CAR_mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 +#define CAR_mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 +#define CAR_mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 +#define CAR_mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 +#define CAR_mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 +#define CAR_mmDIG7_AFMT_INTERRUPT_STATUS 0x5611 +#define CAR_mmDIG8_AFMT_INTERRUPT_STATUS 0x5711 +#define CAR_mmHDMI_GC 0x4a13 +#define CAR_mmDIG0_HDMI_GC 0x4a13 +#define CAR_mmDIG1_HDMI_GC 0x4b13 +#define CAR_mmDIG2_HDMI_GC 0x4c13 +#define CAR_mmDIG3_HDMI_GC 0x4d13 +#define CAR_mmDIG4_HDMI_GC 0x4e13 +#define CAR_mmDIG5_HDMI_GC 0x4f13 +#define CAR_mmDIG6_HDMI_GC 0x5413 +#define CAR_mmDIG7_HDMI_GC 0x5613 +#define CAR_mmDIG8_HDMI_GC 0x5713 +#define CAR_mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define CAR_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define CAR_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 +#define CAR_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 +#define CAR_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 +#define CAR_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 +#define CAR_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 +#define CAR_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 +#define CAR_mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 0x5614 +#define CAR_mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 0x5714 +#define CAR_mmAFMT_ISRC1_0 0x4a15 +#define CAR_mmDIG0_AFMT_ISRC1_0 0x4a15 +#define CAR_mmDIG1_AFMT_ISRC1_0 0x4b15 +#define CAR_mmDIG2_AFMT_ISRC1_0 0x4c15 +#define CAR_mmDIG3_AFMT_ISRC1_0 0x4d15 +#define CAR_mmDIG4_AFMT_ISRC1_0 0x4e15 +#define CAR_mmDIG5_AFMT_ISRC1_0 0x4f15 +#define CAR_mmDIG6_AFMT_ISRC1_0 0x5415 +#define CAR_mmDIG7_AFMT_ISRC1_0 0x5615 +#define CAR_mmDIG8_AFMT_ISRC1_0 0x5715 +#define CAR_mmAFMT_ISRC1_1 0x4a16 +#define CAR_mmDIG0_AFMT_ISRC1_1 0x4a16 +#define CAR_mmDIG1_AFMT_ISRC1_1 0x4b16 +#define CAR_mmDIG2_AFMT_ISRC1_1 0x4c16 +#define CAR_mmDIG3_AFMT_ISRC1_1 0x4d16 +#define CAR_mmDIG4_AFMT_ISRC1_1 0x4e16 +#define CAR_mmDIG5_AFMT_ISRC1_1 0x4f16 +#define CAR_mmDIG6_AFMT_ISRC1_1 0x5416 +#define CAR_mmDIG7_AFMT_ISRC1_1 0x5616 +#define CAR_mmDIG8_AFMT_ISRC1_1 0x5716 +#define CAR_mmAFMT_ISRC1_2 0x4a17 +#define CAR_mmDIG0_AFMT_ISRC1_2 0x4a17 +#define CAR_mmDIG1_AFMT_ISRC1_2 0x4b17 +#define CAR_mmDIG2_AFMT_ISRC1_2 0x4c17 +#define CAR_mmDIG3_AFMT_ISRC1_2 0x4d17 +#define CAR_mmDIG4_AFMT_ISRC1_2 0x4e17 +#define CAR_mmDIG5_AFMT_ISRC1_2 0x4f17 +#define CAR_mmDIG6_AFMT_ISRC1_2 0x5417 +#define CAR_mmDIG7_AFMT_ISRC1_2 0x5617 +#define CAR_mmDIG8_AFMT_ISRC1_2 0x5717 +#define CAR_mmAFMT_ISRC1_3 0x4a18 +#define CAR_mmDIG0_AFMT_ISRC1_3 0x4a18 +#define CAR_mmDIG1_AFMT_ISRC1_3 0x4b18 +#define CAR_mmDIG2_AFMT_ISRC1_3 0x4c18 +#define CAR_mmDIG3_AFMT_ISRC1_3 0x4d18 +#define CAR_mmDIG4_AFMT_ISRC1_3 0x4e18 +#define CAR_mmDIG5_AFMT_ISRC1_3 0x4f18 +#define CAR_mmDIG6_AFMT_ISRC1_3 0x5418 +#define CAR_mmDIG7_AFMT_ISRC1_3 0x5618 +#define CAR_mmDIG8_AFMT_ISRC1_3 0x5718 +#define CAR_mmAFMT_ISRC1_4 0x4a19 +#define CAR_mmDIG0_AFMT_ISRC1_4 0x4a19 +#define CAR_mmDIG1_AFMT_ISRC1_4 0x4b19 +#define CAR_mmDIG2_AFMT_ISRC1_4 0x4c19 +#define CAR_mmDIG3_AFMT_ISRC1_4 0x4d19 +#define CAR_mmDIG4_AFMT_ISRC1_4 0x4e19 +#define CAR_mmDIG5_AFMT_ISRC1_4 0x4f19 +#define CAR_mmDIG6_AFMT_ISRC1_4 0x5419 +#define CAR_mmDIG7_AFMT_ISRC1_4 0x5619 +#define CAR_mmDIG8_AFMT_ISRC1_4 0x5719 +#define CAR_mmAFMT_ISRC2_0 0x4a1a +#define CAR_mmDIG0_AFMT_ISRC2_0 0x4a1a +#define CAR_mmDIG1_AFMT_ISRC2_0 0x4b1a +#define CAR_mmDIG2_AFMT_ISRC2_0 0x4c1a +#define CAR_mmDIG3_AFMT_ISRC2_0 0x4d1a +#define CAR_mmDIG4_AFMT_ISRC2_0 0x4e1a +#define CAR_mmDIG5_AFMT_ISRC2_0 0x4f1a +#define CAR_mmDIG6_AFMT_ISRC2_0 0x541a +#define CAR_mmDIG7_AFMT_ISRC2_0 0x561a +#define CAR_mmDIG8_AFMT_ISRC2_0 0x571a +#define CAR_mmAFMT_ISRC2_1 0x4a1b +#define CAR_mmDIG0_AFMT_ISRC2_1 0x4a1b +#define CAR_mmDIG1_AFMT_ISRC2_1 0x4b1b +#define CAR_mmDIG2_AFMT_ISRC2_1 0x4c1b +#define CAR_mmDIG3_AFMT_ISRC2_1 0x4d1b +#define CAR_mmDIG4_AFMT_ISRC2_1 0x4e1b +#define CAR_mmDIG5_AFMT_ISRC2_1 0x4f1b +#define CAR_mmDIG6_AFMT_ISRC2_1 0x541b +#define CAR_mmDIG7_AFMT_ISRC2_1 0x561b +#define CAR_mmDIG8_AFMT_ISRC2_1 0x571b +#define CAR_mmAFMT_ISRC2_2 0x4a1c +#define CAR_mmDIG0_AFMT_ISRC2_2 0x4a1c +#define CAR_mmDIG1_AFMT_ISRC2_2 0x4b1c +#define CAR_mmDIG2_AFMT_ISRC2_2 0x4c1c +#define CAR_mmDIG3_AFMT_ISRC2_2 0x4d1c +#define CAR_mmDIG4_AFMT_ISRC2_2 0x4e1c +#define CAR_mmDIG5_AFMT_ISRC2_2 0x4f1c +#define CAR_mmDIG6_AFMT_ISRC2_2 0x541c +#define CAR_mmDIG7_AFMT_ISRC2_2 0x561c +#define CAR_mmDIG8_AFMT_ISRC2_2 0x571c +#define CAR_mmAFMT_ISRC2_3 0x4a1d +#define CAR_mmDIG0_AFMT_ISRC2_3 0x4a1d +#define CAR_mmDIG1_AFMT_ISRC2_3 0x4b1d +#define CAR_mmDIG2_AFMT_ISRC2_3 0x4c1d +#define CAR_mmDIG3_AFMT_ISRC2_3 0x4d1d +#define CAR_mmDIG4_AFMT_ISRC2_3 0x4e1d +#define CAR_mmDIG5_AFMT_ISRC2_3 0x4f1d +#define CAR_mmDIG6_AFMT_ISRC2_3 0x541d +#define CAR_mmDIG7_AFMT_ISRC2_3 0x561d +#define CAR_mmDIG8_AFMT_ISRC2_3 0x571d +#define CAR_mmAFMT_AVI_INFO0 0x4a1e +#define CAR_mmDIG0_AFMT_AVI_INFO0 0x4a1e +#define CAR_mmDIG1_AFMT_AVI_INFO0 0x4b1e +#define CAR_mmDIG2_AFMT_AVI_INFO0 0x4c1e +#define CAR_mmDIG3_AFMT_AVI_INFO0 0x4d1e +#define CAR_mmDIG4_AFMT_AVI_INFO0 0x4e1e +#define CAR_mmDIG5_AFMT_AVI_INFO0 0x4f1e +#define CAR_mmDIG6_AFMT_AVI_INFO0 0x541e +#define CAR_mmDIG7_AFMT_AVI_INFO0 0x561e +#define CAR_mmDIG8_AFMT_AVI_INFO0 0x571e +#define CAR_mmAFMT_AVI_INFO1 0x4a1f +#define CAR_mmDIG0_AFMT_AVI_INFO1 0x4a1f +#define CAR_mmDIG1_AFMT_AVI_INFO1 0x4b1f +#define CAR_mmDIG2_AFMT_AVI_INFO1 0x4c1f +#define CAR_mmDIG3_AFMT_AVI_INFO1 0x4d1f +#define CAR_mmDIG4_AFMT_AVI_INFO1 0x4e1f +#define CAR_mmDIG5_AFMT_AVI_INFO1 0x4f1f +#define CAR_mmDIG6_AFMT_AVI_INFO1 0x541f +#define CAR_mmDIG7_AFMT_AVI_INFO1 0x561f +#define CAR_mmDIG8_AFMT_AVI_INFO1 0x571f +#define CAR_mmAFMT_AVI_INFO2 0x4a20 +#define CAR_mmDIG0_AFMT_AVI_INFO2 0x4a20 +#define CAR_mmDIG1_AFMT_AVI_INFO2 0x4b20 +#define CAR_mmDIG2_AFMT_AVI_INFO2 0x4c20 +#define CAR_mmDIG3_AFMT_AVI_INFO2 0x4d20 +#define CAR_mmDIG4_AFMT_AVI_INFO2 0x4e20 +#define CAR_mmDIG5_AFMT_AVI_INFO2 0x4f20 +#define CAR_mmDIG6_AFMT_AVI_INFO2 0x5420 +#define CAR_mmDIG7_AFMT_AVI_INFO2 0x5620 +#define CAR_mmDIG8_AFMT_AVI_INFO2 0x5720 +#define CAR_mmAFMT_AVI_INFO3 0x4a21 +#define CAR_mmDIG0_AFMT_AVI_INFO3 0x4a21 +#define CAR_mmDIG1_AFMT_AVI_INFO3 0x4b21 +#define CAR_mmDIG2_AFMT_AVI_INFO3 0x4c21 +#define CAR_mmDIG3_AFMT_AVI_INFO3 0x4d21 +#define CAR_mmDIG4_AFMT_AVI_INFO3 0x4e21 +#define CAR_mmDIG5_AFMT_AVI_INFO3 0x4f21 +#define CAR_mmDIG6_AFMT_AVI_INFO3 0x5421 +#define CAR_mmDIG7_AFMT_AVI_INFO3 0x5621 +#define CAR_mmDIG8_AFMT_AVI_INFO3 0x5721 +#define CAR_mmAFMT_MPEG_INFO0 0x4a22 +#define CAR_mmDIG0_AFMT_MPEG_INFO0 0x4a22 +#define CAR_mmDIG1_AFMT_MPEG_INFO0 0x4b22 +#define CAR_mmDIG2_AFMT_MPEG_INFO0 0x4c22 +#define CAR_mmDIG3_AFMT_MPEG_INFO0 0x4d22 +#define CAR_mmDIG4_AFMT_MPEG_INFO0 0x4e22 +#define CAR_mmDIG5_AFMT_MPEG_INFO0 0x4f22 +#define CAR_mmDIG6_AFMT_MPEG_INFO0 0x5422 +#define CAR_mmDIG7_AFMT_MPEG_INFO0 0x5622 +#define CAR_mmDIG8_AFMT_MPEG_INFO0 0x5722 +#define CAR_mmAFMT_MPEG_INFO1 0x4a23 +#define CAR_mmDIG0_AFMT_MPEG_INFO1 0x4a23 +#define CAR_mmDIG1_AFMT_MPEG_INFO1 0x4b23 +#define CAR_mmDIG2_AFMT_MPEG_INFO1 0x4c23 +#define CAR_mmDIG3_AFMT_MPEG_INFO1 0x4d23 +#define CAR_mmDIG4_AFMT_MPEG_INFO1 0x4e23 +#define CAR_mmDIG5_AFMT_MPEG_INFO1 0x4f23 +#define CAR_mmDIG6_AFMT_MPEG_INFO1 0x5423 +#define CAR_mmDIG7_AFMT_MPEG_INFO1 0x5623 +#define CAR_mmDIG8_AFMT_MPEG_INFO1 0x5723 +#define CAR_mmAFMT_GENERIC_HDR 0x4a24 +#define CAR_mmDIG0_AFMT_GENERIC_HDR 0x4a24 +#define CAR_mmDIG1_AFMT_GENERIC_HDR 0x4b24 +#define CAR_mmDIG2_AFMT_GENERIC_HDR 0x4c24 +#define CAR_mmDIG3_AFMT_GENERIC_HDR 0x4d24 +#define CAR_mmDIG4_AFMT_GENERIC_HDR 0x4e24 +#define CAR_mmDIG5_AFMT_GENERIC_HDR 0x4f24 +#define CAR_mmDIG6_AFMT_GENERIC_HDR 0x5424 +#define CAR_mmDIG7_AFMT_GENERIC_HDR 0x5624 +#define CAR_mmDIG8_AFMT_GENERIC_HDR 0x5724 +#define CAR_mmAFMT_GENERIC_0 0x4a25 +#define CAR_mmDIG0_AFMT_GENERIC_0 0x4a25 +#define CAR_mmDIG1_AFMT_GENERIC_0 0x4b25 +#define CAR_mmDIG2_AFMT_GENERIC_0 0x4c25 +#define CAR_mmDIG3_AFMT_GENERIC_0 0x4d25 +#define CAR_mmDIG4_AFMT_GENERIC_0 0x4e25 +#define CAR_mmDIG5_AFMT_GENERIC_0 0x4f25 +#define CAR_mmDIG6_AFMT_GENERIC_0 0x5425 +#define CAR_mmDIG7_AFMT_GENERIC_0 0x5625 +#define CAR_mmDIG8_AFMT_GENERIC_0 0x5725 +#define CAR_mmAFMT_GENERIC_1 0x4a26 +#define CAR_mmDIG0_AFMT_GENERIC_1 0x4a26 +#define CAR_mmDIG1_AFMT_GENERIC_1 0x4b26 +#define CAR_mmDIG2_AFMT_GENERIC_1 0x4c26 +#define CAR_mmDIG3_AFMT_GENERIC_1 0x4d26 +#define CAR_mmDIG4_AFMT_GENERIC_1 0x4e26 +#define CAR_mmDIG5_AFMT_GENERIC_1 0x4f26 +#define CAR_mmDIG6_AFMT_GENERIC_1 0x5426 +#define CAR_mmDIG7_AFMT_GENERIC_1 0x5626 +#define CAR_mmDIG8_AFMT_GENERIC_1 0x5726 +#define CAR_mmAFMT_GENERIC_2 0x4a27 +#define CAR_mmDIG0_AFMT_GENERIC_2 0x4a27 +#define CAR_mmDIG1_AFMT_GENERIC_2 0x4b27 +#define CAR_mmDIG2_AFMT_GENERIC_2 0x4c27 +#define CAR_mmDIG3_AFMT_GENERIC_2 0x4d27 +#define CAR_mmDIG4_AFMT_GENERIC_2 0x4e27 +#define CAR_mmDIG5_AFMT_GENERIC_2 0x4f27 +#define CAR_mmDIG6_AFMT_GENERIC_2 0x5427 +#define CAR_mmDIG7_AFMT_GENERIC_2 0x5627 +#define CAR_mmDIG8_AFMT_GENERIC_2 0x5727 +#define CAR_mmAFMT_GENERIC_3 0x4a28 +#define CAR_mmDIG0_AFMT_GENERIC_3 0x4a28 +#define CAR_mmDIG1_AFMT_GENERIC_3 0x4b28 +#define CAR_mmDIG2_AFMT_GENERIC_3 0x4c28 +#define CAR_mmDIG3_AFMT_GENERIC_3 0x4d28 +#define CAR_mmDIG4_AFMT_GENERIC_3 0x4e28 +#define CAR_mmDIG5_AFMT_GENERIC_3 0x4f28 +#define CAR_mmDIG6_AFMT_GENERIC_3 0x5428 +#define CAR_mmDIG7_AFMT_GENERIC_3 0x5628 +#define CAR_mmDIG8_AFMT_GENERIC_3 0x5728 +#define CAR_mmAFMT_GENERIC_4 0x4a29 +#define CAR_mmDIG0_AFMT_GENERIC_4 0x4a29 +#define CAR_mmDIG1_AFMT_GENERIC_4 0x4b29 +#define CAR_mmDIG2_AFMT_GENERIC_4 0x4c29 +#define CAR_mmDIG3_AFMT_GENERIC_4 0x4d29 +#define CAR_mmDIG4_AFMT_GENERIC_4 0x4e29 +#define CAR_mmDIG5_AFMT_GENERIC_4 0x4f29 +#define CAR_mmDIG6_AFMT_GENERIC_4 0x5429 +#define CAR_mmDIG7_AFMT_GENERIC_4 0x5629 +#define CAR_mmDIG8_AFMT_GENERIC_4 0x5729 +#define CAR_mmAFMT_GENERIC_5 0x4a2a +#define CAR_mmDIG0_AFMT_GENERIC_5 0x4a2a +#define CAR_mmDIG1_AFMT_GENERIC_5 0x4b2a +#define CAR_mmDIG2_AFMT_GENERIC_5 0x4c2a +#define CAR_mmDIG3_AFMT_GENERIC_5 0x4d2a +#define CAR_mmDIG4_AFMT_GENERIC_5 0x4e2a +#define CAR_mmDIG5_AFMT_GENERIC_5 0x4f2a +#define CAR_mmDIG6_AFMT_GENERIC_5 0x542a +#define CAR_mmDIG7_AFMT_GENERIC_5 0x562a +#define CAR_mmDIG8_AFMT_GENERIC_5 0x572a +#define CAR_mmAFMT_GENERIC_6 0x4a2b +#define CAR_mmDIG0_AFMT_GENERIC_6 0x4a2b +#define CAR_mmDIG1_AFMT_GENERIC_6 0x4b2b +#define CAR_mmDIG2_AFMT_GENERIC_6 0x4c2b +#define CAR_mmDIG3_AFMT_GENERIC_6 0x4d2b +#define CAR_mmDIG4_AFMT_GENERIC_6 0x4e2b +#define CAR_mmDIG5_AFMT_GENERIC_6 0x4f2b +#define CAR_mmDIG6_AFMT_GENERIC_6 0x542b +#define CAR_mmDIG7_AFMT_GENERIC_6 0x562b +#define CAR_mmDIG8_AFMT_GENERIC_6 0x572b +#define CAR_mmAFMT_GENERIC_7 0x4a2c +#define CAR_mmDIG0_AFMT_GENERIC_7 0x4a2c +#define CAR_mmDIG1_AFMT_GENERIC_7 0x4b2c +#define CAR_mmDIG2_AFMT_GENERIC_7 0x4c2c +#define CAR_mmDIG3_AFMT_GENERIC_7 0x4d2c +#define CAR_mmDIG4_AFMT_GENERIC_7 0x4e2c +#define CAR_mmDIG5_AFMT_GENERIC_7 0x4f2c +#define CAR_mmDIG6_AFMT_GENERIC_7 0x542c +#define CAR_mmDIG7_AFMT_GENERIC_7 0x562c +#define CAR_mmDIG8_AFMT_GENERIC_7 0x572c +#define CAR_mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define CAR_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define CAR_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d +#define CAR_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d +#define CAR_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d +#define CAR_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d +#define CAR_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d +#define CAR_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d +#define CAR_mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 0x562d +#define CAR_mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 0x572d +#define CAR_mmHDMI_ACR_32_0 0x4a2e +#define CAR_mmDIG0_HDMI_ACR_32_0 0x4a2e +#define CAR_mmDIG1_HDMI_ACR_32_0 0x4b2e +#define CAR_mmDIG2_HDMI_ACR_32_0 0x4c2e +#define CAR_mmDIG3_HDMI_ACR_32_0 0x4d2e +#define CAR_mmDIG4_HDMI_ACR_32_0 0x4e2e +#define CAR_mmDIG5_HDMI_ACR_32_0 0x4f2e +#define CAR_mmDIG6_HDMI_ACR_32_0 0x542e +#define CAR_mmDIG7_HDMI_ACR_32_0 0x562e +#define CAR_mmDIG8_HDMI_ACR_32_0 0x572e +#define CAR_mmHDMI_ACR_32_1 0x4a2f +#define CAR_mmDIG0_HDMI_ACR_32_1 0x4a2f +#define CAR_mmDIG1_HDMI_ACR_32_1 0x4b2f +#define CAR_mmDIG2_HDMI_ACR_32_1 0x4c2f +#define CAR_mmDIG3_HDMI_ACR_32_1 0x4d2f +#define CAR_mmDIG4_HDMI_ACR_32_1 0x4e2f +#define CAR_mmDIG5_HDMI_ACR_32_1 0x4f2f +#define CAR_mmDIG6_HDMI_ACR_32_1 0x542f +#define CAR_mmDIG7_HDMI_ACR_32_1 0x562f +#define CAR_mmDIG8_HDMI_ACR_32_1 0x572f +#define CAR_mmHDMI_ACR_44_0 0x4a30 +#define CAR_mmDIG0_HDMI_ACR_44_0 0x4a30 +#define CAR_mmDIG1_HDMI_ACR_44_0 0x4b30 +#define CAR_mmDIG2_HDMI_ACR_44_0 0x4c30 +#define CAR_mmDIG3_HDMI_ACR_44_0 0x4d30 +#define CAR_mmDIG4_HDMI_ACR_44_0 0x4e30 +#define CAR_mmDIG5_HDMI_ACR_44_0 0x4f30 +#define CAR_mmDIG6_HDMI_ACR_44_0 0x5430 +#define CAR_mmDIG7_HDMI_ACR_44_0 0x5630 +#define CAR_mmDIG8_HDMI_ACR_44_0 0x5730 +#define CAR_mmHDMI_ACR_44_1 0x4a31 +#define CAR_mmDIG0_HDMI_ACR_44_1 0x4a31 +#define CAR_mmDIG1_HDMI_ACR_44_1 0x4b31 +#define CAR_mmDIG2_HDMI_ACR_44_1 0x4c31 +#define CAR_mmDIG3_HDMI_ACR_44_1 0x4d31 +#define CAR_mmDIG4_HDMI_ACR_44_1 0x4e31 +#define CAR_mmDIG5_HDMI_ACR_44_1 0x4f31 +#define CAR_mmDIG6_HDMI_ACR_44_1 0x5431 +#define CAR_mmDIG7_HDMI_ACR_44_1 0x5631 +#define CAR_mmDIG8_HDMI_ACR_44_1 0x5731 +#define CAR_mmHDMI_ACR_48_0 0x4a32 +#define CAR_mmDIG0_HDMI_ACR_48_0 0x4a32 +#define CAR_mmDIG1_HDMI_ACR_48_0 0x4b32 +#define CAR_mmDIG2_HDMI_ACR_48_0 0x4c32 +#define CAR_mmDIG3_HDMI_ACR_48_0 0x4d32 +#define CAR_mmDIG4_HDMI_ACR_48_0 0x4e32 +#define CAR_mmDIG5_HDMI_ACR_48_0 0x4f32 +#define CAR_mmDIG6_HDMI_ACR_48_0 0x5432 +#define CAR_mmDIG7_HDMI_ACR_48_0 0x5632 +#define CAR_mmDIG8_HDMI_ACR_48_0 0x5732 +#define CAR_mmHDMI_ACR_48_1 0x4a33 +#define CAR_mmDIG0_HDMI_ACR_48_1 0x4a33 +#define CAR_mmDIG1_HDMI_ACR_48_1 0x4b33 +#define CAR_mmDIG2_HDMI_ACR_48_1 0x4c33 +#define CAR_mmDIG3_HDMI_ACR_48_1 0x4d33 +#define CAR_mmDIG4_HDMI_ACR_48_1 0x4e33 +#define CAR_mmDIG5_HDMI_ACR_48_1 0x4f33 +#define CAR_mmDIG6_HDMI_ACR_48_1 0x5433 +#define CAR_mmDIG7_HDMI_ACR_48_1 0x5633 +#define CAR_mmDIG8_HDMI_ACR_48_1 0x5733 +#define CAR_mmHDMI_ACR_STATUS_0 0x4a34 +#define CAR_mmDIG0_HDMI_ACR_STATUS_0 0x4a34 +#define CAR_mmDIG1_HDMI_ACR_STATUS_0 0x4b34 +#define CAR_mmDIG2_HDMI_ACR_STATUS_0 0x4c34 +#define CAR_mmDIG3_HDMI_ACR_STATUS_0 0x4d34 +#define CAR_mmDIG4_HDMI_ACR_STATUS_0 0x4e34 +#define CAR_mmDIG5_HDMI_ACR_STATUS_0 0x4f34 +#define CAR_mmDIG6_HDMI_ACR_STATUS_0 0x5434 +#define CAR_mmDIG7_HDMI_ACR_STATUS_0 0x5634 +#define CAR_mmDIG8_HDMI_ACR_STATUS_0 0x5734 +#define CAR_mmHDMI_ACR_STATUS_1 0x4a35 +#define CAR_mmDIG0_HDMI_ACR_STATUS_1 0x4a35 +#define CAR_mmDIG1_HDMI_ACR_STATUS_1 0x4b35 +#define CAR_mmDIG2_HDMI_ACR_STATUS_1 0x4c35 +#define CAR_mmDIG3_HDMI_ACR_STATUS_1 0x4d35 +#define CAR_mmDIG4_HDMI_ACR_STATUS_1 0x4e35 +#define CAR_mmDIG5_HDMI_ACR_STATUS_1 0x4f35 +#define CAR_mmDIG6_HDMI_ACR_STATUS_1 0x5435 +#define CAR_mmDIG7_HDMI_ACR_STATUS_1 0x5635 +#define CAR_mmDIG8_HDMI_ACR_STATUS_1 0x5735 +#define CAR_mmAFMT_AUDIO_INFO0 0x4a36 +#define CAR_mmDIG0_AFMT_AUDIO_INFO0 0x4a36 +#define CAR_mmDIG1_AFMT_AUDIO_INFO0 0x4b36 +#define CAR_mmDIG2_AFMT_AUDIO_INFO0 0x4c36 +#define CAR_mmDIG3_AFMT_AUDIO_INFO0 0x4d36 +#define CAR_mmDIG4_AFMT_AUDIO_INFO0 0x4e36 +#define CAR_mmDIG5_AFMT_AUDIO_INFO0 0x4f36 +#define CAR_mmDIG6_AFMT_AUDIO_INFO0 0x5436 +#define CAR_mmDIG7_AFMT_AUDIO_INFO0 0x5636 +#define CAR_mmDIG8_AFMT_AUDIO_INFO0 0x5736 +#define CAR_mmAFMT_AUDIO_INFO1 0x4a37 +#define CAR_mmDIG0_AFMT_AUDIO_INFO1 0x4a37 +#define CAR_mmDIG1_AFMT_AUDIO_INFO1 0x4b37 +#define CAR_mmDIG2_AFMT_AUDIO_INFO1 0x4c37 +#define CAR_mmDIG3_AFMT_AUDIO_INFO1 0x4d37 +#define CAR_mmDIG4_AFMT_AUDIO_INFO1 0x4e37 +#define CAR_mmDIG5_AFMT_AUDIO_INFO1 0x4f37 +#define CAR_mmDIG6_AFMT_AUDIO_INFO1 0x5437 +#define CAR_mmDIG7_AFMT_AUDIO_INFO1 0x5637 +#define CAR_mmDIG8_AFMT_AUDIO_INFO1 0x5737 +#define CAR_mmAFMT_60958_0 0x4a38 +#define CAR_mmDIG0_AFMT_60958_0 0x4a38 +#define CAR_mmDIG1_AFMT_60958_0 0x4b38 +#define CAR_mmDIG2_AFMT_60958_0 0x4c38 +#define CAR_mmDIG3_AFMT_60958_0 0x4d38 +#define CAR_mmDIG4_AFMT_60958_0 0x4e38 +#define CAR_mmDIG5_AFMT_60958_0 0x4f38 +#define CAR_mmDIG6_AFMT_60958_0 0x5438 +#define CAR_mmDIG7_AFMT_60958_0 0x5638 +#define CAR_mmDIG8_AFMT_60958_0 0x5738 +#define CAR_mmAFMT_60958_1 0x4a39 +#define CAR_mmDIG0_AFMT_60958_1 0x4a39 +#define CAR_mmDIG1_AFMT_60958_1 0x4b39 +#define CAR_mmDIG2_AFMT_60958_1 0x4c39 +#define CAR_mmDIG3_AFMT_60958_1 0x4d39 +#define CAR_mmDIG4_AFMT_60958_1 0x4e39 +#define CAR_mmDIG5_AFMT_60958_1 0x4f39 +#define CAR_mmDIG6_AFMT_60958_1 0x5439 +#define CAR_mmDIG7_AFMT_60958_1 0x5639 +#define CAR_mmDIG8_AFMT_60958_1 0x5739 +#define CAR_mmAFMT_AUDIO_CRC_CONTROL 0x4a3a +#define CAR_mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a +#define CAR_mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a +#define CAR_mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a +#define CAR_mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a +#define CAR_mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a +#define CAR_mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a +#define CAR_mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a +#define CAR_mmDIG7_AFMT_AUDIO_CRC_CONTROL 0x563a +#define CAR_mmDIG8_AFMT_AUDIO_CRC_CONTROL 0x573a +#define CAR_mmAFMT_RAMP_CONTROL0 0x4a3b +#define CAR_mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b +#define CAR_mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b +#define CAR_mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b +#define CAR_mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b +#define CAR_mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b +#define CAR_mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b +#define CAR_mmDIG6_AFMT_RAMP_CONTROL0 0x543b +#define CAR_mmDIG7_AFMT_RAMP_CONTROL0 0x563b +#define CAR_mmDIG8_AFMT_RAMP_CONTROL0 0x573b +#define CAR_mmAFMT_RAMP_CONTROL1 0x4a3c +#define CAR_mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c +#define CAR_mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c +#define CAR_mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c +#define CAR_mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c +#define CAR_mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c +#define CAR_mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c +#define CAR_mmDIG6_AFMT_RAMP_CONTROL1 0x543c +#define CAR_mmDIG7_AFMT_RAMP_CONTROL1 0x563c +#define CAR_mmDIG8_AFMT_RAMP_CONTROL1 0x573c +#define CAR_mmAFMT_RAMP_CONTROL2 0x4a3d +#define CAR_mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d +#define CAR_mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d +#define CAR_mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d +#define CAR_mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d +#define CAR_mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d +#define CAR_mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d +#define CAR_mmDIG6_AFMT_RAMP_CONTROL2 0x543d +#define CAR_mmDIG7_AFMT_RAMP_CONTROL2 0x563d +#define CAR_mmDIG8_AFMT_RAMP_CONTROL2 0x573d +#define CAR_mmAFMT_RAMP_CONTROL3 0x4a3e +#define CAR_mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e +#define CAR_mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e +#define CAR_mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e +#define CAR_mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e +#define CAR_mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e +#define CAR_mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e +#define CAR_mmDIG6_AFMT_RAMP_CONTROL3 0x543e +#define CAR_mmDIG7_AFMT_RAMP_CONTROL3 0x563e +#define CAR_mmDIG8_AFMT_RAMP_CONTROL3 0x573e +#define CAR_mmAFMT_60958_2 0x4a3f +#define CAR_mmDIG0_AFMT_60958_2 0x4a3f +#define CAR_mmDIG1_AFMT_60958_2 0x4b3f +#define CAR_mmDIG2_AFMT_60958_2 0x4c3f +#define CAR_mmDIG3_AFMT_60958_2 0x4d3f +#define CAR_mmDIG4_AFMT_60958_2 0x4e3f +#define CAR_mmDIG5_AFMT_60958_2 0x4f3f +#define CAR_mmDIG6_AFMT_60958_2 0x543f +#define CAR_mmDIG7_AFMT_60958_2 0x563f +#define CAR_mmDIG8_AFMT_60958_2 0x573f +#define CAR_mmAFMT_AUDIO_CRC_RESULT 0x4a40 +#define CAR_mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 +#define CAR_mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 +#define CAR_mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 +#define CAR_mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 +#define CAR_mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 +#define CAR_mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 +#define CAR_mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 +#define CAR_mmDIG7_AFMT_AUDIO_CRC_RESULT 0x5640 +#define CAR_mmDIG8_AFMT_AUDIO_CRC_RESULT 0x5740 +#define CAR_mmAFMT_STATUS 0x4a41 +#define CAR_mmDIG0_AFMT_STATUS 0x4a41 +#define CAR_mmDIG1_AFMT_STATUS 0x4b41 +#define CAR_mmDIG2_AFMT_STATUS 0x4c41 +#define CAR_mmDIG3_AFMT_STATUS 0x4d41 +#define CAR_mmDIG4_AFMT_STATUS 0x4e41 +#define CAR_mmDIG5_AFMT_STATUS 0x4f41 +#define CAR_mmDIG6_AFMT_STATUS 0x5441 +#define CAR_mmDIG7_AFMT_STATUS 0x5641 +#define CAR_mmDIG8_AFMT_STATUS 0x5741 +#define CAR_mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define CAR_mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define CAR_mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 +#define CAR_mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 +#define CAR_mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 +#define CAR_mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 +#define CAR_mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 +#define CAR_mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 +#define CAR_mmDIG7_AFMT_AUDIO_PACKET_CONTROL 0x5642 +#define CAR_mmDIG8_AFMT_AUDIO_PACKET_CONTROL 0x5742 +#define CAR_mmAFMT_VBI_PACKET_CONTROL 0x4a43 +#define CAR_mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 +#define CAR_mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 +#define CAR_mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 +#define CAR_mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 +#define CAR_mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 +#define CAR_mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 +#define CAR_mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 +#define CAR_mmDIG7_AFMT_VBI_PACKET_CONTROL 0x5643 +#define CAR_mmDIG8_AFMT_VBI_PACKET_CONTROL 0x5743 +#define CAR_mmAFMT_INFOFRAME_CONTROL0 0x4a44 +#define CAR_mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 +#define CAR_mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 +#define CAR_mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 +#define CAR_mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 +#define CAR_mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 +#define CAR_mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 +#define CAR_mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 +#define CAR_mmDIG7_AFMT_INFOFRAME_CONTROL0 0x5644 +#define CAR_mmDIG8_AFMT_INFOFRAME_CONTROL0 0x5744 +#define CAR_mmAFMT_AUDIO_SRC_CONTROL 0x4a45 +#define CAR_mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 +#define CAR_mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 +#define CAR_mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 +#define CAR_mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 +#define CAR_mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 +#define CAR_mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 +#define CAR_mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 +#define CAR_mmDIG7_AFMT_AUDIO_SRC_CONTROL 0x5645 +#define CAR_mmDIG8_AFMT_AUDIO_SRC_CONTROL 0x5745 +#define CAR_mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define CAR_mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define CAR_mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 +#define CAR_mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 +#define CAR_mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 +#define CAR_mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 +#define CAR_mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 +#define CAR_mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 +#define CAR_mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL 0x5646 +#define CAR_mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL 0x5746 +#define CAR_mmAFMT_CNTL 0x4a7e +#define CAR_mmDIG0_AFMT_CNTL 0x4a7e +#define CAR_mmDIG1_AFMT_CNTL 0x4b7e +#define CAR_mmDIG2_AFMT_CNTL 0x4c7e +#define CAR_mmDIG3_AFMT_CNTL 0x4d7e +#define CAR_mmDIG4_AFMT_CNTL 0x4e7e +#define CAR_mmDIG5_AFMT_CNTL 0x4f7e +#define CAR_mmDIG6_AFMT_CNTL 0x547e +#define CAR_mmDIG7_AFMT_CNTL 0x567e +#define CAR_mmDIG8_AFMT_CNTL 0x577e +#define CAR_mmDIG_BE_CNTL 0x4a47 +#define CAR_mmDIG0_DIG_BE_CNTL 0x4a47 +#define CAR_mmDIG1_DIG_BE_CNTL 0x4b47 +#define CAR_mmDIG2_DIG_BE_CNTL 0x4c47 +#define CAR_mmDIG3_DIG_BE_CNTL 0x4d47 +#define CAR_mmDIG4_DIG_BE_CNTL 0x4e47 +#define CAR_mmDIG5_DIG_BE_CNTL 0x4f47 +#define CAR_mmDIG6_DIG_BE_CNTL 0x5447 +#define CAR_mmDIG7_DIG_BE_CNTL 0x5647 +#define CAR_mmDIG8_DIG_BE_CNTL 0x5747 +#define CAR_mmDIG_BE_EN_CNTL 0x4a48 +#define CAR_mmDIG0_DIG_BE_EN_CNTL 0x4a48 +#define CAR_mmDIG1_DIG_BE_EN_CNTL 0x4b48 +#define CAR_mmDIG2_DIG_BE_EN_CNTL 0x4c48 +#define CAR_mmDIG3_DIG_BE_EN_CNTL 0x4d48 +#define CAR_mmDIG4_DIG_BE_EN_CNTL 0x4e48 +#define CAR_mmDIG5_DIG_BE_EN_CNTL 0x4f48 +#define CAR_mmDIG6_DIG_BE_EN_CNTL 0x5448 +#define CAR_mmDIG7_DIG_BE_EN_CNTL 0x5648 +#define CAR_mmDIG8_DIG_BE_EN_CNTL 0x5748 +#define CAR_mmTMDS_CNTL 0x4a6b +#define CAR_mmDIG0_TMDS_CNTL 0x4a6b +#define CAR_mmDIG1_TMDS_CNTL 0x4b6b +#define CAR_mmDIG2_TMDS_CNTL 0x4c6b +#define CAR_mmDIG3_TMDS_CNTL 0x4d6b +#define CAR_mmDIG4_TMDS_CNTL 0x4e6b +#define CAR_mmDIG5_TMDS_CNTL 0x4f6b +#define CAR_mmDIG6_TMDS_CNTL 0x546b +#define CAR_mmDIG7_TMDS_CNTL 0x566b +#define CAR_mmDIG8_TMDS_CNTL 0x576b +#define CAR_mmTMDS_CONTROL_CHAR 0x4a6c +#define CAR_mmDIG0_TMDS_CONTROL_CHAR 0x4a6c +#define CAR_mmDIG1_TMDS_CONTROL_CHAR 0x4b6c +#define CAR_mmDIG2_TMDS_CONTROL_CHAR 0x4c6c +#define CAR_mmDIG3_TMDS_CONTROL_CHAR 0x4d6c +#define CAR_mmDIG4_TMDS_CONTROL_CHAR 0x4e6c +#define CAR_mmDIG5_TMDS_CONTROL_CHAR 0x4f6c +#define CAR_mmDIG6_TMDS_CONTROL_CHAR 0x546c +#define CAR_mmDIG7_TMDS_CONTROL_CHAR 0x566c +#define CAR_mmDIG8_TMDS_CONTROL_CHAR 0x576c +#define CAR_mmTMDS_CONTROL0_FEEDBACK 0x4a6d +#define CAR_mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d +#define CAR_mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d +#define CAR_mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d +#define CAR_mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d +#define CAR_mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d +#define CAR_mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d +#define CAR_mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d +#define CAR_mmDIG7_TMDS_CONTROL0_FEEDBACK 0x566d +#define CAR_mmDIG8_TMDS_CONTROL0_FEEDBACK 0x576d +#define CAR_mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define CAR_mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define CAR_mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e +#define CAR_mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e +#define CAR_mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e +#define CAR_mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e +#define CAR_mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e +#define CAR_mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e +#define CAR_mmDIG7_TMDS_STEREOSYNC_CTL_SEL 0x566e +#define CAR_mmDIG8_TMDS_STEREOSYNC_CTL_SEL 0x576e +#define CAR_mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define CAR_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define CAR_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f +#define CAR_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f +#define CAR_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f +#define CAR_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f +#define CAR_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f +#define CAR_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f +#define CAR_mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 0x566f +#define CAR_mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 0x576f +#define CAR_mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define CAR_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define CAR_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 +#define CAR_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 +#define CAR_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 +#define CAR_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 +#define CAR_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 +#define CAR_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 +#define CAR_mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 0x5670 +#define CAR_mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 0x5770 +#define CAR_mmTMDS_DEBUG 0x4a71 +#define CAR_mmDIG0_TMDS_DEBUG 0x4a71 +#define CAR_mmDIG1_TMDS_DEBUG 0x4b71 +#define CAR_mmDIG2_TMDS_DEBUG 0x4c71 +#define CAR_mmDIG3_TMDS_DEBUG 0x4d71 +#define CAR_mmDIG4_TMDS_DEBUG 0x4e71 +#define CAR_mmDIG5_TMDS_DEBUG 0x4f71 +#define CAR_mmDIG6_TMDS_DEBUG 0x5471 +#define CAR_mmDIG7_TMDS_DEBUG 0x5671 +#define CAR_mmDIG8_TMDS_DEBUG 0x5771 +#define CAR_mmTMDS_CTL_BITS 0x4a72 +#define CAR_mmDIG0_TMDS_CTL_BITS 0x4a72 +#define CAR_mmDIG1_TMDS_CTL_BITS 0x4b72 +#define CAR_mmDIG2_TMDS_CTL_BITS 0x4c72 +#define CAR_mmDIG3_TMDS_CTL_BITS 0x4d72 +#define CAR_mmDIG4_TMDS_CTL_BITS 0x4e72 +#define CAR_mmDIG5_TMDS_CTL_BITS 0x4f72 +#define CAR_mmDIG6_TMDS_CTL_BITS 0x5472 +#define CAR_mmDIG7_TMDS_CTL_BITS 0x5672 +#define CAR_mmDIG8_TMDS_CTL_BITS 0x5772 +#define CAR_mmTMDS_DCBALANCER_CONTROL 0x4a73 +#define CAR_mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 +#define CAR_mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 +#define CAR_mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 +#define CAR_mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 +#define CAR_mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 +#define CAR_mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 +#define CAR_mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 +#define CAR_mmDIG7_TMDS_DCBALANCER_CONTROL 0x5673 +#define CAR_mmDIG8_TMDS_DCBALANCER_CONTROL 0x5773 +#define CAR_mmTMDS_CTL0_1_GEN_CNTL 0x4a75 +#define CAR_mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 +#define CAR_mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 +#define CAR_mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 +#define CAR_mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 +#define CAR_mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 +#define CAR_mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 +#define CAR_mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 +#define CAR_mmDIG7_TMDS_CTL0_1_GEN_CNTL 0x5675 +#define CAR_mmDIG8_TMDS_CTL0_1_GEN_CNTL 0x5775 +#define CAR_mmTMDS_CTL2_3_GEN_CNTL 0x4a76 +#define CAR_mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 +#define CAR_mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 +#define CAR_mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 +#define CAR_mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 +#define CAR_mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 +#define CAR_mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 +#define CAR_mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 +#define CAR_mmDIG7_TMDS_CTL2_3_GEN_CNTL 0x5676 +#define CAR_mmDIG8_TMDS_CTL2_3_GEN_CNTL 0x5776 +#define CAR_mmDIG_VERSION 0x4a78 +#define CAR_mmDIG0_DIG_VERSION 0x4a78 +#define CAR_mmDIG1_DIG_VERSION 0x4b78 +#define CAR_mmDIG2_DIG_VERSION 0x4c78 +#define CAR_mmDIG3_DIG_VERSION 0x4d78 +#define CAR_mmDIG4_DIG_VERSION 0x4e78 +#define CAR_mmDIG5_DIG_VERSION 0x4f78 +#define CAR_mmDIG6_DIG_VERSION 0x5478 +#define CAR_mmDIG7_DIG_VERSION 0x5678 +#define CAR_mmDIG8_DIG_VERSION 0x5778 +#define CAR_mmDIG_LANE_ENABLE 0x4a79 +#define CAR_mmDIG0_DIG_LANE_ENABLE 0x4a79 +#define CAR_mmDIG1_DIG_LANE_ENABLE 0x4b79 +#define CAR_mmDIG2_DIG_LANE_ENABLE 0x4c79 +#define CAR_mmDIG3_DIG_LANE_ENABLE 0x4d79 +#define CAR_mmDIG4_DIG_LANE_ENABLE 0x4e79 +#define CAR_mmDIG5_DIG_LANE_ENABLE 0x4f79 +#define CAR_mmDIG6_DIG_LANE_ENABLE 0x5479 +#define CAR_mmDIG7_DIG_LANE_ENABLE 0x5679 +#define CAR_mmDIG8_DIG_LANE_ENABLE 0x5779 +#define CAR_mmDIG_TEST_DEBUG_INDEX 0x4a7a +#define CAR_mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a +#define CAR_mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a +#define CAR_mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a +#define CAR_mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a +#define CAR_mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a +#define CAR_mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a +#define CAR_mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a +#define CAR_mmDIG7_DIG_TEST_DEBUG_INDEX 0x567a +#define CAR_mmDIG8_DIG_TEST_DEBUG_INDEX 0x577a +#define CAR_mmDIG_TEST_DEBUG_DATA 0x4a7b +#define CAR_mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b +#define CAR_mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b +#define CAR_mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b +#define CAR_mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b +#define CAR_mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b +#define CAR_mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b +#define CAR_mmDIG6_DIG_TEST_DEBUG_DATA 0x547b +#define CAR_mmDIG7_DIG_TEST_DEBUG_DATA 0x567b +#define CAR_mmDIG8_DIG_TEST_DEBUG_DATA 0x577b +#define CAR_mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define CAR_mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define CAR_mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c +#define CAR_mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c +#define CAR_mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c +#define CAR_mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c +#define CAR_mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c +#define CAR_mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c +#define CAR_mmDIG7_DIG_FE_TEST_DEBUG_INDEX 0x567c +#define CAR_mmDIG8_DIG_FE_TEST_DEBUG_INDEX 0x577c +#define CAR_mmDIG_FE_TEST_DEBUG_DATA 0x4a7d +#define CAR_mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d +#define CAR_mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d +#define CAR_mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d +#define CAR_mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d +#define CAR_mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d +#define CAR_mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d +#define CAR_mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d +#define CAR_mmDIG7_DIG_FE_TEST_DEBUG_DATA 0x567d +#define CAR_mmDIG8_DIG_FE_TEST_DEBUG_DATA 0x577d +#define CAR_mmDMCU_CTRL 0x1600 +#define CAR_mmDMCU_STATUS 0x1601 +#define CAR_mmDMCU_PC_START_ADDR 0x1602 +#define CAR_mmDMCU_FW_START_ADDR 0x1603 +#define CAR_mmDMCU_FW_END_ADDR 0x1604 +#define CAR_mmDMCU_FW_ISR_START_ADDR 0x1605 +#define CAR_mmDMCU_FW_CS_HI 0x1606 +#define CAR_mmDMCU_FW_CS_LO 0x1607 +#define CAR_mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define CAR_mmDMCU_ERAM_WR_CTRL 0x1609 +#define CAR_mmDMCU_ERAM_WR_DATA 0x160a +#define CAR_mmDMCU_ERAM_RD_CTRL 0x160b +#define CAR_mmDMCU_ERAM_RD_DATA 0x160c +#define CAR_mmDMCU_IRAM_WR_CTRL 0x160d +#define CAR_mmDMCU_IRAM_WR_DATA 0x160e +#define CAR_mmDMCU_IRAM_RD_CTRL 0x160f +#define CAR_mmDMCU_IRAM_RD_DATA 0x1610 +#define CAR_mmDMCU_EVENT_TRIGGER 0x1611 +#define CAR_mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define CAR_mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 +#define CAR_mmDMCU_INTERRUPT_STATUS 0x1614 +#define CAR_mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define CAR_mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define CAR_mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x1631 +#define CAR_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define CAR_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x1632 +#define CAR_mmDC_DMCU_SCRATCH 0x1618 +#define CAR_mmDMCU_INT_CNT 0x1619 +#define CAR_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a +#define CAR_mmDMCU_UC_CLK_GATING_CNTL 0x161b +#define CAR_mmMASTER_COMM_DATA_REG1 0x161c +#define CAR_mmMASTER_COMM_DATA_REG2 0x161d +#define CAR_mmMASTER_COMM_DATA_REG3 0x161e +#define CAR_mmMASTER_COMM_CMD_REG 0x161f +#define CAR_mmMASTER_COMM_CNTL_REG 0x1620 +#define CAR_mmSLAVE_COMM_DATA_REG1 0x1621 +#define CAR_mmSLAVE_COMM_DATA_REG2 0x1622 +#define CAR_mmSLAVE_COMM_DATA_REG3 0x1623 +#define CAR_mmSLAVE_COMM_CMD_REG 0x1624 +#define CAR_mmSLAVE_COMM_CNTL_REG 0x1625 +#define CAR_mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define CAR_mmDMCU_TEST_DEBUG_DATA 0x1627 +#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 +#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 +#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 +#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 +#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b +#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 +#define CAR_mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 +#define CAR_mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 +#define CAR_mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 +#define CAR_mmDP_LINK_CNTL 0x4aa0 +#define CAR_mmDP0_DP_LINK_CNTL 0x4aa0 +#define CAR_mmDP1_DP_LINK_CNTL 0x4ba0 +#define CAR_mmDP2_DP_LINK_CNTL 0x4ca0 +#define CAR_mmDP3_DP_LINK_CNTL 0x4da0 +#define CAR_mmDP4_DP_LINK_CNTL 0x4ea0 +#define CAR_mmDP5_DP_LINK_CNTL 0x4fa0 +#define CAR_mmDP6_DP_LINK_CNTL 0x54a0 +#define CAR_mmDP7_DP_LINK_CNTL 0x56a0 +#define CAR_mmDP8_DP_LINK_CNTL 0x57a0 +#define CAR_mmDP_PIXEL_FORMAT 0x4aa1 +#define CAR_mmDP0_DP_PIXEL_FORMAT 0x4aa1 +#define CAR_mmDP1_DP_PIXEL_FORMAT 0x4ba1 +#define CAR_mmDP2_DP_PIXEL_FORMAT 0x4ca1 +#define CAR_mmDP3_DP_PIXEL_FORMAT 0x4da1 +#define CAR_mmDP4_DP_PIXEL_FORMAT 0x4ea1 +#define CAR_mmDP5_DP_PIXEL_FORMAT 0x4fa1 +#define CAR_mmDP6_DP_PIXEL_FORMAT 0x54a1 +#define CAR_mmDP7_DP_PIXEL_FORMAT 0x56a1 +#define CAR_mmDP8_DP_PIXEL_FORMAT 0x57a1 +#define CAR_mmDP_MSA_COLORIMETRY 0x4aa2 +#define CAR_mmDP0_DP_MSA_COLORIMETRY 0x4aa2 +#define CAR_mmDP1_DP_MSA_COLORIMETRY 0x4ba2 +#define CAR_mmDP2_DP_MSA_COLORIMETRY 0x4ca2 +#define CAR_mmDP3_DP_MSA_COLORIMETRY 0x4da2 +#define CAR_mmDP4_DP_MSA_COLORIMETRY 0x4ea2 +#define CAR_mmDP5_DP_MSA_COLORIMETRY 0x4fa2 +#define CAR_mmDP6_DP_MSA_COLORIMETRY 0x54a2 +#define CAR_mmDP7_DP_MSA_COLORIMETRY 0x56a2 +#define CAR_mmDP8_DP_MSA_COLORIMETRY 0x57a2 +#define CAR_mmDP_CONFIG 0x4aa3 +#define CAR_mmDP0_DP_CONFIG 0x4aa3 +#define CAR_mmDP1_DP_CONFIG 0x4ba3 +#define CAR_mmDP2_DP_CONFIG 0x4ca3 +#define CAR_mmDP3_DP_CONFIG 0x4da3 +#define CAR_mmDP4_DP_CONFIG 0x4ea3 +#define CAR_mmDP5_DP_CONFIG 0x4fa3 +#define CAR_mmDP6_DP_CONFIG 0x54a3 +#define CAR_mmDP7_DP_CONFIG 0x56a3 +#define CAR_mmDP8_DP_CONFIG 0x57a3 +#define CAR_mmDP_VID_STREAM_CNTL 0x4aa4 +#define CAR_mmDP0_DP_VID_STREAM_CNTL 0x4aa4 +#define CAR_mmDP1_DP_VID_STREAM_CNTL 0x4ba4 +#define CAR_mmDP2_DP_VID_STREAM_CNTL 0x4ca4 +#define CAR_mmDP3_DP_VID_STREAM_CNTL 0x4da4 +#define CAR_mmDP4_DP_VID_STREAM_CNTL 0x4ea4 +#define CAR_mmDP5_DP_VID_STREAM_CNTL 0x4fa4 +#define CAR_mmDP6_DP_VID_STREAM_CNTL 0x54a4 +#define CAR_mmDP7_DP_VID_STREAM_CNTL 0x56a4 +#define CAR_mmDP8_DP_VID_STREAM_CNTL 0x57a4 +#define CAR_mmDP_STEER_FIFO 0x4aa5 +#define CAR_mmDP0_DP_STEER_FIFO 0x4aa5 +#define CAR_mmDP1_DP_STEER_FIFO 0x4ba5 +#define CAR_mmDP2_DP_STEER_FIFO 0x4ca5 +#define CAR_mmDP3_DP_STEER_FIFO 0x4da5 +#define CAR_mmDP4_DP_STEER_FIFO 0x4ea5 +#define CAR_mmDP5_DP_STEER_FIFO 0x4fa5 +#define CAR_mmDP6_DP_STEER_FIFO 0x54a5 +#define CAR_mmDP7_DP_STEER_FIFO 0x56a5 +#define CAR_mmDP8_DP_STEER_FIFO 0x57a5 +#define CAR_mmDP_MSA_MISC 0x4aa6 +#define CAR_mmDP0_DP_MSA_MISC 0x4aa6 +#define CAR_mmDP1_DP_MSA_MISC 0x4ba6 +#define CAR_mmDP2_DP_MSA_MISC 0x4ca6 +#define CAR_mmDP3_DP_MSA_MISC 0x4da6 +#define CAR_mmDP4_DP_MSA_MISC 0x4ea6 +#define CAR_mmDP5_DP_MSA_MISC 0x4fa6 +#define CAR_mmDP6_DP_MSA_MISC 0x54a6 +#define CAR_mmDP7_DP_MSA_MISC 0x56a6 +#define CAR_mmDP8_DP_MSA_MISC 0x57a6 +#define CAR_mmDP_VID_TIMING 0x4aa8 +#define CAR_mmDP0_DP_VID_TIMING 0x4aa8 +#define CAR_mmDP1_DP_VID_TIMING 0x4ba8 +#define CAR_mmDP2_DP_VID_TIMING 0x4ca8 +#define CAR_mmDP3_DP_VID_TIMING 0x4da8 +#define CAR_mmDP4_DP_VID_TIMING 0x4ea8 +#define CAR_mmDP5_DP_VID_TIMING 0x4fa8 +#define CAR_mmDP6_DP_VID_TIMING 0x54a8 +#define CAR_mmDP7_DP_VID_TIMING 0x56a8 +#define CAR_mmDP8_DP_VID_TIMING 0x57a8 +#define CAR_mmDP_VID_N 0x4aa9 +#define CAR_mmDP0_DP_VID_N 0x4aa9 +#define CAR_mmDP1_DP_VID_N 0x4ba9 +#define CAR_mmDP2_DP_VID_N 0x4ca9 +#define CAR_mmDP3_DP_VID_N 0x4da9 +#define CAR_mmDP4_DP_VID_N 0x4ea9 +#define CAR_mmDP5_DP_VID_N 0x4fa9 +#define CAR_mmDP6_DP_VID_N 0x54a9 +#define CAR_mmDP7_DP_VID_N 0x56a9 +#define CAR_mmDP8_DP_VID_N 0x57a9 +#define CAR_mmDP_VID_M 0x4aaa +#define CAR_mmDP0_DP_VID_M 0x4aaa +#define CAR_mmDP1_DP_VID_M 0x4baa +#define CAR_mmDP2_DP_VID_M 0x4caa +#define CAR_mmDP3_DP_VID_M 0x4daa +#define CAR_mmDP4_DP_VID_M 0x4eaa +#define CAR_mmDP5_DP_VID_M 0x4faa +#define CAR_mmDP6_DP_VID_M 0x54aa +#define CAR_mmDP7_DP_VID_M 0x56aa +#define CAR_mmDP8_DP_VID_M 0x57aa +#define CAR_mmDP_LINK_FRAMING_CNTL 0x4aab +#define CAR_mmDP0_DP_LINK_FRAMING_CNTL 0x4aab +#define CAR_mmDP1_DP_LINK_FRAMING_CNTL 0x4bab +#define CAR_mmDP2_DP_LINK_FRAMING_CNTL 0x4cab +#define CAR_mmDP3_DP_LINK_FRAMING_CNTL 0x4dab +#define CAR_mmDP4_DP_LINK_FRAMING_CNTL 0x4eab +#define CAR_mmDP5_DP_LINK_FRAMING_CNTL 0x4fab +#define CAR_mmDP6_DP_LINK_FRAMING_CNTL 0x54ab +#define CAR_mmDP7_DP_LINK_FRAMING_CNTL 0x56ab +#define CAR_mmDP8_DP_LINK_FRAMING_CNTL 0x57ab +#define CAR_mmDP_HBR2_EYE_PATTERN 0x4aac +#define CAR_mmDP0_DP_HBR2_EYE_PATTERN 0x4aac +#define CAR_mmDP1_DP_HBR2_EYE_PATTERN 0x4bac +#define CAR_mmDP2_DP_HBR2_EYE_PATTERN 0x4cac +#define CAR_mmDP3_DP_HBR2_EYE_PATTERN 0x4dac +#define CAR_mmDP4_DP_HBR2_EYE_PATTERN 0x4eac +#define CAR_mmDP5_DP_HBR2_EYE_PATTERN 0x4fac +#define CAR_mmDP6_DP_HBR2_EYE_PATTERN 0x54ac +#define CAR_mmDP7_DP_HBR2_EYE_PATTERN 0x56ac +#define CAR_mmDP8_DP_HBR2_EYE_PATTERN 0x57ac +#define CAR_mmDP_VID_MSA_VBID 0x4aad +#define CAR_mmDP0_DP_VID_MSA_VBID 0x4aad +#define CAR_mmDP1_DP_VID_MSA_VBID 0x4bad +#define CAR_mmDP2_DP_VID_MSA_VBID 0x4cad +#define CAR_mmDP3_DP_VID_MSA_VBID 0x4dad +#define CAR_mmDP4_DP_VID_MSA_VBID 0x4ead +#define CAR_mmDP5_DP_VID_MSA_VBID 0x4fad +#define CAR_mmDP6_DP_VID_MSA_VBID 0x54ad +#define CAR_mmDP7_DP_VID_MSA_VBID 0x56ad +#define CAR_mmDP8_DP_VID_MSA_VBID 0x57ad +#define CAR_mmDP_VID_INTERRUPT_CNTL 0x4aae +#define CAR_mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae +#define CAR_mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae +#define CAR_mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae +#define CAR_mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae +#define CAR_mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae +#define CAR_mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae +#define CAR_mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae +#define CAR_mmDP7_DP_VID_INTERRUPT_CNTL 0x56ae +#define CAR_mmDP8_DP_VID_INTERRUPT_CNTL 0x57ae +#define CAR_mmDP_DPHY_CNTL 0x4aaf +#define CAR_mmDP0_DP_DPHY_CNTL 0x4aaf +#define CAR_mmDP1_DP_DPHY_CNTL 0x4baf +#define CAR_mmDP2_DP_DPHY_CNTL 0x4caf +#define CAR_mmDP3_DP_DPHY_CNTL 0x4daf +#define CAR_mmDP4_DP_DPHY_CNTL 0x4eaf +#define CAR_mmDP5_DP_DPHY_CNTL 0x4faf +#define CAR_mmDP6_DP_DPHY_CNTL 0x54af +#define CAR_mmDP7_DP_DPHY_CNTL 0x56af +#define CAR_mmDP8_DP_DPHY_CNTL 0x57af +#define CAR_mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define CAR_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define CAR_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 +#define CAR_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 +#define CAR_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 +#define CAR_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 +#define CAR_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 +#define CAR_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 +#define CAR_mmDP7_DP_DPHY_TRAINING_PATTERN_SEL 0x56b0 +#define CAR_mmDP8_DP_DPHY_TRAINING_PATTERN_SEL 0x57b0 +#define CAR_mmDP_DPHY_SYM0 0x4ab1 +#define CAR_mmDP0_DP_DPHY_SYM0 0x4ab1 +#define CAR_mmDP1_DP_DPHY_SYM0 0x4bb1 +#define CAR_mmDP2_DP_DPHY_SYM0 0x4cb1 +#define CAR_mmDP3_DP_DPHY_SYM0 0x4db1 +#define CAR_mmDP4_DP_DPHY_SYM0 0x4eb1 +#define CAR_mmDP5_DP_DPHY_SYM0 0x4fb1 +#define CAR_mmDP6_DP_DPHY_SYM0 0x54b1 +#define CAR_mmDP7_DP_DPHY_SYM0 0x56b1 +#define CAR_mmDP8_DP_DPHY_SYM0 0x57b1 +#define CAR_mmDP_DPHY_SYM1 0x4ab2 +#define CAR_mmDP0_DP_DPHY_SYM1 0x4ab2 +#define CAR_mmDP1_DP_DPHY_SYM1 0x4bb2 +#define CAR_mmDP2_DP_DPHY_SYM1 0x4cb2 +#define CAR_mmDP3_DP_DPHY_SYM1 0x4db2 +#define CAR_mmDP4_DP_DPHY_SYM1 0x4eb2 +#define CAR_mmDP5_DP_DPHY_SYM1 0x4fb2 +#define CAR_mmDP6_DP_DPHY_SYM1 0x54b2 +#define CAR_mmDP7_DP_DPHY_SYM1 0x56b2 +#define CAR_mmDP8_DP_DPHY_SYM1 0x57b2 +#define CAR_mmDP_DPHY_SYM2 0x4ab3 +#define CAR_mmDP0_DP_DPHY_SYM2 0x4ab3 +#define CAR_mmDP1_DP_DPHY_SYM2 0x4bb3 +#define CAR_mmDP2_DP_DPHY_SYM2 0x4cb3 +#define CAR_mmDP3_DP_DPHY_SYM2 0x4db3 +#define CAR_mmDP4_DP_DPHY_SYM2 0x4eb3 +#define CAR_mmDP5_DP_DPHY_SYM2 0x4fb3 +#define CAR_mmDP6_DP_DPHY_SYM2 0x54b3 +#define CAR_mmDP7_DP_DPHY_SYM2 0x56b3 +#define CAR_mmDP8_DP_DPHY_SYM2 0x57b3 +#define CAR_mmDP_DPHY_8B10B_CNTL 0x4ab4 +#define CAR_mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 +#define CAR_mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 +#define CAR_mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 +#define CAR_mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 +#define CAR_mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 +#define CAR_mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 +#define CAR_mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 +#define CAR_mmDP7_DP_DPHY_8B10B_CNTL 0x56b4 +#define CAR_mmDP8_DP_DPHY_8B10B_CNTL 0x57b4 +#define CAR_mmDP_DPHY_PRBS_CNTL 0x4ab5 +#define CAR_mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 +#define CAR_mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 +#define CAR_mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 +#define CAR_mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 +#define CAR_mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 +#define CAR_mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 +#define CAR_mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 +#define CAR_mmDP7_DP_DPHY_PRBS_CNTL 0x56b5 +#define CAR_mmDP8_DP_DPHY_PRBS_CNTL 0x57b5 +#define CAR_mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define CAR_mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define CAR_mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc +#define CAR_mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc +#define CAR_mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc +#define CAR_mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc +#define CAR_mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc +#define CAR_mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc +#define CAR_mmDP7_DP_DPHY_BS_SR_SWAP_CNTL 0x56dc +#define CAR_mmDP8_DP_DPHY_BS_SR_SWAP_CNTL 0x57dc +#define CAR_mmDP_DPHY_CRC_EN 0x4ab7 +#define CAR_mmDP0_DP_DPHY_CRC_EN 0x4ab7 +#define CAR_mmDP1_DP_DPHY_CRC_EN 0x4bb7 +#define CAR_mmDP2_DP_DPHY_CRC_EN 0x4cb7 +#define CAR_mmDP3_DP_DPHY_CRC_EN 0x4db7 +#define CAR_mmDP4_DP_DPHY_CRC_EN 0x4eb7 +#define CAR_mmDP5_DP_DPHY_CRC_EN 0x4fb7 +#define CAR_mmDP6_DP_DPHY_CRC_EN 0x54b7 +#define CAR_mmDP7_DP_DPHY_CRC_EN 0x56b7 +#define CAR_mmDP8_DP_DPHY_CRC_EN 0x57b7 +#define CAR_mmDP_DPHY_CRC_CNTL 0x4ab8 +#define CAR_mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 +#define CAR_mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 +#define CAR_mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 +#define CAR_mmDP3_DP_DPHY_CRC_CNTL 0x4db8 +#define CAR_mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 +#define CAR_mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 +#define CAR_mmDP6_DP_DPHY_CRC_CNTL 0x54b8 +#define CAR_mmDP7_DP_DPHY_CRC_CNTL 0x56b8 +#define CAR_mmDP8_DP_DPHY_CRC_CNTL 0x57b8 +#define CAR_mmDP_DPHY_CRC_RESULT 0x4ab9 +#define CAR_mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 +#define CAR_mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 +#define CAR_mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 +#define CAR_mmDP3_DP_DPHY_CRC_RESULT 0x4db9 +#define CAR_mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 +#define CAR_mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 +#define CAR_mmDP6_DP_DPHY_CRC_RESULT 0x54b9 +#define CAR_mmDP7_DP_DPHY_CRC_RESULT 0x56b9 +#define CAR_mmDP8_DP_DPHY_CRC_RESULT 0x57b9 +#define CAR_mmDP_DPHY_CRC_MST_CNTL 0x4aba +#define CAR_mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba +#define CAR_mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba +#define CAR_mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba +#define CAR_mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba +#define CAR_mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba +#define CAR_mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba +#define CAR_mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba +#define CAR_mmDP7_DP_DPHY_CRC_MST_CNTL 0x56ba +#define CAR_mmDP8_DP_DPHY_CRC_MST_CNTL 0x57ba +#define CAR_mmDP_DPHY_CRC_MST_STATUS 0x4abb +#define CAR_mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb +#define CAR_mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb +#define CAR_mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb +#define CAR_mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb +#define CAR_mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb +#define CAR_mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb +#define CAR_mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb +#define CAR_mmDP7_DP_DPHY_CRC_MST_STATUS 0x56bb +#define CAR_mmDP8_DP_DPHY_CRC_MST_STATUS 0x57bb +#define CAR_mmDP_DPHY_FAST_TRAINING 0x4abc +#define CAR_mmDP0_DP_DPHY_FAST_TRAINING 0x4abc +#define CAR_mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc +#define CAR_mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc +#define CAR_mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc +#define CAR_mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc +#define CAR_mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc +#define CAR_mmDP6_DP_DPHY_FAST_TRAINING 0x54bc +#define CAR_mmDP7_DP_DPHY_FAST_TRAINING 0x56bc +#define CAR_mmDP8_DP_DPHY_FAST_TRAINING 0x57bc +#define CAR_mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define CAR_mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define CAR_mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd +#define CAR_mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd +#define CAR_mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd +#define CAR_mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd +#define CAR_mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd +#define CAR_mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd +#define CAR_mmDP7_DP_DPHY_FAST_TRAINING_STATUS 0x56bd +#define CAR_mmDP8_DP_DPHY_FAST_TRAINING_STATUS 0x57bd +#define CAR_mmDP_DPHY_HBR2_PATTERN_CONTROL 0x4add +#define CAR_mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x4add +#define CAR_mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x4bdd +#define CAR_mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x4cdd +#define CAR_mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x4ddd +#define CAR_mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x4edd +#define CAR_mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x4fdd +#define CAR_mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x54dd +#define CAR_mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL 0x56dd +#define CAR_mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL 0x57dd +#define CAR_mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define CAR_mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define CAR_mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe +#define CAR_mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe +#define CAR_mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe +#define CAR_mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe +#define CAR_mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe +#define CAR_mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be +#define CAR_mmDP7_DP_MSA_V_TIMING_OVERRIDE1 0x56be +#define CAR_mmDP8_DP_MSA_V_TIMING_OVERRIDE1 0x57be +#define CAR_mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define CAR_mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define CAR_mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf +#define CAR_mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf +#define CAR_mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf +#define CAR_mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf +#define CAR_mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf +#define CAR_mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf +#define CAR_mmDP7_DP_MSA_V_TIMING_OVERRIDE2 0x56bf +#define CAR_mmDP8_DP_MSA_V_TIMING_OVERRIDE2 0x57bf +#define CAR_mmDP_SEC_CNTL 0x4ac3 +#define CAR_mmDP0_DP_SEC_CNTL 0x4ac3 +#define CAR_mmDP1_DP_SEC_CNTL 0x4bc3 +#define CAR_mmDP2_DP_SEC_CNTL 0x4cc3 +#define CAR_mmDP3_DP_SEC_CNTL 0x4dc3 +#define CAR_mmDP4_DP_SEC_CNTL 0x4ec3 +#define CAR_mmDP5_DP_SEC_CNTL 0x4fc3 +#define CAR_mmDP6_DP_SEC_CNTL 0x54c3 +#define CAR_mmDP7_DP_SEC_CNTL 0x56c3 +#define CAR_mmDP8_DP_SEC_CNTL 0x57c3 +#define CAR_mmDP_SEC_CNTL1 0x4ac4 +#define CAR_mmDP0_DP_SEC_CNTL1 0x4ac4 +#define CAR_mmDP1_DP_SEC_CNTL1 0x4bc4 +#define CAR_mmDP2_DP_SEC_CNTL1 0x4cc4 +#define CAR_mmDP3_DP_SEC_CNTL1 0x4dc4 +#define CAR_mmDP4_DP_SEC_CNTL1 0x4ec4 +#define CAR_mmDP5_DP_SEC_CNTL1 0x4fc4 +#define CAR_mmDP6_DP_SEC_CNTL1 0x54c4 +#define CAR_mmDP7_DP_SEC_CNTL1 0x56c4 +#define CAR_mmDP8_DP_SEC_CNTL1 0x57c4 +#define CAR_mmDP_SEC_FRAMING1 0x4ac5 +#define CAR_mmDP0_DP_SEC_FRAMING1 0x4ac5 +#define CAR_mmDP1_DP_SEC_FRAMING1 0x4bc5 +#define CAR_mmDP2_DP_SEC_FRAMING1 0x4cc5 +#define CAR_mmDP3_DP_SEC_FRAMING1 0x4dc5 +#define CAR_mmDP4_DP_SEC_FRAMING1 0x4ec5 +#define CAR_mmDP5_DP_SEC_FRAMING1 0x4fc5 +#define CAR_mmDP6_DP_SEC_FRAMING1 0x54c5 +#define CAR_mmDP7_DP_SEC_FRAMING1 0x56c5 +#define CAR_mmDP8_DP_SEC_FRAMING1 0x57c5 +#define CAR_mmDP_SEC_FRAMING2 0x4ac6 +#define CAR_mmDP0_DP_SEC_FRAMING2 0x4ac6 +#define CAR_mmDP1_DP_SEC_FRAMING2 0x4bc6 +#define CAR_mmDP2_DP_SEC_FRAMING2 0x4cc6 +#define CAR_mmDP3_DP_SEC_FRAMING2 0x4dc6 +#define CAR_mmDP4_DP_SEC_FRAMING2 0x4ec6 +#define CAR_mmDP5_DP_SEC_FRAMING2 0x4fc6 +#define CAR_mmDP6_DP_SEC_FRAMING2 0x54c6 +#define CAR_mmDP7_DP_SEC_FRAMING2 0x56c6 +#define CAR_mmDP8_DP_SEC_FRAMING2 0x57c6 +#define CAR_mmDP_SEC_FRAMING3 0x4ac7 +#define CAR_mmDP0_DP_SEC_FRAMING3 0x4ac7 +#define CAR_mmDP1_DP_SEC_FRAMING3 0x4bc7 +#define CAR_mmDP2_DP_SEC_FRAMING3 0x4cc7 +#define CAR_mmDP3_DP_SEC_FRAMING3 0x4dc7 +#define CAR_mmDP4_DP_SEC_FRAMING3 0x4ec7 +#define CAR_mmDP5_DP_SEC_FRAMING3 0x4fc7 +#define CAR_mmDP6_DP_SEC_FRAMING3 0x54c7 +#define CAR_mmDP7_DP_SEC_FRAMING3 0x56c7 +#define CAR_mmDP8_DP_SEC_FRAMING3 0x57c7 +#define CAR_mmDP_SEC_FRAMING4 0x4ac8 +#define CAR_mmDP0_DP_SEC_FRAMING4 0x4ac8 +#define CAR_mmDP1_DP_SEC_FRAMING4 0x4bc8 +#define CAR_mmDP2_DP_SEC_FRAMING4 0x4cc8 +#define CAR_mmDP3_DP_SEC_FRAMING4 0x4dc8 +#define CAR_mmDP4_DP_SEC_FRAMING4 0x4ec8 +#define CAR_mmDP5_DP_SEC_FRAMING4 0x4fc8 +#define CAR_mmDP6_DP_SEC_FRAMING4 0x54c8 +#define CAR_mmDP7_DP_SEC_FRAMING4 0x56c8 +#define CAR_mmDP8_DP_SEC_FRAMING4 0x57c8 +#define CAR_mmDP_SEC_AUD_N 0x4ac9 +#define CAR_mmDP0_DP_SEC_AUD_N 0x4ac9 +#define CAR_mmDP1_DP_SEC_AUD_N 0x4bc9 +#define CAR_mmDP2_DP_SEC_AUD_N 0x4cc9 +#define CAR_mmDP3_DP_SEC_AUD_N 0x4dc9 +#define CAR_mmDP4_DP_SEC_AUD_N 0x4ec9 +#define CAR_mmDP5_DP_SEC_AUD_N 0x4fc9 +#define CAR_mmDP6_DP_SEC_AUD_N 0x54c9 +#define CAR_mmDP7_DP_SEC_AUD_N 0x56c9 +#define CAR_mmDP8_DP_SEC_AUD_N 0x57c9 +#define CAR_mmDP_SEC_AUD_N_READBACK 0x4aca +#define CAR_mmDP0_DP_SEC_AUD_N_READBACK 0x4aca +#define CAR_mmDP1_DP_SEC_AUD_N_READBACK 0x4bca +#define CAR_mmDP2_DP_SEC_AUD_N_READBACK 0x4cca +#define CAR_mmDP3_DP_SEC_AUD_N_READBACK 0x4dca +#define CAR_mmDP4_DP_SEC_AUD_N_READBACK 0x4eca +#define CAR_mmDP5_DP_SEC_AUD_N_READBACK 0x4fca +#define CAR_mmDP6_DP_SEC_AUD_N_READBACK 0x54ca +#define CAR_mmDP7_DP_SEC_AUD_N_READBACK 0x56ca +#define CAR_mmDP8_DP_SEC_AUD_N_READBACK 0x57ca +#define CAR_mmDP_SEC_AUD_M 0x4acb +#define CAR_mmDP0_DP_SEC_AUD_M 0x4acb +#define CAR_mmDP1_DP_SEC_AUD_M 0x4bcb +#define CAR_mmDP2_DP_SEC_AUD_M 0x4ccb +#define CAR_mmDP3_DP_SEC_AUD_M 0x4dcb +#define CAR_mmDP4_DP_SEC_AUD_M 0x4ecb +#define CAR_mmDP5_DP_SEC_AUD_M 0x4fcb +#define CAR_mmDP6_DP_SEC_AUD_M 0x54cb +#define CAR_mmDP7_DP_SEC_AUD_M 0x56cb +#define CAR_mmDP8_DP_SEC_AUD_M 0x57cb +#define CAR_mmDP_SEC_AUD_M_READBACK 0x4acc +#define CAR_mmDP0_DP_SEC_AUD_M_READBACK 0x4acc +#define CAR_mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc +#define CAR_mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc +#define CAR_mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc +#define CAR_mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc +#define CAR_mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc +#define CAR_mmDP6_DP_SEC_AUD_M_READBACK 0x54cc +#define CAR_mmDP7_DP_SEC_AUD_M_READBACK 0x56cc +#define CAR_mmDP8_DP_SEC_AUD_M_READBACK 0x57cc +#define CAR_mmDP_SEC_TIMESTAMP 0x4acd +#define CAR_mmDP0_DP_SEC_TIMESTAMP 0x4acd +#define CAR_mmDP1_DP_SEC_TIMESTAMP 0x4bcd +#define CAR_mmDP2_DP_SEC_TIMESTAMP 0x4ccd +#define CAR_mmDP3_DP_SEC_TIMESTAMP 0x4dcd +#define CAR_mmDP4_DP_SEC_TIMESTAMP 0x4ecd +#define CAR_mmDP5_DP_SEC_TIMESTAMP 0x4fcd +#define CAR_mmDP6_DP_SEC_TIMESTAMP 0x54cd +#define CAR_mmDP7_DP_SEC_TIMESTAMP 0x56cd +#define CAR_mmDP8_DP_SEC_TIMESTAMP 0x57cd +#define CAR_mmDP_SEC_PACKET_CNTL 0x4ace +#define CAR_mmDP0_DP_SEC_PACKET_CNTL 0x4ace +#define CAR_mmDP1_DP_SEC_PACKET_CNTL 0x4bce +#define CAR_mmDP2_DP_SEC_PACKET_CNTL 0x4cce +#define CAR_mmDP3_DP_SEC_PACKET_CNTL 0x4dce +#define CAR_mmDP4_DP_SEC_PACKET_CNTL 0x4ece +#define CAR_mmDP5_DP_SEC_PACKET_CNTL 0x4fce +#define CAR_mmDP6_DP_SEC_PACKET_CNTL 0x54ce +#define CAR_mmDP7_DP_SEC_PACKET_CNTL 0x56ce +#define CAR_mmDP8_DP_SEC_PACKET_CNTL 0x57ce +#define CAR_mmDP_MSE_RATE_CNTL 0x4acf +#define CAR_mmDP0_DP_MSE_RATE_CNTL 0x4acf +#define CAR_mmDP1_DP_MSE_RATE_CNTL 0x4bcf +#define CAR_mmDP2_DP_MSE_RATE_CNTL 0x4ccf +#define CAR_mmDP3_DP_MSE_RATE_CNTL 0x4dcf +#define CAR_mmDP4_DP_MSE_RATE_CNTL 0x4ecf +#define CAR_mmDP5_DP_MSE_RATE_CNTL 0x4fcf +#define CAR_mmDP6_DP_MSE_RATE_CNTL 0x54cf +#define CAR_mmDP7_DP_MSE_RATE_CNTL 0x56cf +#define CAR_mmDP8_DP_MSE_RATE_CNTL 0x57cf +#define CAR_mmDP_MSE_RATE_UPDATE 0x4ad1 +#define CAR_mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 +#define CAR_mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 +#define CAR_mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 +#define CAR_mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 +#define CAR_mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 +#define CAR_mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 +#define CAR_mmDP6_DP_MSE_RATE_UPDATE 0x54d1 +#define CAR_mmDP7_DP_MSE_RATE_UPDATE 0x56d1 +#define CAR_mmDP8_DP_MSE_RATE_UPDATE 0x57d1 +#define CAR_mmDP_MSE_SAT0 0x4ad2 +#define CAR_mmDP0_DP_MSE_SAT0 0x4ad2 +#define CAR_mmDP1_DP_MSE_SAT0 0x4bd2 +#define CAR_mmDP2_DP_MSE_SAT0 0x4cd2 +#define CAR_mmDP3_DP_MSE_SAT0 0x4dd2 +#define CAR_mmDP4_DP_MSE_SAT0 0x4ed2 +#define CAR_mmDP5_DP_MSE_SAT0 0x4fd2 +#define CAR_mmDP6_DP_MSE_SAT0 0x54d2 +#define CAR_mmDP7_DP_MSE_SAT0 0x56d2 +#define CAR_mmDP8_DP_MSE_SAT0 0x57d2 +#define CAR_mmDP_MSE_SAT1 0x4ad3 +#define CAR_mmDP0_DP_MSE_SAT1 0x4ad3 +#define CAR_mmDP1_DP_MSE_SAT1 0x4bd3 +#define CAR_mmDP2_DP_MSE_SAT1 0x4cd3 +#define CAR_mmDP3_DP_MSE_SAT1 0x4dd3 +#define CAR_mmDP4_DP_MSE_SAT1 0x4ed3 +#define CAR_mmDP5_DP_MSE_SAT1 0x4fd3 +#define CAR_mmDP6_DP_MSE_SAT1 0x54d3 +#define CAR_mmDP7_DP_MSE_SAT1 0x56d3 +#define CAR_mmDP8_DP_MSE_SAT1 0x57d3 +#define CAR_mmDP_MSE_SAT2 0x4ad4 +#define CAR_mmDP0_DP_MSE_SAT2 0x4ad4 +#define CAR_mmDP1_DP_MSE_SAT2 0x4bd4 +#define CAR_mmDP2_DP_MSE_SAT2 0x4cd4 +#define CAR_mmDP3_DP_MSE_SAT2 0x4dd4 +#define CAR_mmDP4_DP_MSE_SAT2 0x4ed4 +#define CAR_mmDP5_DP_MSE_SAT2 0x4fd4 +#define CAR_mmDP6_DP_MSE_SAT2 0x54d4 +#define CAR_mmDP7_DP_MSE_SAT2 0x56d4 +#define CAR_mmDP8_DP_MSE_SAT2 0x57d4 +#define CAR_mmDP_MSE_SAT_UPDATE 0x4ad5 +#define CAR_mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 +#define CAR_mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 +#define CAR_mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 +#define CAR_mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 +#define CAR_mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 +#define CAR_mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 +#define CAR_mmDP6_DP_MSE_SAT_UPDATE 0x54d5 +#define CAR_mmDP7_DP_MSE_SAT_UPDATE 0x56d5 +#define CAR_mmDP8_DP_MSE_SAT_UPDATE 0x57d5 +#define CAR_mmDP_MSE_LINK_TIMING 0x4ad6 +#define CAR_mmDP0_DP_MSE_LINK_TIMING 0x4ad6 +#define CAR_mmDP1_DP_MSE_LINK_TIMING 0x4bd6 +#define CAR_mmDP2_DP_MSE_LINK_TIMING 0x4cd6 +#define CAR_mmDP3_DP_MSE_LINK_TIMING 0x4dd6 +#define CAR_mmDP4_DP_MSE_LINK_TIMING 0x4ed6 +#define CAR_mmDP5_DP_MSE_LINK_TIMING 0x4fd6 +#define CAR_mmDP6_DP_MSE_LINK_TIMING 0x54d6 +#define CAR_mmDP7_DP_MSE_LINK_TIMING 0x56d6 +#define CAR_mmDP8_DP_MSE_LINK_TIMING 0x57d6 +#define CAR_mmDP_MSE_MISC_CNTL 0x4ad7 +#define CAR_mmDP0_DP_MSE_MISC_CNTL 0x4ad7 +#define CAR_mmDP1_DP_MSE_MISC_CNTL 0x4bd7 +#define CAR_mmDP2_DP_MSE_MISC_CNTL 0x4cd7 +#define CAR_mmDP3_DP_MSE_MISC_CNTL 0x4dd7 +#define CAR_mmDP4_DP_MSE_MISC_CNTL 0x4ed7 +#define CAR_mmDP5_DP_MSE_MISC_CNTL 0x4fd7 +#define CAR_mmDP6_DP_MSE_MISC_CNTL 0x54d7 +#define CAR_mmDP7_DP_MSE_MISC_CNTL 0x56d7 +#define CAR_mmDP8_DP_MSE_MISC_CNTL 0x57d7 +#define CAR_mmDP_TEST_DEBUG_INDEX 0x4ad8 +#define CAR_mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 +#define CAR_mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 +#define CAR_mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 +#define CAR_mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 +#define CAR_mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 +#define CAR_mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 +#define CAR_mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 +#define CAR_mmDP7_DP_TEST_DEBUG_INDEX 0x56d8 +#define CAR_mmDP8_DP_TEST_DEBUG_INDEX 0x57d8 +#define CAR_mmDP_TEST_DEBUG_DATA 0x4ad9 +#define CAR_mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 +#define CAR_mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 +#define CAR_mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 +#define CAR_mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 +#define CAR_mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 +#define CAR_mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 +#define CAR_mmDP6_DP_TEST_DEBUG_DATA 0x54d9 +#define CAR_mmDP7_DP_TEST_DEBUG_DATA 0x56d9 +#define CAR_mmDP8_DP_TEST_DEBUG_DATA 0x57d9 +#define CAR_mmDP_FE_TEST_DEBUG_INDEX 0x4ada +#define CAR_mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada +#define CAR_mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda +#define CAR_mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda +#define CAR_mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda +#define CAR_mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda +#define CAR_mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda +#define CAR_mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da +#define CAR_mmDP7_DP_FE_TEST_DEBUG_INDEX 0x56da +#define CAR_mmDP8_DP_FE_TEST_DEBUG_INDEX 0x57da +#define CAR_mmDP_FE_TEST_DEBUG_DATA 0x4adb +#define CAR_mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb +#define CAR_mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb +#define CAR_mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb +#define CAR_mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb +#define CAR_mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb +#define CAR_mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb +#define CAR_mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db +#define CAR_mmDP7_DP_FE_TEST_DEBUG_DATA 0x56db +#define CAR_mmDP8_DP_FE_TEST_DEBUG_DATA 0x57db +#define CAR_mmAUX_CONTROL 0x5c00 +#define CAR_mmDP_AUX0_AUX_CONTROL 0x5c00 +#define CAR_mmDP_AUX1_AUX_CONTROL 0x5c1c +#define CAR_mmDP_AUX2_AUX_CONTROL 0x5c38 +#define CAR_mmDP_AUX3_AUX_CONTROL 0x5c54 +#define CAR_mmDP_AUX4_AUX_CONTROL 0x5c70 +#define CAR_mmDP_AUX5_AUX_CONTROL 0x5c8c +#define CAR_mmAUX_SW_CONTROL 0x5c01 +#define CAR_mmDP_AUX0_AUX_SW_CONTROL 0x5c01 +#define CAR_mmDP_AUX1_AUX_SW_CONTROL 0x5c1d +#define CAR_mmDP_AUX2_AUX_SW_CONTROL 0x5c39 +#define CAR_mmDP_AUX3_AUX_SW_CONTROL 0x5c55 +#define CAR_mmDP_AUX4_AUX_SW_CONTROL 0x5c71 +#define CAR_mmDP_AUX5_AUX_SW_CONTROL 0x5c8d +#define CAR_mmAUX_ARB_CONTROL 0x5c02 +#define CAR_mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 +#define CAR_mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e +#define CAR_mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a +#define CAR_mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 +#define CAR_mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 +#define CAR_mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e +#define CAR_mmAUX_INTERRUPT_CONTROL 0x5c03 +#define CAR_mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 +#define CAR_mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f +#define CAR_mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b +#define CAR_mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 +#define CAR_mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 +#define CAR_mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f +#define CAR_mmAUX_SW_STATUS 0x5c04 +#define CAR_mmDP_AUX0_AUX_SW_STATUS 0x5c04 +#define CAR_mmDP_AUX1_AUX_SW_STATUS 0x5c20 +#define CAR_mmDP_AUX2_AUX_SW_STATUS 0x5c3c +#define CAR_mmDP_AUX3_AUX_SW_STATUS 0x5c58 +#define CAR_mmDP_AUX4_AUX_SW_STATUS 0x5c74 +#define CAR_mmDP_AUX5_AUX_SW_STATUS 0x5c90 +#define CAR_mmAUX_LS_STATUS 0x5c05 +#define CAR_mmDP_AUX0_AUX_LS_STATUS 0x5c05 +#define CAR_mmDP_AUX1_AUX_LS_STATUS 0x5c21 +#define CAR_mmDP_AUX2_AUX_LS_STATUS 0x5c3d +#define CAR_mmDP_AUX3_AUX_LS_STATUS 0x5c59 +#define CAR_mmDP_AUX4_AUX_LS_STATUS 0x5c75 +#define CAR_mmDP_AUX5_AUX_LS_STATUS 0x5c91 +#define CAR_mmAUX_SW_DATA 0x5c06 +#define CAR_mmDP_AUX0_AUX_SW_DATA 0x5c06 +#define CAR_mmDP_AUX1_AUX_SW_DATA 0x5c22 +#define CAR_mmDP_AUX2_AUX_SW_DATA 0x5c3e +#define CAR_mmDP_AUX3_AUX_SW_DATA 0x5c5a +#define CAR_mmDP_AUX4_AUX_SW_DATA 0x5c76 +#define CAR_mmDP_AUX5_AUX_SW_DATA 0x5c92 +#define CAR_mmAUX_LS_DATA 0x5c07 +#define CAR_mmDP_AUX0_AUX_LS_DATA 0x5c07 +#define CAR_mmDP_AUX1_AUX_LS_DATA 0x5c23 +#define CAR_mmDP_AUX2_AUX_LS_DATA 0x5c3f +#define CAR_mmDP_AUX3_AUX_LS_DATA 0x5c5b +#define CAR_mmDP_AUX4_AUX_LS_DATA 0x5c77 +#define CAR_mmDP_AUX5_AUX_LS_DATA 0x5c93 +#define CAR_mmAUX_DPHY_TX_REF_CONTROL 0x5c08 +#define CAR_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 +#define CAR_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 +#define CAR_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 +#define CAR_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c +#define CAR_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 +#define CAR_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 +#define CAR_mmAUX_DPHY_TX_CONTROL 0x5c09 +#define CAR_mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 +#define CAR_mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 +#define CAR_mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 +#define CAR_mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d +#define CAR_mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 +#define CAR_mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 +#define CAR_mmAUX_DPHY_RX_CONTROL0 0x5c0a +#define CAR_mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a +#define CAR_mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 +#define CAR_mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 +#define CAR_mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e +#define CAR_mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a +#define CAR_mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 +#define CAR_mmAUX_DPHY_RX_CONTROL1 0x5c0b +#define CAR_mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b +#define CAR_mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 +#define CAR_mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 +#define CAR_mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f +#define CAR_mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b +#define CAR_mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 +#define CAR_mmAUX_DPHY_TX_STATUS 0x5c0c +#define CAR_mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c +#define CAR_mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 +#define CAR_mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 +#define CAR_mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 +#define CAR_mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c +#define CAR_mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 +#define CAR_mmAUX_DPHY_RX_STATUS 0x5c0d +#define CAR_mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d +#define CAR_mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 +#define CAR_mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 +#define CAR_mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 +#define CAR_mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d +#define CAR_mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 +#define CAR_mmAUX_GTC_SYNC_CONTROL 0x5c0e +#define CAR_mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e +#define CAR_mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a +#define CAR_mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46 +#define CAR_mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62 +#define CAR_mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e +#define CAR_mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a +#define CAR_mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define CAR_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define CAR_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b +#define CAR_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 +#define CAR_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 +#define CAR_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f +#define CAR_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b +#define CAR_mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define CAR_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define CAR_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c +#define CAR_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 +#define CAR_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 +#define CAR_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 +#define CAR_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c +#define CAR_mmAUX_GTC_SYNC_STATUS 0x5c11 +#define CAR_mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 +#define CAR_mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d +#define CAR_mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 +#define CAR_mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 +#define CAR_mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 +#define CAR_mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d +#define CAR_mmAUX_GTC_SYNC_DATA 0x5c12 +#define CAR_mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12 +#define CAR_mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e +#define CAR_mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a +#define CAR_mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66 +#define CAR_mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82 +#define CAR_mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e +#define CAR_mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 +#define CAR_mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 +#define CAR_mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f +#define CAR_mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b +#define CAR_mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67 +#define CAR_mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83 +#define CAR_mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f +#define CAR_mmAUX_TEST_DEBUG_INDEX 0x5c14 +#define CAR_mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 +#define CAR_mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 +#define CAR_mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c +#define CAR_mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 +#define CAR_mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 +#define CAR_mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 +#define CAR_mmAUX_TEST_DEBUG_DATA 0x5c15 +#define CAR_mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 +#define CAR_mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 +#define CAR_mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d +#define CAR_mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 +#define CAR_mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 +#define CAR_mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 +#define CAR_ixDP_AUX_DEBUG_A 0x10 +#define CAR_ixDP_AUX_DEBUG_B 0x11 +#define CAR_ixDP_AUX_DEBUG_C 0x12 +#define CAR_ixDP_AUX_DEBUG_D 0x13 +#define CAR_ixDP_AUX_DEBUG_E 0x14 +#define CAR_ixDP_AUX_DEBUG_F 0x15 +#define CAR_ixDP_AUX_DEBUG_G 0x16 +#define CAR_ixDP_AUX_DEBUG_H 0x17 +#define CAR_ixDP_AUX_DEBUG_I 0x18 +#define CAR_ixDP_AUX_DEBUG_J 0x19 +#define CAR_ixDP_AUX_DEBUG_K 0x1a +#define CAR_ixDP_AUX_DEBUG_L 0x1b +#define CAR_ixDP_AUX_DEBUG_M 0x1c +#define CAR_ixDP_AUX_DEBUG_N 0x1d +#define CAR_ixDP_AUX_DEBUG_O 0x1e +#define CAR_ixDP_AUX_DEBUG_P 0x1f +#define CAR_ixDP_AUX_DEBUG_Q 0x20 +#define CAR_mmDVO_ENABLE 0x16a0 +#define CAR_mmDVO_SOURCE_SELECT 0x16a1 +#define CAR_mmDVO_OUTPUT 0x16a2 +#define CAR_mmDVO_CONTROL 0x16a3 +#define CAR_mmDVO_CRC_EN 0x16a4 +#define CAR_mmDVO_CRC2_SIG_MASK 0x16a5 +#define CAR_mmDVO_CRC2_SIG_RESULT 0x16a6 +#define CAR_mmDVO_FIFO_ERROR_STATUS 0x16a7 +#define CAR_mmDVO_TEST_DEBUG_INDEX 0x16a8 +#define CAR_mmDVO_TEST_DEBUG_DATA 0x16a9 +#define CAR_mmFBC_CNTL 0x280 +#define CAR_mmFBC_IDLE_MASK 0x281 +#define CAR_mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 +#define CAR_mmFBC_START_STOP_DELAY 0x283 +#define CAR_mmFBC_COMP_CNTL 0x284 +#define CAR_mmFBC_COMP_MODE 0x285 +#define CAR_mmFBC_DEBUG0 0x286 +#define CAR_mmFBC_DEBUG1 0x287 +#define CAR_mmFBC_DEBUG2 0x288 +#define CAR_mmFBC_IND_LUT0 0x289 +#define CAR_mmFBC_IND_LUT1 0x28a +#define CAR_mmFBC_IND_LUT2 0x28b +#define CAR_mmFBC_IND_LUT3 0x28c +#define CAR_mmFBC_IND_LUT4 0x28d +#define CAR_mmFBC_IND_LUT5 0x28e +#define CAR_mmFBC_IND_LUT6 0x28f +#define CAR_mmFBC_IND_LUT7 0x290 +#define CAR_mmFBC_IND_LUT8 0x291 +#define CAR_mmFBC_IND_LUT9 0x292 +#define CAR_mmFBC_IND_LUT10 0x293 +#define CAR_mmFBC_IND_LUT11 0x294 +#define CAR_mmFBC_IND_LUT12 0x295 +#define CAR_mmFBC_IND_LUT13 0x296 +#define CAR_mmFBC_IND_LUT14 0x297 +#define CAR_mmFBC_IND_LUT15 0x298 +#define CAR_mmFBC_CSM_REGION_OFFSET_01 0x299 +#define CAR_mmFBC_CSM_REGION_OFFSET_23 0x29a +#define CAR_mmFBC_CLIENT_REGION_MASK 0x29b +#define CAR_mmFBC_DEBUG_COMP 0x29c +#define CAR_mmFBC_DEBUG_CSR 0x29d +#define CAR_mmFBC_DEBUG_CSR_RDATA 0x29e +#define CAR_mmFBC_DEBUG_CSR_WDATA 0x29f +#define CAR_mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 +#define CAR_mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 +#define CAR_mmFBC_MISC 0x2a2 +#define CAR_mmFBC_STATUS 0x2a3 +#define CAR_mmFBC_TEST_DEBUG_INDEX 0x2a4 +#define CAR_mmFBC_TEST_DEBUG_DATA 0x2a5 +#define CAR_mmFMT_CLAMP_COMPONENT_R 0x1be8 +#define CAR_mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 +#define CAR_mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 +#define CAR_mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 +#define CAR_mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 +#define CAR_mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 +#define CAR_mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 +#define CAR_mmFMT_CLAMP_COMPONENT_G 0x1be9 +#define CAR_mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 +#define CAR_mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 +#define CAR_mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 +#define CAR_mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 +#define CAR_mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 +#define CAR_mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 +#define CAR_mmFMT_CLAMP_COMPONENT_B 0x1bea +#define CAR_mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea +#define CAR_mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea +#define CAR_mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea +#define CAR_mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea +#define CAR_mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea +#define CAR_mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea +#define CAR_mmFMT_DYNAMIC_EXP_CNTL 0x1bed +#define CAR_mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed +#define CAR_mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded +#define CAR_mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed +#define CAR_mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed +#define CAR_mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed +#define CAR_mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed +#define CAR_mmFMT_CONTROL 0x1bee +#define CAR_mmFMT0_FMT_CONTROL 0x1bee +#define CAR_mmFMT1_FMT_CONTROL 0x1dee +#define CAR_mmFMT2_FMT_CONTROL 0x1fee +#define CAR_mmFMT3_FMT_CONTROL 0x41ee +#define CAR_mmFMT4_FMT_CONTROL 0x43ee +#define CAR_mmFMT5_FMT_CONTROL 0x45ee +#define CAR_mmFMT_BIT_DEPTH_CONTROL 0x1bf2 +#define CAR_mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 +#define CAR_mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 +#define CAR_mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 +#define CAR_mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 +#define CAR_mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 +#define CAR_mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 +#define CAR_mmFMT_DITHER_RAND_R_SEED 0x1bf3 +#define CAR_mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 +#define CAR_mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 +#define CAR_mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 +#define CAR_mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 +#define CAR_mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 +#define CAR_mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 +#define CAR_mmFMT_DITHER_RAND_G_SEED 0x1bf4 +#define CAR_mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 +#define CAR_mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 +#define CAR_mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 +#define CAR_mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 +#define CAR_mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 +#define CAR_mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 +#define CAR_mmFMT_DITHER_RAND_B_SEED 0x1bf5 +#define CAR_mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 +#define CAR_mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 +#define CAR_mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 +#define CAR_mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 +#define CAR_mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 +#define CAR_mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 +#define CAR_mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define CAR_mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define CAR_mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 +#define CAR_mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 +#define CAR_mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 +#define CAR_mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 +#define CAR_mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 +#define CAR_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define CAR_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define CAR_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 +#define CAR_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 +#define CAR_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 +#define CAR_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 +#define CAR_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 +#define CAR_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define CAR_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define CAR_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 +#define CAR_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 +#define CAR_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 +#define CAR_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 +#define CAR_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 +#define CAR_mmFMT_CLAMP_CNTL 0x1bf9 +#define CAR_mmFMT0_FMT_CLAMP_CNTL 0x1bf9 +#define CAR_mmFMT1_FMT_CLAMP_CNTL 0x1df9 +#define CAR_mmFMT2_FMT_CLAMP_CNTL 0x1ff9 +#define CAR_mmFMT3_FMT_CLAMP_CNTL 0x41f9 +#define CAR_mmFMT4_FMT_CLAMP_CNTL 0x43f9 +#define CAR_mmFMT5_FMT_CLAMP_CNTL 0x45f9 +#define CAR_mmFMT_CRC_CNTL 0x1bfa +#define CAR_mmFMT0_FMT_CRC_CNTL 0x1bfa +#define CAR_mmFMT1_FMT_CRC_CNTL 0x1dfa +#define CAR_mmFMT2_FMT_CRC_CNTL 0x1ffa +#define CAR_mmFMT3_FMT_CRC_CNTL 0x41fa +#define CAR_mmFMT4_FMT_CRC_CNTL 0x43fa +#define CAR_mmFMT5_FMT_CRC_CNTL 0x45fa +#define CAR_mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define CAR_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define CAR_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb +#define CAR_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb +#define CAR_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb +#define CAR_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb +#define CAR_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb +#define CAR_mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define CAR_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define CAR_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc +#define CAR_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc +#define CAR_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc +#define CAR_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc +#define CAR_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc +#define CAR_mmFMT_CRC_SIG_RED_GREEN 0x1bfd +#define CAR_mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd +#define CAR_mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd +#define CAR_mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd +#define CAR_mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd +#define CAR_mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd +#define CAR_mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd +#define CAR_mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define CAR_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define CAR_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe +#define CAR_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe +#define CAR_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe +#define CAR_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe +#define CAR_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe +#define CAR_mmFMT_DEBUG_CNTL 0x1bff +#define CAR_mmFMT0_FMT_DEBUG_CNTL 0x1bff +#define CAR_mmFMT1_FMT_DEBUG_CNTL 0x1dff +#define CAR_mmFMT2_FMT_DEBUG_CNTL 0x1fff +#define CAR_mmFMT3_FMT_DEBUG_CNTL 0x41ff +#define CAR_mmFMT4_FMT_DEBUG_CNTL 0x43ff +#define CAR_mmFMT5_FMT_DEBUG_CNTL 0x45ff +#define CAR_mmFMT_TEST_DEBUG_INDEX 0x1beb +#define CAR_mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb +#define CAR_mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb +#define CAR_mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb +#define CAR_mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb +#define CAR_mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb +#define CAR_mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb +#define CAR_mmFMT_TEST_DEBUG_DATA 0x1bec +#define CAR_mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec +#define CAR_mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec +#define CAR_mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec +#define CAR_mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec +#define CAR_mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec +#define CAR_mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec +#define CAR_ixFMT_DEBUG0 0x1 +#define CAR_ixFMT_DEBUG1 0x2 +#define CAR_ixFMT_DEBUG2 0x3 +#define CAR_ixFMT_DEBUG_ID 0x0 +#define CAR_mmLB_DATA_FORMAT 0x1ac0 +#define CAR_mmLB0_LB_DATA_FORMAT 0x1ac0 +#define CAR_mmLB1_LB_DATA_FORMAT 0x1cc0 +#define CAR_mmLB2_LB_DATA_FORMAT 0x1ec0 +#define CAR_mmLB3_LB_DATA_FORMAT 0x40c0 +#define CAR_mmLB4_LB_DATA_FORMAT 0x42c0 +#define CAR_mmLB5_LB_DATA_FORMAT 0x44c0 +#define CAR_mmLB_MEMORY_CTRL 0x1ac1 +#define CAR_mmLB0_LB_MEMORY_CTRL 0x1ac1 +#define CAR_mmLB1_LB_MEMORY_CTRL 0x1cc1 +#define CAR_mmLB2_LB_MEMORY_CTRL 0x1ec1 +#define CAR_mmLB3_LB_MEMORY_CTRL 0x40c1 +#define CAR_mmLB4_LB_MEMORY_CTRL 0x42c1 +#define CAR_mmLB5_LB_MEMORY_CTRL 0x44c1 +#define CAR_mmLB_MEMORY_SIZE_STATUS 0x1ac2 +#define CAR_mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 +#define CAR_mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 +#define CAR_mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 +#define CAR_mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 +#define CAR_mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 +#define CAR_mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 +#define CAR_mmLB_DESKTOP_HEIGHT 0x1ac3 +#define CAR_mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 +#define CAR_mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 +#define CAR_mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 +#define CAR_mmLB3_LB_DESKTOP_HEIGHT 0x40c3 +#define CAR_mmLB4_LB_DESKTOP_HEIGHT 0x42c3 +#define CAR_mmLB5_LB_DESKTOP_HEIGHT 0x44c3 +#define CAR_mmLB_VLINE_START_END 0x1ac4 +#define CAR_mmLB0_LB_VLINE_START_END 0x1ac4 +#define CAR_mmLB1_LB_VLINE_START_END 0x1cc4 +#define CAR_mmLB2_LB_VLINE_START_END 0x1ec4 +#define CAR_mmLB3_LB_VLINE_START_END 0x40c4 +#define CAR_mmLB4_LB_VLINE_START_END 0x42c4 +#define CAR_mmLB5_LB_VLINE_START_END 0x44c4 +#define CAR_mmLB_VLINE2_START_END 0x1ac5 +#define CAR_mmLB0_LB_VLINE2_START_END 0x1ac5 +#define CAR_mmLB1_LB_VLINE2_START_END 0x1cc5 +#define CAR_mmLB2_LB_VLINE2_START_END 0x1ec5 +#define CAR_mmLB3_LB_VLINE2_START_END 0x40c5 +#define CAR_mmLB4_LB_VLINE2_START_END 0x42c5 +#define CAR_mmLB5_LB_VLINE2_START_END 0x44c5 +#define CAR_mmLB_V_COUNTER 0x1ac6 +#define CAR_mmLB0_LB_V_COUNTER 0x1ac6 +#define CAR_mmLB1_LB_V_COUNTER 0x1cc6 +#define CAR_mmLB2_LB_V_COUNTER 0x1ec6 +#define CAR_mmLB3_LB_V_COUNTER 0x40c6 +#define CAR_mmLB4_LB_V_COUNTER 0x42c6 +#define CAR_mmLB5_LB_V_COUNTER 0x44c6 +#define CAR_mmLB_SNAPSHOT_V_COUNTER 0x1ac7 +#define CAR_mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 +#define CAR_mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 +#define CAR_mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 +#define CAR_mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 +#define CAR_mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 +#define CAR_mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 +#define CAR_mmLB_INTERRUPT_MASK 0x1ac8 +#define CAR_mmLB0_LB_INTERRUPT_MASK 0x1ac8 +#define CAR_mmLB1_LB_INTERRUPT_MASK 0x1cc8 +#define CAR_mmLB2_LB_INTERRUPT_MASK 0x1ec8 +#define CAR_mmLB3_LB_INTERRUPT_MASK 0x40c8 +#define CAR_mmLB4_LB_INTERRUPT_MASK 0x42c8 +#define CAR_mmLB5_LB_INTERRUPT_MASK 0x44c8 +#define CAR_mmLB_VLINE_STATUS 0x1ac9 +#define CAR_mmLB0_LB_VLINE_STATUS 0x1ac9 +#define CAR_mmLB1_LB_VLINE_STATUS 0x1cc9 +#define CAR_mmLB2_LB_VLINE_STATUS 0x1ec9 +#define CAR_mmLB3_LB_VLINE_STATUS 0x40c9 +#define CAR_mmLB4_LB_VLINE_STATUS 0x42c9 +#define CAR_mmLB5_LB_VLINE_STATUS 0x44c9 +#define CAR_mmLB_VLINE2_STATUS 0x1aca +#define CAR_mmLB0_LB_VLINE2_STATUS 0x1aca +#define CAR_mmLB1_LB_VLINE2_STATUS 0x1cca +#define CAR_mmLB2_LB_VLINE2_STATUS 0x1eca +#define CAR_mmLB3_LB_VLINE2_STATUS 0x40ca +#define CAR_mmLB4_LB_VLINE2_STATUS 0x42ca +#define CAR_mmLB5_LB_VLINE2_STATUS 0x44ca +#define CAR_mmLB_VBLANK_STATUS 0x1acb +#define CAR_mmLB0_LB_VBLANK_STATUS 0x1acb +#define CAR_mmLB1_LB_VBLANK_STATUS 0x1ccb +#define CAR_mmLB2_LB_VBLANK_STATUS 0x1ecb +#define CAR_mmLB3_LB_VBLANK_STATUS 0x40cb +#define CAR_mmLB4_LB_VBLANK_STATUS 0x42cb +#define CAR_mmLB5_LB_VBLANK_STATUS 0x44cb +#define CAR_mmLB_SYNC_RESET_SEL 0x1acc +#define CAR_mmLB0_LB_SYNC_RESET_SEL 0x1acc +#define CAR_mmLB1_LB_SYNC_RESET_SEL 0x1ccc +#define CAR_mmLB2_LB_SYNC_RESET_SEL 0x1ecc +#define CAR_mmLB3_LB_SYNC_RESET_SEL 0x40cc +#define CAR_mmLB4_LB_SYNC_RESET_SEL 0x42cc +#define CAR_mmLB5_LB_SYNC_RESET_SEL 0x44cc +#define CAR_mmLB_BLACK_KEYER_R_CR 0x1acd +#define CAR_mmLB0_LB_BLACK_KEYER_R_CR 0x1acd +#define CAR_mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd +#define CAR_mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd +#define CAR_mmLB3_LB_BLACK_KEYER_R_CR 0x40cd +#define CAR_mmLB4_LB_BLACK_KEYER_R_CR 0x42cd +#define CAR_mmLB5_LB_BLACK_KEYER_R_CR 0x44cd +#define CAR_mmLB_BLACK_KEYER_G_Y 0x1ace +#define CAR_mmLB0_LB_BLACK_KEYER_G_Y 0x1ace +#define CAR_mmLB1_LB_BLACK_KEYER_G_Y 0x1cce +#define CAR_mmLB2_LB_BLACK_KEYER_G_Y 0x1ece +#define CAR_mmLB3_LB_BLACK_KEYER_G_Y 0x40ce +#define CAR_mmLB4_LB_BLACK_KEYER_G_Y 0x42ce +#define CAR_mmLB5_LB_BLACK_KEYER_G_Y 0x44ce +#define CAR_mmLB_BLACK_KEYER_B_CB 0x1acf +#define CAR_mmLB0_LB_BLACK_KEYER_B_CB 0x1acf +#define CAR_mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf +#define CAR_mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf +#define CAR_mmLB3_LB_BLACK_KEYER_B_CB 0x40cf +#define CAR_mmLB4_LB_BLACK_KEYER_B_CB 0x42cf +#define CAR_mmLB5_LB_BLACK_KEYER_B_CB 0x44cf +#define CAR_mmLB_KEYER_COLOR_CTRL 0x1ad0 +#define CAR_mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 +#define CAR_mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 +#define CAR_mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 +#define CAR_mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 +#define CAR_mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 +#define CAR_mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 +#define CAR_mmLB_KEYER_COLOR_R_CR 0x1ad1 +#define CAR_mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 +#define CAR_mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 +#define CAR_mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 +#define CAR_mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 +#define CAR_mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 +#define CAR_mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 +#define CAR_mmLB_KEYER_COLOR_G_Y 0x1ad2 +#define CAR_mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 +#define CAR_mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 +#define CAR_mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 +#define CAR_mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 +#define CAR_mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 +#define CAR_mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 +#define CAR_mmLB_KEYER_COLOR_B_CB 0x1ad3 +#define CAR_mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 +#define CAR_mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 +#define CAR_mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 +#define CAR_mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 +#define CAR_mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 +#define CAR_mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 +#define CAR_mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define CAR_mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define CAR_mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 +#define CAR_mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 +#define CAR_mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 +#define CAR_mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 +#define CAR_mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 +#define CAR_mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define CAR_mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define CAR_mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 +#define CAR_mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 +#define CAR_mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 +#define CAR_mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 +#define CAR_mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 +#define CAR_mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define CAR_mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define CAR_mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 +#define CAR_mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 +#define CAR_mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 +#define CAR_mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 +#define CAR_mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 +#define CAR_mmLB_BUFFER_LEVEL_STATUS 0x1ad7 +#define CAR_mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 +#define CAR_mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 +#define CAR_mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 +#define CAR_mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 +#define CAR_mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 +#define CAR_mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 +#define CAR_mmLB_BUFFER_URGENCY_CTRL 0x1ad8 +#define CAR_mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 +#define CAR_mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 +#define CAR_mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 +#define CAR_mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 +#define CAR_mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 +#define CAR_mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 +#define CAR_mmLB_BUFFER_URGENCY_STATUS 0x1ad9 +#define CAR_mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 +#define CAR_mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 +#define CAR_mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 +#define CAR_mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 +#define CAR_mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 +#define CAR_mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 +#define CAR_mmLB_BUFFER_STATUS 0x1ada +#define CAR_mmLB0_LB_BUFFER_STATUS 0x1ada +#define CAR_mmLB1_LB_BUFFER_STATUS 0x1cda +#define CAR_mmLB2_LB_BUFFER_STATUS 0x1eda +#define CAR_mmLB3_LB_BUFFER_STATUS 0x40da +#define CAR_mmLB4_LB_BUFFER_STATUS 0x42da +#define CAR_mmLB5_LB_BUFFER_STATUS 0x44da +#define CAR_mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define CAR_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define CAR_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc +#define CAR_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc +#define CAR_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc +#define CAR_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc +#define CAR_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc +#define CAR_mmMVP_AFR_FLIP_MODE 0x1ae0 +#define CAR_mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 +#define CAR_mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 +#define CAR_mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 +#define CAR_mmLB3_MVP_AFR_FLIP_MODE 0x40e0 +#define CAR_mmLB4_MVP_AFR_FLIP_MODE 0x42e0 +#define CAR_mmLB5_MVP_AFR_FLIP_MODE 0x44e0 +#define CAR_mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define CAR_mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define CAR_mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 +#define CAR_mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 +#define CAR_mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 +#define CAR_mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 +#define CAR_mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 +#define CAR_mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define CAR_mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define CAR_mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 +#define CAR_mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 +#define CAR_mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 +#define CAR_mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 +#define CAR_mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 +#define CAR_mmDC_MVP_LB_CONTROL 0x1ae3 +#define CAR_mmLB0_DC_MVP_LB_CONTROL 0x1ae3 +#define CAR_mmLB1_DC_MVP_LB_CONTROL 0x1ce3 +#define CAR_mmLB2_DC_MVP_LB_CONTROL 0x1ee3 +#define CAR_mmLB3_DC_MVP_LB_CONTROL 0x40e3 +#define CAR_mmLB4_DC_MVP_LB_CONTROL 0x42e3 +#define CAR_mmLB5_DC_MVP_LB_CONTROL 0x44e3 +#define CAR_mmLB_DEBUG 0x1ae4 +#define CAR_mmLB0_LB_DEBUG 0x1ae4 +#define CAR_mmLB1_LB_DEBUG 0x1ce4 +#define CAR_mmLB2_LB_DEBUG 0x1ee4 +#define CAR_mmLB3_LB_DEBUG 0x40e4 +#define CAR_mmLB4_LB_DEBUG 0x42e4 +#define CAR_mmLB5_LB_DEBUG 0x44e4 +#define CAR_mmLB_DEBUG2 0x1ae5 +#define CAR_mmLB0_LB_DEBUG2 0x1ae5 +#define CAR_mmLB1_LB_DEBUG2 0x1ce5 +#define CAR_mmLB2_LB_DEBUG2 0x1ee5 +#define CAR_mmLB3_LB_DEBUG2 0x40e5 +#define CAR_mmLB4_LB_DEBUG2 0x42e5 +#define CAR_mmLB5_LB_DEBUG2 0x44e5 +#define CAR_mmLB_DEBUG3 0x1ae6 +#define CAR_mmLB0_LB_DEBUG3 0x1ae6 +#define CAR_mmLB1_LB_DEBUG3 0x1ce6 +#define CAR_mmLB2_LB_DEBUG3 0x1ee6 +#define CAR_mmLB3_LB_DEBUG3 0x40e6 +#define CAR_mmLB4_LB_DEBUG3 0x42e6 +#define CAR_mmLB5_LB_DEBUG3 0x44e6 +#define CAR_mmLB_TEST_DEBUG_INDEX 0x1afe +#define CAR_mmLB0_LB_TEST_DEBUG_INDEX 0x1afe +#define CAR_mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe +#define CAR_mmLB2_LB_TEST_DEBUG_INDEX 0x1efe +#define CAR_mmLB3_LB_TEST_DEBUG_INDEX 0x40fe +#define CAR_mmLB4_LB_TEST_DEBUG_INDEX 0x42fe +#define CAR_mmLB5_LB_TEST_DEBUG_INDEX 0x44fe +#define CAR_mmLB_TEST_DEBUG_DATA 0x1aff +#define CAR_mmLB0_LB_TEST_DEBUG_DATA 0x1aff +#define CAR_mmLB1_LB_TEST_DEBUG_DATA 0x1cff +#define CAR_mmLB2_LB_TEST_DEBUG_DATA 0x1eff +#define CAR_mmLB3_LB_TEST_DEBUG_DATA 0x40ff +#define CAR_mmLB4_LB_TEST_DEBUG_DATA 0x42ff +#define CAR_mmLB5_LB_TEST_DEBUG_DATA 0x44ff +#define CAR_mmLBV_DATA_FORMAT 0x463c +#define CAR_mmLBV_MEMORY_CTRL 0x463d +#define CAR_mmLBV_MEMORY_SIZE_STATUS 0x463e +#define CAR_mmLBV_DESKTOP_HEIGHT 0x463f +#define CAR_mmLBV_VLINE_START_END 0x4640 +#define CAR_mmLBV_VLINE2_START_END 0x4641 +#define CAR_mmLBV_V_COUNTER 0x4642 +#define CAR_mmLBV_SNAPSHOT_V_COUNTER 0x4643 +#define CAR_mmLBV_V_COUNTER_CHROMA 0x4644 +#define CAR_mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 +#define CAR_mmLBV_INTERRUPT_MASK 0x4646 +#define CAR_mmLBV_VLINE_STATUS 0x4647 +#define CAR_mmLBV_VLINE2_STATUS 0x4648 +#define CAR_mmLBV_VBLANK_STATUS 0x4649 +#define CAR_mmLBV_SYNC_RESET_SEL 0x464a +#define CAR_mmLBV_BLACK_KEYER_R_CR 0x464b +#define CAR_mmLBV_BLACK_KEYER_G_Y 0x464c +#define CAR_mmLBV_BLACK_KEYER_B_CB 0x464d +#define CAR_mmLBV_KEYER_COLOR_CTRL 0x464e +#define CAR_mmLBV_KEYER_COLOR_R_CR 0x464f +#define CAR_mmLBV_KEYER_COLOR_G_Y 0x4650 +#define CAR_mmLBV_KEYER_COLOR_B_CB 0x4651 +#define CAR_mmLBV_KEYER_COLOR_REP_R_CR 0x4652 +#define CAR_mmLBV_KEYER_COLOR_REP_G_Y 0x4653 +#define CAR_mmLBV_KEYER_COLOR_REP_B_CB 0x4654 +#define CAR_mmLBV_BUFFER_LEVEL_STATUS 0x4655 +#define CAR_mmLBV_BUFFER_URGENCY_CTRL 0x4656 +#define CAR_mmLBV_BUFFER_URGENCY_STATUS 0x4657 +#define CAR_mmLBV_BUFFER_STATUS 0x4658 +#define CAR_mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 +#define CAR_mmLBV_DEBUG 0x465a +#define CAR_mmLBV_DEBUG2 0x465b +#define CAR_mmLBV_DEBUG3 0x465c +#define CAR_mmLBV_TEST_DEBUG_INDEX 0x4666 +#define CAR_mmLBV_TEST_DEBUG_DATA 0x4667 +#define CAR_mmMVP_CONTROL1 0x2ac +#define CAR_mmMVP_CONTROL2 0x2ad +#define CAR_mmMVP_FIFO_CONTROL 0x2ae +#define CAR_mmMVP_FIFO_STATUS 0x2af +#define CAR_mmMVP_SLAVE_STATUS 0x2b0 +#define CAR_mmMVP_INBAND_CNTL_CAP 0x2b1 +#define CAR_mmMVP_BLACK_KEYER 0x2b2 +#define CAR_mmMVP_CRC_CNTL 0x2b3 +#define CAR_mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 +#define CAR_mmMVP_CRC_RESULT_RED 0x2b5 +#define CAR_mmMVP_CONTROL3 0x2b6 +#define CAR_mmMVP_RECEIVE_CNT_CNTL1 0x2b7 +#define CAR_mmMVP_RECEIVE_CNT_CNTL2 0x2b8 +#define CAR_mmMVP_DEBUG 0x2bb +#define CAR_mmMVP_TEST_DEBUG_INDEX 0x2b9 +#define CAR_mmMVP_TEST_DEBUG_DATA 0x2ba +#define CAR_ixMVP_DEBUG_12 0xc +#define CAR_ixMVP_DEBUG_13 0xd +#define CAR_ixMVP_DEBUG_14 0xe +#define CAR_ixMVP_DEBUG_15 0xf +#define CAR_ixMVP_DEBUG_16 0x10 +#define CAR_ixMVP_DEBUG_17 0x11 +#define CAR_mmSCL_COEF_RAM_SELECT 0x1b40 +#define CAR_mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 +#define CAR_mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 +#define CAR_mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 +#define CAR_mmSCL3_SCL_COEF_RAM_SELECT 0x4140 +#define CAR_mmSCL4_SCL_COEF_RAM_SELECT 0x4340 +#define CAR_mmSCL5_SCL_COEF_RAM_SELECT 0x4540 +#define CAR_mmSCL_COEF_RAM_TAP_DATA 0x1b41 +#define CAR_mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 +#define CAR_mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 +#define CAR_mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 +#define CAR_mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 +#define CAR_mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 +#define CAR_mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 +#define CAR_mmSCL_MODE 0x1b42 +#define CAR_mmSCL0_SCL_MODE 0x1b42 +#define CAR_mmSCL1_SCL_MODE 0x1d42 +#define CAR_mmSCL2_SCL_MODE 0x1f42 +#define CAR_mmSCL3_SCL_MODE 0x4142 +#define CAR_mmSCL4_SCL_MODE 0x4342 +#define CAR_mmSCL5_SCL_MODE 0x4542 +#define CAR_mmSCL_TAP_CONTROL 0x1b43 +#define CAR_mmSCL0_SCL_TAP_CONTROL 0x1b43 +#define CAR_mmSCL1_SCL_TAP_CONTROL 0x1d43 +#define CAR_mmSCL2_SCL_TAP_CONTROL 0x1f43 +#define CAR_mmSCL3_SCL_TAP_CONTROL 0x4143 +#define CAR_mmSCL4_SCL_TAP_CONTROL 0x4343 +#define CAR_mmSCL5_SCL_TAP_CONTROL 0x4543 +#define CAR_mmSCL_CONTROL 0x1b44 +#define CAR_mmSCL0_SCL_CONTROL 0x1b44 +#define CAR_mmSCL1_SCL_CONTROL 0x1d44 +#define CAR_mmSCL2_SCL_CONTROL 0x1f44 +#define CAR_mmSCL3_SCL_CONTROL 0x4144 +#define CAR_mmSCL4_SCL_CONTROL 0x4344 +#define CAR_mmSCL5_SCL_CONTROL 0x4544 +#define CAR_mmSCL_BYPASS_CONTROL 0x1b45 +#define CAR_mmSCL0_SCL_BYPASS_CONTROL 0x1b45 +#define CAR_mmSCL1_SCL_BYPASS_CONTROL 0x1d45 +#define CAR_mmSCL2_SCL_BYPASS_CONTROL 0x1f45 +#define CAR_mmSCL3_SCL_BYPASS_CONTROL 0x4145 +#define CAR_mmSCL4_SCL_BYPASS_CONTROL 0x4345 +#define CAR_mmSCL5_SCL_BYPASS_CONTROL 0x4545 +#define CAR_mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define CAR_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define CAR_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 +#define CAR_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 +#define CAR_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define CAR_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 +#define CAR_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 +#define CAR_mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define CAR_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define CAR_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 +#define CAR_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 +#define CAR_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define CAR_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 +#define CAR_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 +#define CAR_mmSCL_HORZ_FILTER_CONTROL 0x1b48 +#define CAR_mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 +#define CAR_mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 +#define CAR_mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 +#define CAR_mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 +#define CAR_mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 +#define CAR_mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 +#define CAR_mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define CAR_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define CAR_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 +#define CAR_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 +#define CAR_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 +#define CAR_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 +#define CAR_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 +#define CAR_mmSCL_HORZ_FILTER_INIT 0x1b4a +#define CAR_mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a +#define CAR_mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a +#define CAR_mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a +#define CAR_mmSCL3_SCL_HORZ_FILTER_INIT 0x414a +#define CAR_mmSCL4_SCL_HORZ_FILTER_INIT 0x434a +#define CAR_mmSCL5_SCL_HORZ_FILTER_INIT 0x454a +#define CAR_mmSCL_VERT_FILTER_CONTROL 0x1b4b +#define CAR_mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b +#define CAR_mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b +#define CAR_mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b +#define CAR_mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b +#define CAR_mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b +#define CAR_mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b +#define CAR_mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define CAR_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define CAR_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c +#define CAR_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c +#define CAR_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c +#define CAR_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c +#define CAR_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c +#define CAR_mmSCL_VERT_FILTER_INIT 0x1b4d +#define CAR_mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d +#define CAR_mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d +#define CAR_mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d +#define CAR_mmSCL3_SCL_VERT_FILTER_INIT 0x414d +#define CAR_mmSCL4_SCL_VERT_FILTER_INIT 0x434d +#define CAR_mmSCL5_SCL_VERT_FILTER_INIT 0x454d +#define CAR_mmSCL_VERT_FILTER_INIT_BOT 0x1b4e +#define CAR_mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e +#define CAR_mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e +#define CAR_mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e +#define CAR_mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e +#define CAR_mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e +#define CAR_mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e +#define CAR_mmSCL_ROUND_OFFSET 0x1b4f +#define CAR_mmSCL0_SCL_ROUND_OFFSET 0x1b4f +#define CAR_mmSCL1_SCL_ROUND_OFFSET 0x1d4f +#define CAR_mmSCL2_SCL_ROUND_OFFSET 0x1f4f +#define CAR_mmSCL3_SCL_ROUND_OFFSET 0x414f +#define CAR_mmSCL4_SCL_ROUND_OFFSET 0x434f +#define CAR_mmSCL5_SCL_ROUND_OFFSET 0x454f +#define CAR_mmSCL_UPDATE 0x1b51 +#define CAR_mmSCL0_SCL_UPDATE 0x1b51 +#define CAR_mmSCL1_SCL_UPDATE 0x1d51 +#define CAR_mmSCL2_SCL_UPDATE 0x1f51 +#define CAR_mmSCL3_SCL_UPDATE 0x4151 +#define CAR_mmSCL4_SCL_UPDATE 0x4351 +#define CAR_mmSCL5_SCL_UPDATE 0x4551 +#define CAR_mmSCL_F_SHARP_CONTROL 0x1b53 +#define CAR_mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 +#define CAR_mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 +#define CAR_mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 +#define CAR_mmSCL3_SCL_F_SHARP_CONTROL 0x4153 +#define CAR_mmSCL4_SCL_F_SHARP_CONTROL 0x4353 +#define CAR_mmSCL5_SCL_F_SHARP_CONTROL 0x4553 +#define CAR_mmSCL_ALU_CONTROL 0x1b54 +#define CAR_mmSCL0_SCL_ALU_CONTROL 0x1b54 +#define CAR_mmSCL1_SCL_ALU_CONTROL 0x1d54 +#define CAR_mmSCL2_SCL_ALU_CONTROL 0x1f54 +#define CAR_mmSCL3_SCL_ALU_CONTROL 0x4154 +#define CAR_mmSCL4_SCL_ALU_CONTROL 0x4354 +#define CAR_mmSCL5_SCL_ALU_CONTROL 0x4554 +#define CAR_mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define CAR_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define CAR_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 +#define CAR_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 +#define CAR_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define CAR_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 +#define CAR_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 +#define CAR_mmVIEWPORT_START_SECONDARY 0x1b5b +#define CAR_mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b +#define CAR_mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b +#define CAR_mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b +#define CAR_mmSCL3_VIEWPORT_START_SECONDARY 0x415b +#define CAR_mmSCL4_VIEWPORT_START_SECONDARY 0x435b +#define CAR_mmSCL5_VIEWPORT_START_SECONDARY 0x455b +#define CAR_mmVIEWPORT_START 0x1b5c +#define CAR_mmSCL0_VIEWPORT_START 0x1b5c +#define CAR_mmSCL1_VIEWPORT_START 0x1d5c +#define CAR_mmSCL2_VIEWPORT_START 0x1f5c +#define CAR_mmSCL3_VIEWPORT_START 0x415c +#define CAR_mmSCL4_VIEWPORT_START 0x435c +#define CAR_mmSCL5_VIEWPORT_START 0x455c +#define CAR_mmVIEWPORT_SIZE 0x1b5d +#define CAR_mmSCL0_VIEWPORT_SIZE 0x1b5d +#define CAR_mmSCL1_VIEWPORT_SIZE 0x1d5d +#define CAR_mmSCL2_VIEWPORT_SIZE 0x1f5d +#define CAR_mmSCL3_VIEWPORT_SIZE 0x415d +#define CAR_mmSCL4_VIEWPORT_SIZE 0x435d +#define CAR_mmSCL5_VIEWPORT_SIZE 0x455d +#define CAR_mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define CAR_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define CAR_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e +#define CAR_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e +#define CAR_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e +#define CAR_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e +#define CAR_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e +#define CAR_mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define CAR_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define CAR_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f +#define CAR_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f +#define CAR_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f +#define CAR_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f +#define CAR_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f +#define CAR_mmSCL_MODE_CHANGE_DET1 0x1b60 +#define CAR_mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 +#define CAR_mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 +#define CAR_mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 +#define CAR_mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 +#define CAR_mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 +#define CAR_mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 +#define CAR_mmSCL_MODE_CHANGE_DET2 0x1b61 +#define CAR_mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 +#define CAR_mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 +#define CAR_mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 +#define CAR_mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 +#define CAR_mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 +#define CAR_mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 +#define CAR_mmSCL_MODE_CHANGE_DET3 0x1b62 +#define CAR_mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 +#define CAR_mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 +#define CAR_mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 +#define CAR_mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 +#define CAR_mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 +#define CAR_mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 +#define CAR_mmSCL_MODE_CHANGE_MASK 0x1b63 +#define CAR_mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 +#define CAR_mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 +#define CAR_mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 +#define CAR_mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 +#define CAR_mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 +#define CAR_mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 +#define CAR_mmSCL_DEBUG2 0x1b69 +#define CAR_mmSCL0_SCL_DEBUG2 0x1b69 +#define CAR_mmSCL1_SCL_DEBUG2 0x1d69 +#define CAR_mmSCL2_SCL_DEBUG2 0x1f69 +#define CAR_mmSCL3_SCL_DEBUG2 0x4169 +#define CAR_mmSCL4_SCL_DEBUG2 0x4369 +#define CAR_mmSCL5_SCL_DEBUG2 0x4569 +#define CAR_mmSCL_DEBUG 0x1b6a +#define CAR_mmSCL0_SCL_DEBUG 0x1b6a +#define CAR_mmSCL1_SCL_DEBUG 0x1d6a +#define CAR_mmSCL2_SCL_DEBUG 0x1f6a +#define CAR_mmSCL3_SCL_DEBUG 0x416a +#define CAR_mmSCL4_SCL_DEBUG 0x436a +#define CAR_mmSCL5_SCL_DEBUG 0x456a +#define CAR_mmSCL_TEST_DEBUG_INDEX 0x1b6b +#define CAR_mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b +#define CAR_mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b +#define CAR_mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b +#define CAR_mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b +#define CAR_mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b +#define CAR_mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b +#define CAR_mmSCL_TEST_DEBUG_DATA 0x1b6c +#define CAR_mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c +#define CAR_mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c +#define CAR_mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c +#define CAR_mmSCL3_SCL_TEST_DEBUG_DATA 0x416c +#define CAR_mmSCL4_SCL_TEST_DEBUG_DATA 0x436c +#define CAR_mmSCL5_SCL_TEST_DEBUG_DATA 0x456c +#define CAR_mmSCLV_COEF_RAM_SELECT 0x4670 +#define CAR_mmSCLV_COEF_RAM_TAP_DATA 0x4671 +#define CAR_mmSCLV_MODE 0x4672 +#define CAR_mmSCLV_TAP_CONTROL 0x4673 +#define CAR_mmSCLV_CONTROL 0x4674 +#define CAR_mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 +#define CAR_mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 +#define CAR_mmSCLV_HORZ_FILTER_CONTROL 0x4677 +#define CAR_mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 +#define CAR_mmSCLV_HORZ_FILTER_INIT 0x4679 +#define CAR_mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a +#define CAR_mmSCLV_HORZ_FILTER_INIT_C 0x467b +#define CAR_mmSCLV_VERT_FILTER_CONTROL 0x467c +#define CAR_mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d +#define CAR_mmSCLV_VERT_FILTER_INIT 0x467e +#define CAR_mmSCLV_VERT_FILTER_INIT_BOT 0x467f +#define CAR_mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 +#define CAR_mmSCLV_VERT_FILTER_INIT_C 0x4681 +#define CAR_mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 +#define CAR_mmSCLV_ROUND_OFFSET 0x4683 +#define CAR_mmSCLV_UPDATE 0x4684 +#define CAR_mmSCLV_ALU_CONTROL 0x4685 +#define CAR_mmSCLV_VIEWPORT_START 0x4686 +#define CAR_mmSCLV_VIEWPORT_START_SECONDARY 0x4687 +#define CAR_mmSCLV_VIEWPORT_SIZE 0x4688 +#define CAR_mmSCLV_VIEWPORT_START_C 0x4689 +#define CAR_mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a +#define CAR_mmSCLV_VIEWPORT_SIZE_C 0x468b +#define CAR_mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c +#define CAR_mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d +#define CAR_mmSCLV_MODE_CHANGE_DET1 0x468e +#define CAR_mmSCLV_MODE_CHANGE_DET2 0x468f +#define CAR_mmSCLV_MODE_CHANGE_DET3 0x4690 +#define CAR_mmSCLV_MODE_CHANGE_MASK 0x4691 +#define CAR_mmSCLV_HORZ_FILTER_INIT_BOT 0x4692 +#define CAR_mmSCLV_HORZ_FILTER_INIT_BOT_C 0x4693 +#define CAR_mmSCLV_DEBUG2 0x4694 +#define CAR_mmSCLV_DEBUG 0x4695 +#define CAR_mmSCLV_TEST_DEBUG_INDEX 0x4696 +#define CAR_mmSCLV_TEST_DEBUG_DATA 0x4697 +#define CAR_mmCOL_MAN_UPDATE 0x46a4 +#define CAR_mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 +#define CAR_mmINPUT_CSC_C11_C12_A 0x46a6 +#define CAR_mmINPUT_CSC_C13_C14_A 0x46a7 +#define CAR_mmINPUT_CSC_C21_C22_A 0x46a8 +#define CAR_mmINPUT_CSC_C23_C24_A 0x46a9 +#define CAR_mmINPUT_CSC_C31_C32_A 0x46aa +#define CAR_mmINPUT_CSC_C33_C34_A 0x46ab +#define CAR_mmINPUT_CSC_C11_C12_B 0x46ac +#define CAR_mmINPUT_CSC_C13_C14_B 0x46ad +#define CAR_mmINPUT_CSC_C21_C22_B 0x46ae +#define CAR_mmINPUT_CSC_C23_C24_B 0x46af +#define CAR_mmINPUT_CSC_C31_C32_B 0x46b0 +#define CAR_mmINPUT_CSC_C33_C34_B 0x46b1 +#define CAR_mmPRESCALE_CONTROL 0x46b2 +#define CAR_mmPRESCALE_VALUES_R 0x46b3 +#define CAR_mmPRESCALE_VALUES_G 0x46b4 +#define CAR_mmPRESCALE_VALUES_B 0x46b5 +#define CAR_mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 +#define CAR_mmOUTPUT_CSC_C11_C12_A 0x46b7 +#define CAR_mmOUTPUT_CSC_C13_C14_A 0x46b8 +#define CAR_mmOUTPUT_CSC_C21_C22_A 0x46b9 +#define CAR_mmOUTPUT_CSC_C23_C24_A 0x46ba +#define CAR_mmOUTPUT_CSC_C31_C32_A 0x46bb +#define CAR_mmOUTPUT_CSC_C33_C34_A 0x46bc +#define CAR_mmOUTPUT_CSC_C11_C12_B 0x46bd +#define CAR_mmOUTPUT_CSC_C13_C14_B 0x46be +#define CAR_mmOUTPUT_CSC_C21_C22_B 0x46bf +#define CAR_mmOUTPUT_CSC_C23_C24_B 0x46c0 +#define CAR_mmOUTPUT_CSC_C31_C32_B 0x46c1 +#define CAR_mmOUTPUT_CSC_C33_C34_B 0x46c2 +#define CAR_mmDENORM_CLAMP_CONTROL 0x46c3 +#define CAR_mmDENORM_CLAMP_RANGE_R_CR 0x46c4 +#define CAR_mmDENORM_CLAMP_RANGE_G_Y 0x46c5 +#define CAR_mmDENORM_CLAMP_RANGE_B_CB 0x46c6 +#define CAR_mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 +#define CAR_mmGAMMA_CORR_CONTROL 0x46c8 +#define CAR_mmGAMMA_CORR_LUT_INDEX 0x46c9 +#define CAR_mmGAMMA_CORR_LUT_DATA 0x46ca +#define CAR_mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb +#define CAR_mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc +#define CAR_mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd +#define CAR_mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce +#define CAR_mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf +#define CAR_mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 +#define CAR_mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 +#define CAR_mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 +#define CAR_mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 +#define CAR_mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 +#define CAR_mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 +#define CAR_mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 +#define CAR_mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 +#define CAR_mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 +#define CAR_mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 +#define CAR_mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da +#define CAR_mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db +#define CAR_mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc +#define CAR_mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd +#define CAR_mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de +#define CAR_mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df +#define CAR_mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 +#define CAR_mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 +#define CAR_mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 +#define CAR_mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 +#define CAR_mmPACK_FIFO_ERROR 0x46e4 +#define CAR_mmOUTPUT_FIFO_ERROR 0x46e5 +#define CAR_mmINPUT_GAMMA_LUT_AUTOFILL 0x46e6 +#define CAR_mmINPUT_GAMMA_LUT_RW_INDEX 0x46e7 +#define CAR_mmINPUT_GAMMA_LUT_SEQ_COLOR 0x46e8 +#define CAR_mmINPUT_GAMMA_LUT_PWL_DATA 0x46e9 +#define CAR_mmINPUT_GAMMA_LUT_30_COLOR 0x46ea +#define CAR_mmCOL_MAN_INPUT_GAMMA_CONTROL1 0x46eb +#define CAR_mmCOL_MAN_INPUT_GAMMA_CONTROL2 0x46ec +#define CAR_mmINPUT_GAMMA_BW_OFFSETS_B 0x46ed +#define CAR_mmINPUT_GAMMA_BW_OFFSETS_G 0x46ee +#define CAR_mmINPUT_GAMMA_BW_OFFSETS_R 0x46ef +#define CAR_mmCOL_MAN_DEBUG_CONTROL 0x46f0 +#define CAR_mmCOL_MAN_TEST_DEBUG_INDEX 0x46f1 +#define CAR_mmCOL_MAN_TEST_DEBUG_DATA 0x46f3 +#define CAR_mmUNP_GRPH_ENABLE 0x4600 +#define CAR_mmUNP_GRPH_CONTROL 0x4601 +#define CAR_mmUNP_GRPH_CONTROL_C 0x4602 +#define CAR_mmUNP_GRPH_CONTROL_EXP 0x4603 +#define CAR_mmUNP_GRPH_SWAP_CNTL 0x4605 +#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 +#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 +#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 +#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 +#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a +#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b +#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c +#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d +#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e +#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f +#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 +#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 +#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 +#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 +#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 +#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 +#define CAR_mmUNP_GRPH_PITCH_L 0x4616 +#define CAR_mmUNP_GRPH_PITCH_C 0x4617 +#define CAR_mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 +#define CAR_mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 +#define CAR_mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a +#define CAR_mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b +#define CAR_mmUNP_GRPH_X_START_L 0x461c +#define CAR_mmUNP_GRPH_X_START_C 0x461d +#define CAR_mmUNP_GRPH_Y_START_L 0x461e +#define CAR_mmUNP_GRPH_Y_START_C 0x461f +#define CAR_mmUNP_GRPH_X_END_L 0x4620 +#define CAR_mmUNP_GRPH_X_END_C 0x4621 +#define CAR_mmUNP_GRPH_Y_END_L 0x4622 +#define CAR_mmUNP_GRPH_Y_END_C 0x4623 +#define CAR_mmUNP_GRPH_UPDATE 0x4624 +#define CAR_mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a +#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 +#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 +#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 +#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 +#define CAR_mmUNP_DVMM_PTE_CONTROL 0x4629 +#define CAR_mmUNP_DVMM_PTE_CONTROL_C 0x4604 +#define CAR_mmUNP_DVMM_PTE_ARB_CONTROL 0x462a +#define CAR_mmUNP_DVMM_PTE_ARB_CONTROL_C 0x462d +#define CAR_mmUNP_GRPH_INTERRUPT_STATUS 0x462b +#define CAR_mmUNP_GRPH_INTERRUPT_CONTROL 0x462c +#define CAR_mmUNP_GRPH_STEREOSYNC_FLIP 0x462e +#define CAR_mmUNP_FLIP_CONTROL 0x462f +#define CAR_mmUNP_CRC_CONTROL 0x4630 +#define CAR_mmUNP_CRC_MASK 0x4631 +#define CAR_mmUNP_CRC_CURRENT 0x4632 +#define CAR_mmUNP_CRC_LAST 0x4633 +#define CAR_mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 +#define CAR_mmUNP_HW_ROTATION 0x4635 +#define CAR_mmUNP_DEBUG 0x4636 +#define CAR_mmUNP_DEBUG2 0x4637 +#define CAR_mmUNP_DVMM_DEBUG 0x463b +#define CAR_mmUNP_TEST_DEBUG_INDEX 0x4638 +#define CAR_mmUNP_TEST_DEBUG_DATA 0x4639 +#define CAR_mmGENMO_WT 0xf0 +#define CAR_mmGENMO_RD 0xf3 +#define CAR_mmGENENB 0xf0 +#define CAR_mmGENFC_WT 0xee +#define CAR_mmVGA0_GENFC_WT 0xee +#define CAR_mmVGA1_GENFC_WT 0xf6 +#define CAR_mmGENFC_RD 0xf2 +#define CAR_mmGENS0 0xf0 +#define CAR_mmGENS1 0xee +#define CAR_mmVGA0_GENS1 0xee +#define CAR_mmVGA1_GENS1 0xf6 +#define CAR_mmDAC_DATA 0xf2 +#define CAR_mmDAC_MASK 0xf1 +#define CAR_mmDAC_R_INDEX 0xf1 +#define CAR_mmDAC_W_INDEX 0xf2 +#define CAR_mmSEQ8_IDX 0xf1 +#define CAR_mmSEQ8_DATA 0xf1 +#define CAR_ixSEQ00 0x0 +#define CAR_ixSEQ01 0x1 +#define CAR_ixSEQ02 0x2 +#define CAR_ixSEQ03 0x3 +#define CAR_ixSEQ04 0x4 +#define CAR_mmCRTC8_IDX 0xed +#define CAR_mmVGA0_CRTC8_IDX 0xed +#define CAR_mmVGA1_CRTC8_IDX 0xf5 +#define CAR_mmCRTC8_DATA 0xed +#define CAR_mmVGA0_CRTC8_DATA 0xed +#define CAR_mmVGA1_CRTC8_DATA 0xf5 +#define CAR_ixCRT00 0x0 +#define CAR_ixCRT01 0x1 +#define CAR_ixCRT02 0x2 +#define CAR_ixCRT03 0x3 +#define CAR_ixCRT04 0x4 +#define CAR_ixCRT05 0x5 +#define CAR_ixCRT06 0x6 +#define CAR_ixCRT07 0x7 +#define CAR_ixCRT08 0x8 +#define CAR_ixCRT09 0x9 +#define CAR_ixCRT0A 0xa +#define CAR_ixCRT0B 0xb +#define CAR_ixCRT0C 0xc +#define CAR_ixCRT0D 0xd +#define CAR_ixCRT0E 0xe +#define CAR_ixCRT0F 0xf +#define CAR_ixCRT10 0x10 +#define CAR_ixCRT11 0x11 +#define CAR_ixCRT12 0x12 +#define CAR_ixCRT13 0x13 +#define CAR_ixCRT14 0x14 +#define CAR_ixCRT15 0x15 +#define CAR_ixCRT16 0x16 +#define CAR_ixCRT17 0x17 +#define CAR_ixCRT18 0x18 +#define CAR_ixCRT1E 0x1e +#define CAR_ixCRT1F 0x1f +#define CAR_ixCRT22 0x22 +#define CAR_mmGRPH8_IDX 0xf3 +#define CAR_mmGRPH8_DATA 0xf3 +#define CAR_ixGRA00 0x0 +#define CAR_ixGRA01 0x1 +#define CAR_ixGRA02 0x2 +#define CAR_ixGRA03 0x3 +#define CAR_ixGRA04 0x4 +#define CAR_ixGRA05 0x5 +#define CAR_ixGRA06 0x6 +#define CAR_ixGRA07 0x7 +#define CAR_ixGRA08 0x8 +#define CAR_mmATTRX 0xf0 +#define CAR_mmATTRDW 0xf0 +#define CAR_mmATTRDR 0xf0 +#define CAR_ixATTR00 0x0 +#define CAR_ixATTR01 0x1 +#define CAR_ixATTR02 0x2 +#define CAR_ixATTR03 0x3 +#define CAR_ixATTR04 0x4 +#define CAR_ixATTR05 0x5 +#define CAR_ixATTR06 0x6 +#define CAR_ixATTR07 0x7 +#define CAR_ixATTR08 0x8 +#define CAR_ixATTR09 0x9 +#define CAR_ixATTR0A 0xa +#define CAR_ixATTR0B 0xb +#define CAR_ixATTR0C 0xc +#define CAR_ixATTR0D 0xd +#define CAR_ixATTR0E 0xe +#define CAR_ixATTR0F 0xf +#define CAR_ixATTR10 0x10 +#define CAR_ixATTR11 0x11 +#define CAR_ixATTR12 0x12 +#define CAR_ixATTR13 0x13 +#define CAR_ixATTR14 0x14 +#define CAR_mmVGA_RENDER_CONTROL 0xc0 +#define CAR_mmVGA_SOURCE_SELECT 0xfc +#define CAR_mmVGA_SEQUENCER_RESET_CONTROL 0xc1 +#define CAR_mmVGA_MODE_CONTROL 0xc2 +#define CAR_mmVGA_SURFACE_PITCH_SELECT 0xc3 +#define CAR_mmVGA_MEMORY_BASE_ADDRESS 0xc4 +#define CAR_mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 +#define CAR_mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 +#define CAR_mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 +#define CAR_mmVGA_HDP_CONTROL 0xca +#define CAR_mmVGA_CACHE_CONTROL 0xcb +#define CAR_mmD1VGA_CONTROL 0xcc +#define CAR_mmD2VGA_CONTROL 0xce +#define CAR_mmD3VGA_CONTROL 0xf8 +#define CAR_mmD4VGA_CONTROL 0xf9 +#define CAR_mmD5VGA_CONTROL 0xfa +#define CAR_mmD6VGA_CONTROL 0xfb +#define CAR_mmVGA_HW_DEBUG 0xcf +#define CAR_mmVGA_STATUS 0xd0 +#define CAR_mmVGA_INTERRUPT_CONTROL 0xd1 +#define CAR_mmVGA_STATUS_CLEAR 0xd2 +#define CAR_mmVGA_INTERRUPT_STATUS 0xd3 +#define CAR_mmVGA_MAIN_CONTROL 0xd4 +#define CAR_mmVGA_TEST_CONTROL 0xd5 +#define CAR_mmVGA_DEBUG_READBACK_INDEX 0xd6 +#define CAR_mmVGA_DEBUG_READBACK_DATA 0xd7 +#define CAR_mmVGA_MEM_WRITE_PAGE_ADDR 0x12 +#define CAR_mmVGA_MEM_READ_PAGE_ADDR 0x13 +#define CAR_mmVGA_TEST_DEBUG_INDEX 0xc5 +#define CAR_mmVGA_TEST_DEBUG_DATA 0xc7 +#define CAR_ixVGADCC_DBG_DCCIF_C 0x7e +#define CAR_mmBPHYC_DAC_MACRO_CNTL 0x48b9 +#define CAR_mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba +#define CAR_mmPLL_REF_DIV 0x1700 +#define CAR_mmBPHYC_PLL0_PLL_REF_DIV 0x1700 +#define CAR_mmBPHYC_PLL1_PLL_REF_DIV 0x172a +#define CAR_mmBPHYC_PLL2_PLL_REF_DIV 0x1754 +#define CAR_mmPLL_FB_DIV 0x1701 +#define CAR_mmBPHYC_PLL0_PLL_FB_DIV 0x1701 +#define CAR_mmBPHYC_PLL1_PLL_FB_DIV 0x172b +#define CAR_mmBPHYC_PLL2_PLL_FB_DIV 0x1755 +#define CAR_mmPLL_POST_DIV 0x1702 +#define CAR_mmBPHYC_PLL0_PLL_POST_DIV 0x1702 +#define CAR_mmBPHYC_PLL1_PLL_POST_DIV 0x172c +#define CAR_mmBPHYC_PLL2_PLL_POST_DIV 0x1756 +#define CAR_mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define CAR_mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define CAR_mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d +#define CAR_mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757 +#define CAR_mmPLL_SS_CNTL 0x1704 +#define CAR_mmBPHYC_PLL0_PLL_SS_CNTL 0x1704 +#define CAR_mmBPHYC_PLL1_PLL_SS_CNTL 0x172e +#define CAR_mmBPHYC_PLL2_PLL_SS_CNTL 0x1758 +#define CAR_mmPLL_DS_CNTL 0x1705 +#define CAR_mmBPHYC_PLL0_PLL_DS_CNTL 0x1705 +#define CAR_mmBPHYC_PLL1_PLL_DS_CNTL 0x172f +#define CAR_mmBPHYC_PLL2_PLL_DS_CNTL 0x1759 +#define CAR_mmPLL_IDCLK_CNTL 0x1706 +#define CAR_mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706 +#define CAR_mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730 +#define CAR_mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a +#define CAR_mmPLL_CNTL 0x1707 +#define CAR_mmBPHYC_PLL0_PLL_CNTL 0x1707 +#define CAR_mmBPHYC_PLL1_PLL_CNTL 0x1731 +#define CAR_mmBPHYC_PLL2_PLL_CNTL 0x175b +#define CAR_mmPLL_ANALOG 0x1708 +#define CAR_mmBPHYC_PLL0_PLL_ANALOG 0x1708 +#define CAR_mmBPHYC_PLL1_PLL_ANALOG 0x1732 +#define CAR_mmBPHYC_PLL2_PLL_ANALOG 0x175c +#define CAR_mmPLL_VREG_CNTL 0x1709 +#define CAR_mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709 +#define CAR_mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733 +#define CAR_mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d +#define CAR_mmPLL_UNLOCK_DETECT_CNTL 0x170a +#define CAR_mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a +#define CAR_mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734 +#define CAR_mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e +#define CAR_mmPLL_DEBUG_CNTL 0x170b +#define CAR_mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b +#define CAR_mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735 +#define CAR_mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f +#define CAR_mmPLL_UPDATE_LOCK 0x170c +#define CAR_mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c +#define CAR_mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736 +#define CAR_mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760 +#define CAR_mmPLL_UPDATE_CNTL 0x170d +#define CAR_mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d +#define CAR_mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737 +#define CAR_mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761 +#define CAR_mmPLL_XOR_LOCK 0x1710 +#define CAR_mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710 +#define CAR_mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a +#define CAR_mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764 +#define CAR_mmPLL_ANALOG_CNTL 0x1711 +#define CAR_mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711 +#define CAR_mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b +#define CAR_mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765 +#define CAR_mmVGA25_PPLL_REF_DIV 0x1712 +#define CAR_mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712 +#define CAR_mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c +#define CAR_mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766 +#define CAR_mmVGA28_PPLL_REF_DIV 0x1713 +#define CAR_mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713 +#define CAR_mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d +#define CAR_mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767 +#define CAR_mmVGA41_PPLL_REF_DIV 0x1714 +#define CAR_mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714 +#define CAR_mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e +#define CAR_mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768 +#define CAR_mmVGA25_PPLL_FB_DIV 0x1715 +#define CAR_mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715 +#define CAR_mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f +#define CAR_mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769 +#define CAR_mmVGA28_PPLL_FB_DIV 0x1716 +#define CAR_mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716 +#define CAR_mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740 +#define CAR_mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a +#define CAR_mmVGA41_PPLL_FB_DIV 0x1717 +#define CAR_mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717 +#define CAR_mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741 +#define CAR_mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b +#define CAR_mmVGA25_PPLL_POST_DIV 0x1718 +#define CAR_mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718 +#define CAR_mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742 +#define CAR_mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c +#define CAR_mmVGA28_PPLL_POST_DIV 0x1719 +#define CAR_mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719 +#define CAR_mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743 +#define CAR_mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d +#define CAR_mmVGA41_PPLL_POST_DIV 0x171a +#define CAR_mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a +#define CAR_mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744 +#define CAR_mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e +#define CAR_mmVGA25_PPLL_ANALOG 0x171b +#define CAR_mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b +#define CAR_mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745 +#define CAR_mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f +#define CAR_mmVGA28_PPLL_ANALOG 0x171c +#define CAR_mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c +#define CAR_mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746 +#define CAR_mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770 +#define CAR_mmVGA41_PPLL_ANALOG 0x171d +#define CAR_mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d +#define CAR_mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747 +#define CAR_mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771 +#define CAR_mmDISPPLL_BG_CNTL 0x171e +#define CAR_mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e +#define CAR_mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748 +#define CAR_mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772 +#define CAR_mmPPLL_DIV_UPDATE_DEBUG 0x171f +#define CAR_mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f +#define CAR_mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749 +#define CAR_mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773 +#define CAR_mmPPLL_STATUS_DEBUG 0x1720 +#define CAR_mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720 +#define CAR_mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a +#define CAR_mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774 +#define CAR_mmPPLL_DEBUG_MUX_CNTL 0x1721 +#define CAR_mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721 +#define CAR_mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b +#define CAR_mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775 +#define CAR_mmPPLL_SPARE0 0x1722 +#define CAR_mmBPHYC_PLL0_PPLL_SPARE0 0x1722 +#define CAR_mmBPHYC_PLL1_PPLL_SPARE0 0x174c +#define CAR_mmBPHYC_PLL2_PPLL_SPARE0 0x1776 +#define CAR_mmPPLL_SPARE1 0x1723 +#define CAR_mmBPHYC_PLL0_PPLL_SPARE1 0x1723 +#define CAR_mmBPHYC_PLL1_PPLL_SPARE1 0x174d +#define CAR_mmBPHYC_PLL2_PPLL_SPARE1 0x1777 +#define CAR_mmUNIPHY_TX_CONTROL1 0x48c0 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1 0x49c0 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1 0x49e0 +#define CAR_mmUNIPHY_TX_CONTROL2 0x48c1 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2 0x49c1 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2 0x49e1 +#define CAR_mmUNIPHY_TX_CONTROL3 0x48c2 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3 0x49c2 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3 0x49e2 +#define CAR_mmUNIPHY_TX_CONTROL4 0x48c3 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4 0x49c3 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4 0x49e3 +#define CAR_mmUNIPHY_POWER_CONTROL 0x48c4 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL 0x49c4 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL 0x49e4 +#define CAR_mmUNIPHY_PLL_FBDIV 0x48c5 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV 0x49c5 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV 0x49e5 +#define CAR_mmUNIPHY_PLL_CONTROL1 0x48c6 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1 0x49c6 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1 0x49e6 +#define CAR_mmUNIPHY_PLL_CONTROL2 0x48c7 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2 0x49c7 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2 0x49e7 +#define CAR_mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE 0x49c8 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE 0x49e8 +#define CAR_mmUNIPHY_PLL_SS_CNTL 0x48c9 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL 0x49c9 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL 0x49e9 +#define CAR_mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_DATA_SYNCHRONIZATION 0x49ca +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_DATA_SYNCHRONIZATION 0x49ea +#define CAR_mmUNIPHY_REG_TEST_OUTPUT 0x48cb +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT 0x49cb +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT 0x49eb +#define CAR_mmUNIPHY_ANG_BIST_CNTL 0x48cc +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL 0x49cc +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL 0x49ec +#define CAR_mmUNIPHY_REG_TEST_OUTPUT2 0x48cd +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2 0x49cd +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2 0x49ed +#define CAR_mmUNIPHY_TMDP_REG0 0x48ce +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0 0x49ce +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0 0x49ee +#define CAR_mmUNIPHY_TMDP_REG1 0x48cf +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1 0x49cf +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1 0x49ef +#define CAR_mmUNIPHY_TMDP_REG2 0x48d0 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2 0x49d0 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2 0x49f0 +#define CAR_mmUNIPHY_TMDP_REG3 0x48d1 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3 0x49d1 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3 0x49f1 +#define CAR_mmUNIPHY_TMDP_REG4 0x48d2 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4 0x49d2 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4 0x49f2 +#define CAR_mmUNIPHY_TMDP_REG5 0x48d3 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5 0x49d3 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5 0x49f3 +#define CAR_mmUNIPHY_TMDP_REG6 0x48d4 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6 0x49d4 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6 0x49f4 +#define CAR_mmUNIPHY_TPG_CONTROL 0x48d5 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL 0x49d5 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL 0x49f5 +#define CAR_mmUNIPHY_TPG_SEED 0x48d6 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED 0x49d6 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED 0x49f6 +#define CAR_mmUNIPHY_DEBUG 0x48d7 +#define CAR_mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7 +#define CAR_mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7 +#define CAR_mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917 +#define CAR_mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937 +#define CAR_mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957 +#define CAR_mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977 +#define CAR_mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997 +#define CAR_mmBPHYC_UNIPHY7_UNIPHY_DEBUG 0x49d7 +#define CAR_mmBPHYC_UNIPHY8_UNIPHY_DEBUG 0x49f7 +#define CAR_mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define CAR_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define CAR_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 +#define CAR_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 +#define CAR_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define CAR_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 +#define CAR_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 +#define CAR_mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define CAR_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define CAR_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 +#define CAR_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 +#define CAR_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define CAR_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 +#define CAR_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 +#define CAR_mmDPG_WATERMARK_MASK_CONTROL 0x1b32 +#define CAR_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 +#define CAR_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 +#define CAR_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 +#define CAR_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 +#define CAR_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 +#define CAR_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 +#define CAR_mmDPG_PIPE_URGENCY_CONTROL 0x1b33 +#define CAR_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 +#define CAR_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 +#define CAR_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 +#define CAR_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define CAR_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 +#define CAR_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 +#define CAR_mmDPG_PIPE_DPM_CONTROL 0x1b34 +#define CAR_mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 +#define CAR_mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 +#define CAR_mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 +#define CAR_mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 +#define CAR_mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 +#define CAR_mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 +#define CAR_mmDPG_PIPE_STUTTER_CONTROL 0x1b35 +#define CAR_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 +#define CAR_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 +#define CAR_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 +#define CAR_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define CAR_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 +#define CAR_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 +#define CAR_mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define CAR_mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define CAR_mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 +#define CAR_mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 +#define CAR_mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define CAR_mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 +#define CAR_mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 +#define CAR_mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define CAR_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define CAR_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 +#define CAR_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 +#define CAR_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define CAR_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 +#define CAR_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 +#define CAR_mmDPG_REPEATER_PROGRAM 0x1b3a +#define CAR_mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a +#define CAR_mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a +#define CAR_mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a +#define CAR_mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a +#define CAR_mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a +#define CAR_mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a +#define CAR_mmDPG_HW_DEBUG_A 0x1b3b +#define CAR_mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b +#define CAR_mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b +#define CAR_mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b +#define CAR_mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b +#define CAR_mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b +#define CAR_mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b +#define CAR_mmDPG_HW_DEBUG_B 0x1b3c +#define CAR_mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c +#define CAR_mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c +#define CAR_mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c +#define CAR_mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c +#define CAR_mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c +#define CAR_mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c +#define CAR_mmDPG_HW_DEBUG_11 0x1b3d +#define CAR_mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d +#define CAR_mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d +#define CAR_mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d +#define CAR_mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d +#define CAR_mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d +#define CAR_mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d +#define CAR_mmDPG_CHK_PRE_PROC_CNTL 0x1b3e +#define CAR_mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x1b3e +#define CAR_mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x1d3e +#define CAR_mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x1f3e +#define CAR_mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x413e +#define CAR_mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x433e +#define CAR_mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x453e +#define CAR_mmDPG_TEST_DEBUG_INDEX 0x1b38 +#define CAR_mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 +#define CAR_mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 +#define CAR_mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 +#define CAR_mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 +#define CAR_mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 +#define CAR_mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 +#define CAR_mmDPG_TEST_DEBUG_DATA 0x1b39 +#define CAR_mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 +#define CAR_mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 +#define CAR_mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 +#define CAR_mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 +#define CAR_mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 +#define CAR_mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 +#define CAR_mmDPGV0_PIPE_ARBITRATION_CONTROL1 0x4730 +#define CAR_mmDPGV1_PIPE_ARBITRATION_CONTROL1 0x473d +#define CAR_mmDPGV0_PIPE_ARBITRATION_CONTROL2 0x4731 +#define CAR_mmDPGV1_PIPE_ARBITRATION_CONTROL2 0x473e +#define CAR_mmDPGV0_WATERMARK_MASK_CONTROL 0x4732 +#define CAR_mmDPGV1_WATERMARK_MASK_CONTROL 0x473f +#define CAR_mmDPGV0_PIPE_URGENCY_CONTROL 0x4733 +#define CAR_mmDPGV1_PIPE_URGENCY_CONTROL 0x4740 +#define CAR_mmDPGV0_PIPE_DPM_CONTROL 0x4734 +#define CAR_mmDPGV1_PIPE_DPM_CONTROL 0x4741 +#define CAR_mmDPGV0_PIPE_STUTTER_CONTROL 0x4735 +#define CAR_mmDPGV1_PIPE_STUTTER_CONTROL 0x4742 +#define CAR_mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define CAR_mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743 +#define CAR_mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define CAR_mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744 +#define CAR_mmDPGV0_REPEATER_PROGRAM 0x4738 +#define CAR_mmDPGV1_REPEATER_PROGRAM 0x4745 +#define CAR_mmDPGV0_HW_DEBUG_A 0x4739 +#define CAR_mmDPGV1_HW_DEBUG_A 0x4746 +#define CAR_mmDPGV0_HW_DEBUG_B 0x473a +#define CAR_mmDPGV1_HW_DEBUG_B 0x4747 +#define CAR_mmDPGV0_HW_DEBUG_11 0x473b +#define CAR_mmDPGV1_HW_DEBUG_11 0x4748 +#define CAR_mmDPGV0_CHK_PRE_PROC_CNTL 0x473c +#define CAR_mmDPGV1_CHK_PRE_PROC_CNTL 0x4749 +#define CAR_mmDPGV_TEST_DEBUG_INDEX 0x474e +#define CAR_mmDPGV_TEST_DEBUG_DATA 0x474f +#define CAR_ixDPGV0_DEBUG00_DMIFARB 0x1 +#define CAR_ixDPGV1_DEBUG00_DMIFARB 0x6a +#define CAR_ixDPGV0_DEBUG01_DMIFARB 0x2 +#define CAR_ixDPGV1_DEBUG01_DMIFARB 0x6b +#define CAR_ixDPGV0_DEBUG02_DMIFARB 0x3 +#define CAR_ixDPGV1_DEBUG02_DMIFARB 0x6c +#define CAR_ixDPGV0_DEBUG03_DMIFARB 0x4 +#define CAR_ixDPGV1_DEBUG03_DMIFARB 0x6d +#define CAR_ixDPGV0_DEBUG04_DMIFARB 0x5 +#define CAR_ixDPGV1_DEBUG04_DMIFARB 0x6e +#define CAR_ixDPGV0_DEBUG00 0x6 +#define CAR_ixDPGV1_DEBUG00 0x6f +#define CAR_ixDPGV0_DEBUG01 0x7 +#define CAR_ixDPGV1_DEBUG01 0x70 +#define CAR_ixDPGV0_DEBUG02 0x8 +#define CAR_ixDPGV1_DEBUG02 0x71 +#define CAR_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define CAR_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define CAR_ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 +#define CAR_ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 +#define CAR_ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define CAR_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 +#define CAR_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 +#define CAR_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a +#define CAR_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b +#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c +#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d +#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e +#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f +#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 +#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 +#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 +#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 +#define CAR_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 +#define CAR_mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 +#define CAR_mmAZALIA_F0_CODEC_DEBUG 0x1836 +#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 +#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 +#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 +#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a +#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b +#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c +#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d +#define CAR_mmGLOBAL_CAPABILITIES 0x0 +#define CAR_mmMINOR_VERSION 0x0 +#define CAR_mmMAJOR_VERSION 0x0 +#define CAR_mmOUTPUT_PAYLOAD_CAPABILITY 0x1 +#define CAR_mmINPUT_PAYLOAD_CAPABILITY 0x1 +#define CAR_mmGLOBAL_CONTROL 0x2 +#define CAR_mmWAKE_ENABLE 0x3 +#define CAR_mmSTATE_CHANGE_STATUS 0x3 +#define CAR_mmGLOBAL_STATUS 0x4 +#define CAR_mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define CAR_mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define CAR_mmINTERRUPT_CONTROL 0x8 +#define CAR_mmINTERRUPT_STATUS 0x9 +#define CAR_mmWALL_CLOCK_COUNTER 0xc +#define CAR_mmSTREAM_SYNCHRONIZATION 0xe +#define CAR_mmCORB_LOWER_BASE_ADDRESS 0x10 +#define CAR_mmCORB_UPPER_BASE_ADDRESS 0x11 +#define CAR_mmCORB_WRITE_POINTER 0x12 +#define CAR_mmCORB_READ_POINTER 0x12 +#define CAR_mmCORB_CONTROL 0x13 +#define CAR_mmCORB_STATUS 0x13 +#define CAR_mmCORB_SIZE 0x13 +#define CAR_mmRIRB_LOWER_BASE_ADDRESS 0x14 +#define CAR_mmRIRB_UPPER_BASE_ADDRESS 0x15 +#define CAR_mmRIRB_WRITE_POINTER 0x16 +#define CAR_mmRESPONSE_INTERRUPT_COUNT 0x16 +#define CAR_mmRIRB_CONTROL 0x17 +#define CAR_mmRIRB_STATUS 0x17 +#define CAR_mmRIRB_SIZE 0x17 +#define CAR_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 +#define CAR_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define CAR_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define CAR_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 +#define CAR_mmIMMEDIATE_COMMAND_STATUS 0x1a +#define CAR_mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c +#define CAR_mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d +#define CAR_mmWALL_CLOCK_COUNTER_ALIAS 0x80c +#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 +#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 +#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 +#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 +#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 +#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 +#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 +#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 +#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 +#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define CAR_ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define CAR_ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define CAR_ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define CAR_ixAUDIO_DESCRIPTOR0 0x1 +#define CAR_ixAUDIO_DESCRIPTOR1 0x2 +#define CAR_ixAUDIO_DESCRIPTOR2 0x3 +#define CAR_ixAUDIO_DESCRIPTOR3 0x4 +#define CAR_ixAUDIO_DESCRIPTOR4 0x5 +#define CAR_ixAUDIO_DESCRIPTOR5 0x6 +#define CAR_ixAUDIO_DESCRIPTOR6 0x7 +#define CAR_ixAUDIO_DESCRIPTOR7 0x8 +#define CAR_ixAUDIO_DESCRIPTOR8 0x9 +#define CAR_ixAUDIO_DESCRIPTOR9 0xa +#define CAR_ixAUDIO_DESCRIPTOR10 0xb +#define CAR_ixAUDIO_DESCRIPTOR11 0xc +#define CAR_ixAUDIO_DESCRIPTOR12 0xd +#define CAR_ixAUDIO_DESCRIPTOR13 0xe +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 +#define CAR_ixSINK_DESCRIPTION0 0x5 +#define CAR_ixSINK_DESCRIPTION1 0x6 +#define CAR_ixSINK_DESCRIPTION2 0x7 +#define CAR_ixSINK_DESCRIPTION3 0x8 +#define CAR_ixSINK_DESCRIPTION4 0x9 +#define CAR_ixSINK_DESCRIPTION5 0xa +#define CAR_ixSINK_DESCRIPTION6 0xb +#define CAR_ixSINK_DESCRIPTION7 0xc +#define CAR_ixSINK_DESCRIPTION8 0xd +#define CAR_ixSINK_DESCRIPTION9 0xe +#define CAR_ixSINK_DESCRIPTION10 0xf +#define CAR_ixSINK_DESCRIPTION11 0x10 +#define CAR_ixSINK_DESCRIPTION12 0x11 +#define CAR_ixSINK_DESCRIPTION13 0x12 +#define CAR_ixSINK_DESCRIPTION14 0x13 +#define CAR_ixSINK_DESCRIPTION15 0x14 +#define CAR_ixSINK_DESCRIPTION16 0x15 +#define CAR_ixSINK_DESCRIPTION17 0x16 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define CAR_ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define CAR_mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 +#define CAR_mmAZALIA_AUDIO_DTO 0x17e5 +#define CAR_mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 +#define CAR_mmAZALIA_SCLK_CONTROL 0x17e7 +#define CAR_mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 +#define CAR_mmAZALIA_DATA_DMA_CONTROL 0x17e9 +#define CAR_mmAZALIA_BDL_DMA_CONTROL 0x17ea +#define CAR_mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb +#define CAR_mmAZALIA_CORB_DMA_CONTROL 0x17ec +#define CAR_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 +#define CAR_mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 +#define CAR_mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 +#define CAR_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 +#define CAR_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 +#define CAR_mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 +#define CAR_mmAZALIA_CONTROLLER_DEBUG 0x17f9 +#define CAR_mmAZALIA_MEM_PWR_CTRL 0x1810 +#define CAR_mmAZALIA_MEM_PWR_STATUS 0x1811 +#define CAR_mmDCI_PG_DEBUG_CONFIG 0x1812 +#define CAR_mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb +#define CAR_mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc +#define CAR_mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd +#define CAR_mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe +#define CAR_mmAZALIA_INPUT_CRC0_RESULT 0x17ff +#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 +#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 +#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 +#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 +#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 +#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 +#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 +#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 +#define CAR_mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 +#define CAR_mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 +#define CAR_mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 +#define CAR_mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 +#define CAR_mmAZALIA_INPUT_CRC1_RESULT 0x1804 +#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 +#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 +#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 +#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 +#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 +#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 +#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 +#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 +#define CAR_mmAZALIA_CRC0_CONTROL0 0x1805 +#define CAR_mmAZALIA_CRC0_CONTROL1 0x1806 +#define CAR_mmAZALIA_CRC0_CONTROL2 0x1807 +#define CAR_mmAZALIA_CRC0_CONTROL3 0x1808 +#define CAR_mmAZALIA_CRC0_RESULT 0x1809 +#define CAR_ixAZALIA_CRC0_CHANNEL0 0x0 +#define CAR_ixAZALIA_CRC0_CHANNEL1 0x1 +#define CAR_ixAZALIA_CRC0_CHANNEL2 0x2 +#define CAR_ixAZALIA_CRC0_CHANNEL3 0x3 +#define CAR_ixAZALIA_CRC0_CHANNEL4 0x4 +#define CAR_ixAZALIA_CRC0_CHANNEL5 0x5 +#define CAR_ixAZALIA_CRC0_CHANNEL6 0x6 +#define CAR_ixAZALIA_CRC0_CHANNEL7 0x7 +#define CAR_mmAZALIA_CRC1_CONTROL0 0x180a +#define CAR_mmAZALIA_CRC1_CONTROL1 0x180b +#define CAR_mmAZALIA_CRC1_CONTROL2 0x180c +#define CAR_mmAZALIA_CRC1_CONTROL3 0x180d +#define CAR_mmAZALIA_CRC1_RESULT 0x180e +#define CAR_ixAZALIA_CRC1_CHANNEL0 0x0 +#define CAR_ixAZALIA_CRC1_CHANNEL1 0x1 +#define CAR_ixAZALIA_CRC1_CHANNEL2 0x2 +#define CAR_ixAZALIA_CRC1_CHANNEL3 0x3 +#define CAR_ixAZALIA_CRC1_CHANNEL4 0x4 +#define CAR_ixAZALIA_CRC1_CHANNEL5 0x5 +#define CAR_ixAZALIA_CRC1_CHANNEL6 0x6 +#define CAR_ixAZALIA_CRC1_CHANNEL7 0x7 +#define CAR_mmAZ_TEST_DEBUG_INDEX 0x181f +#define CAR_mmAZ_TEST_DEBUG_DATA 0x1820 +#define CAR_mmAZALIA_STREAM_INDEX 0x1780 +#define CAR_mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 +#define CAR_mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 +#define CAR_mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 +#define CAR_mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 +#define CAR_mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 +#define CAR_mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a +#define CAR_mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c +#define CAR_mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e +#define CAR_mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 +#define CAR_mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 +#define CAR_mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 +#define CAR_mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 +#define CAR_mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 +#define CAR_mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca +#define CAR_mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc +#define CAR_mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce +#define CAR_mmAZALIA_STREAM_DATA 0x1781 +#define CAR_mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 +#define CAR_mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 +#define CAR_mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 +#define CAR_mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 +#define CAR_mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 +#define CAR_mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b +#define CAR_mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d +#define CAR_mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f +#define CAR_mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 +#define CAR_mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 +#define CAR_mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 +#define CAR_mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 +#define CAR_mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 +#define CAR_mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb +#define CAR_mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd +#define CAR_mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf +#define CAR_ixAZALIA_FIFO_SIZE_CONTROL 0x0 +#define CAR_ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 +#define CAR_ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 +#define CAR_ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 +#define CAR_ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 +#define CAR_ixAZALIA_STREAM_DEBUG 0x5 +#define CAR_mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define CAR_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define CAR_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac +#define CAR_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 +#define CAR_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 +#define CAR_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 +#define CAR_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc +#define CAR_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 +#define CAR_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 +#define CAR_mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define CAR_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define CAR_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad +#define CAR_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 +#define CAR_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 +#define CAR_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 +#define CAR_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd +#define CAR_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 +#define CAR_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd +#define CAR_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe +#define CAR_ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define CAR_ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 +#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a +#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b +#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c +#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d +#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e +#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f +#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 +#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 +#define CAR_ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 +#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a +#define CAR_ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b +#define CAR_ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c +#define CAR_ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d +#define CAR_ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e +#define CAR_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define CAR_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define CAR_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 +#define CAR_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc +#define CAR_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 +#define CAR_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 +#define CAR_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 +#define CAR_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec +#define CAR_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 +#define CAR_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define CAR_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define CAR_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 +#define CAR_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd +#define CAR_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 +#define CAR_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 +#define CAR_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 +#define CAR_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed +#define CAR_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 +#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 +#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 +#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 +#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 +#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define CAR_mmBLND_CONTROL 0x1b6d +#define CAR_mmBLND0_BLND_CONTROL 0x1b6d +#define CAR_mmBLND1_BLND_CONTROL 0x1d6d +#define CAR_mmBLND2_BLND_CONTROL 0x1f6d +#define CAR_mmBLND3_BLND_CONTROL 0x416d +#define CAR_mmBLND4_BLND_CONTROL 0x436d +#define CAR_mmBLND5_BLND_CONTROL 0x456d +#define CAR_mmBLND_SM_CONTROL2 0x1b6e +#define CAR_mmBLND0_BLND_SM_CONTROL2 0x1b6e +#define CAR_mmBLND1_BLND_SM_CONTROL2 0x1d6e +#define CAR_mmBLND2_BLND_SM_CONTROL2 0x1f6e +#define CAR_mmBLND3_BLND_SM_CONTROL2 0x416e +#define CAR_mmBLND4_BLND_SM_CONTROL2 0x436e +#define CAR_mmBLND5_BLND_SM_CONTROL2 0x456e +#define CAR_mmBLND_CONTROL2 0x1b6f +#define CAR_mmBLND0_BLND_CONTROL2 0x1b6f +#define CAR_mmBLND1_BLND_CONTROL2 0x1d6f +#define CAR_mmBLND2_BLND_CONTROL2 0x1f6f +#define CAR_mmBLND3_BLND_CONTROL2 0x416f +#define CAR_mmBLND4_BLND_CONTROL2 0x436f +#define CAR_mmBLND5_BLND_CONTROL2 0x456f +#define CAR_mmBLND_UPDATE 0x1b70 +#define CAR_mmBLND0_BLND_UPDATE 0x1b70 +#define CAR_mmBLND1_BLND_UPDATE 0x1d70 +#define CAR_mmBLND2_BLND_UPDATE 0x1f70 +#define CAR_mmBLND3_BLND_UPDATE 0x4170 +#define CAR_mmBLND4_BLND_UPDATE 0x4370 +#define CAR_mmBLND5_BLND_UPDATE 0x4570 +#define CAR_mmBLND_UNDERFLOW_INTERRUPT 0x1b71 +#define CAR_mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 +#define CAR_mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 +#define CAR_mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 +#define CAR_mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 +#define CAR_mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 +#define CAR_mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 +#define CAR_mmBLND_V_UPDATE_LOCK 0x1b73 +#define CAR_mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 +#define CAR_mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 +#define CAR_mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 +#define CAR_mmBLND3_BLND_V_UPDATE_LOCK 0x4173 +#define CAR_mmBLND4_BLND_V_UPDATE_LOCK 0x4373 +#define CAR_mmBLND5_BLND_V_UPDATE_LOCK 0x4573 +#define CAR_mmBLND_REG_UPDATE_STATUS 0x1b77 +#define CAR_mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 +#define CAR_mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 +#define CAR_mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 +#define CAR_mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 +#define CAR_mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 +#define CAR_mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 +#define CAR_mmBLND_DEBUG 0x1b74 +#define CAR_mmBLND0_BLND_DEBUG 0x1b74 +#define CAR_mmBLND1_BLND_DEBUG 0x1d74 +#define CAR_mmBLND2_BLND_DEBUG 0x1f74 +#define CAR_mmBLND3_BLND_DEBUG 0x4174 +#define CAR_mmBLND4_BLND_DEBUG 0x4374 +#define CAR_mmBLND5_BLND_DEBUG 0x4574 +#define CAR_mmBLND_TEST_DEBUG_INDEX 0x1b75 +#define CAR_mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 +#define CAR_mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 +#define CAR_mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 +#define CAR_mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 +#define CAR_mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 +#define CAR_mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 +#define CAR_mmBLND_TEST_DEBUG_DATA 0x1b76 +#define CAR_mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 +#define CAR_mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 +#define CAR_mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 +#define CAR_mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 +#define CAR_mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 +#define CAR_mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 +#define CAR_mmWB_ENABLE 0x5e18 +#define CAR_mmWB_EC_CONFIG 0x5e19 +#define CAR_mmCNV_MODE 0x5e1a +#define CAR_mmCNV_WINDOW_START 0x5e1b +#define CAR_mmCNV_WINDOW_SIZE 0x5e1c +#define CAR_mmCNV_UPDATE 0x5e1d +#define CAR_mmCNV_SOURCE_SIZE 0x5e1e +#define CAR_mmCNV_CSC_CONTROL 0x5e1f +#define CAR_mmCNV_CSC_C11_C12 0x5e20 +#define CAR_mmCNV_CSC_C13_C14 0x5e21 +#define CAR_mmCNV_CSC_C21_C22 0x5e22 +#define CAR_mmCNV_CSC_C23_C24 0x5e23 +#define CAR_mmCNV_CSC_C31_C32 0x5e24 +#define CAR_mmCNV_CSC_C33_C34 0x5e25 +#define CAR_mmCNV_CSC_ROUND_OFFSET_R 0x5e26 +#define CAR_mmCNV_CSC_ROUND_OFFSET_G 0x5e27 +#define CAR_mmCNV_CSC_ROUND_OFFSET_B 0x5e28 +#define CAR_mmCNV_CSC_CLAMP_R 0x5e29 +#define CAR_mmCNV_CSC_CLAMP_G 0x5e2a +#define CAR_mmCNV_CSC_CLAMP_B 0x5e2b +#define CAR_mmCNV_TEST_CNTL 0x5e2c +#define CAR_mmCNV_TEST_CRC_RED 0x5e2d +#define CAR_mmCNV_TEST_CRC_GREEN 0x5e2e +#define CAR_mmCNV_TEST_CRC_BLUE 0x5e2f +#define CAR_mmWB_DEBUG_CTRL 0x5e30 +#define CAR_mmWB_DBG_MODE 0x5e31 +#define CAR_mmWB_HW_DEBUG 0x5e32 +#define CAR_mmCNV_INPUT_SELECT 0x5e33 +#define CAR_mmWB_SOFT_RESET 0x5e36 +#define CAR_mmCNV_TEST_DEBUG_INDEX 0x5e34 +#define CAR_mmCNV_TEST_DEBUG_DATA 0x5e35 +#define CAR_mmDCFE_CLOCK_CONTROL 0x1b00 +#define CAR_mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 +#define CAR_mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 +#define CAR_mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 +#define CAR_mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 +#define CAR_mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 +#define CAR_mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 +#define CAR_mmDCFE_SOFT_RESET 0x1b01 +#define CAR_mmDCFE0_DCFE_SOFT_RESET 0x1b01 +#define CAR_mmDCFE1_DCFE_SOFT_RESET 0x1d01 +#define CAR_mmDCFE2_DCFE_SOFT_RESET 0x1f01 +#define CAR_mmDCFE3_DCFE_SOFT_RESET 0x4101 +#define CAR_mmDCFE4_DCFE_SOFT_RESET 0x4301 +#define CAR_mmDCFE5_DCFE_SOFT_RESET 0x4501 +#define CAR_mmDCFE_DBG_CONFIG 0x1b02 +#define CAR_mmDCFE0_DCFE_DBG_CONFIG 0x1b02 +#define CAR_mmDCFE1_DCFE_DBG_CONFIG 0x1d02 +#define CAR_mmDCFE2_DCFE_DBG_CONFIG 0x1f02 +#define CAR_mmDCFE3_DCFE_DBG_CONFIG 0x4102 +#define CAR_mmDCFE4_DCFE_DBG_CONFIG 0x4302 +#define CAR_mmDCFE5_DCFE_DBG_CONFIG 0x4502 +#define CAR_mmDCFE_MEM_PWR_CTRL 0x1b03 +#define CAR_mmDCFE0_DCFE_MEM_PWR_CTRL 0x1b03 +#define CAR_mmDCFE1_DCFE_MEM_PWR_CTRL 0x1d03 +#define CAR_mmDCFE2_DCFE_MEM_PWR_CTRL 0x1f03 +#define CAR_mmDCFE3_DCFE_MEM_PWR_CTRL 0x4103 +#define CAR_mmDCFE4_DCFE_MEM_PWR_CTRL 0x4303 +#define CAR_mmDCFE5_DCFE_MEM_PWR_CTRL 0x4503 +#define CAR_mmDCFE_MEM_PWR_CTRL2 0x1b04 +#define CAR_mmDCFE0_DCFE_MEM_PWR_CTRL2 0x1b04 +#define CAR_mmDCFE1_DCFE_MEM_PWR_CTRL2 0x1d04 +#define CAR_mmDCFE2_DCFE_MEM_PWR_CTRL2 0x1f04 +#define CAR_mmDCFE3_DCFE_MEM_PWR_CTRL2 0x4104 +#define CAR_mmDCFE4_DCFE_MEM_PWR_CTRL2 0x4304 +#define CAR_mmDCFE5_DCFE_MEM_PWR_CTRL2 0x4504 +#define CAR_mmDCFE_MEM_PWR_STATUS 0x1b05 +#define CAR_mmDCFE0_DCFE_MEM_PWR_STATUS 0x1b05 +#define CAR_mmDCFE1_DCFE_MEM_PWR_STATUS 0x1d05 +#define CAR_mmDCFE2_DCFE_MEM_PWR_STATUS 0x1f05 +#define CAR_mmDCFE3_DCFE_MEM_PWR_STATUS 0x4105 +#define CAR_mmDCFE4_DCFE_MEM_PWR_STATUS 0x4305 +#define CAR_mmDCFE5_DCFE_MEM_PWR_STATUS 0x4505 +#define CAR_mmDCFE_MISC 0x1b06 +#define CAR_mmDCFE0_DCFE_MISC 0x1b06 +#define CAR_mmDCFE1_DCFE_MISC 0x1d06 +#define CAR_mmDCFE2_DCFE_MISC 0x1f06 +#define CAR_mmDCFE3_DCFE_MISC 0x4106 +#define CAR_mmDCFE4_DCFE_MISC 0x4306 +#define CAR_mmDCFE5_DCFE_MISC 0x4506 +#define CAR_mmDCFEV_CLOCK_CONTROL 0x46f4 +#define CAR_mmDCFEV_SOFT_RESET 0x46f5 +#define CAR_mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 +#define CAR_mmDCFEV_DBG_CONFIG 0x46f7 +#define CAR_mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 +#define CAR_mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 +#define CAR_mmDCFEV_MEM_PWR_CTRL 0x46fa +#define CAR_mmDCFEV_MEM_PWR_CTRL2 0x46fb +#define CAR_mmDCFEV_MEM_PWR_STATUS 0x46fc +#define CAR_mmDCFEV_DMIFV_DEBUG 0x46fd +#define CAR_mmDCFEV_MISC 0x46fe +#define CAR_mmDC_HPD_INT_STATUS 0x1898 +#define CAR_mmHPD0_DC_HPD_INT_STATUS 0x1898 +#define CAR_mmHPD1_DC_HPD_INT_STATUS 0x18a0 +#define CAR_mmHPD2_DC_HPD_INT_STATUS 0x18a8 +#define CAR_mmHPD3_DC_HPD_INT_STATUS 0x18b0 +#define CAR_mmHPD4_DC_HPD_INT_STATUS 0x18b8 +#define CAR_mmHPD5_DC_HPD_INT_STATUS 0x18c0 +#define CAR_mmDC_HPD_INT_CONTROL 0x1899 +#define CAR_mmHPD0_DC_HPD_INT_CONTROL 0x1899 +#define CAR_mmHPD1_DC_HPD_INT_CONTROL 0x18a1 +#define CAR_mmHPD2_DC_HPD_INT_CONTROL 0x18a9 +#define CAR_mmHPD3_DC_HPD_INT_CONTROL 0x18b1 +#define CAR_mmHPD4_DC_HPD_INT_CONTROL 0x18b9 +#define CAR_mmHPD5_DC_HPD_INT_CONTROL 0x18c1 +#define CAR_mmDC_HPD_CONTROL 0x189a +#define CAR_mmHPD0_DC_HPD_CONTROL 0x189a +#define CAR_mmHPD1_DC_HPD_CONTROL 0x18a2 +#define CAR_mmHPD2_DC_HPD_CONTROL 0x18aa +#define CAR_mmHPD3_DC_HPD_CONTROL 0x18b2 +#define CAR_mmHPD4_DC_HPD_CONTROL 0x18ba +#define CAR_mmHPD5_DC_HPD_CONTROL 0x18c2 +#define CAR_mmDC_HPD_FAST_TRAIN_CNTL 0x189b +#define CAR_mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b +#define CAR_mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 +#define CAR_mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab +#define CAR_mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 +#define CAR_mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb +#define CAR_mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 +#define CAR_mmDC_HPD_TOGGLE_FILT_CNTL 0x189c +#define CAR_mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c +#define CAR_mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 +#define CAR_mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac +#define CAR_mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 +#define CAR_mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc +#define CAR_mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 +#define CAR_mmDCO_SCRATCH0 0x184e +#define CAR_mmDCO_SCRATCH1 0x184f +#define CAR_mmDCO_SCRATCH2 0x1850 +#define CAR_mmDCO_SCRATCH3 0x1851 +#define CAR_mmDCO_SCRATCH4 0x1852 +#define CAR_mmDCO_SCRATCH5 0x1853 +#define CAR_mmDCO_SCRATCH6 0x1854 +#define CAR_mmDCO_SCRATCH7 0x1855 +#define CAR_mmDCE_VCE_CONTROL 0x1856 +#define CAR_mmDISP_INTERRUPT_STATUS 0x1857 +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 +#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE10 0x1875 +#define CAR_mmDCO_MEM_PWR_STATUS 0x1861 +#define CAR_mmDCO_MEM_PWR_STATUS1 0x1874 +#define CAR_mmDCO_MEM_PWR_CTRL 0x1862 +#define CAR_mmDCO_MEM_PWR_CTRL2 0x1863 +#define CAR_mmDCO_CLK_CNTL 0x1864 +#define CAR_mmDCO_CLK_CNTL2 0x1876 +#define CAR_mmDCO_CLK_CNTL3 0x1877 +#define CAR_mmDPDBG_CNTL 0x1866 +#define CAR_mmDPDBG_INTERRUPT 0x1867 +#define CAR_mmDCO_POWER_MANAGEMENT_CNTL 0x1868 +#define CAR_mmDCO_SOFT_RESET 0x1871 +#define CAR_mmDIG_SOFT_RESET 0x1872 +#define CAR_mmDIG_SOFT_RESET_2 0x186a +#define CAR_mmDCO_STEREOSYNC_SEL 0x186e +#define CAR_mmDCO_TEST_DEBUG_INDEX 0x186f +#define CAR_mmDCO_TEST_DEBUG_DATA 0x1870 +#define CAR_mmDC_I2C_CONTROL 0x16d4 +#define CAR_mmDC_I2C_ARBITRATION 0x16d5 +#define CAR_mmDC_I2C_INTERRUPT_CONTROL 0x16d6 +#define CAR_mmDC_I2C_SW_STATUS 0x16d7 +#define CAR_mmDC_I2C_DDC1_HW_STATUS 0x16d8 +#define CAR_mmDC_I2C_DDC2_HW_STATUS 0x16d9 +#define CAR_mmDC_I2C_DDC3_HW_STATUS 0x16da +#define CAR_mmDC_I2C_DDC4_HW_STATUS 0x16db +#define CAR_mmDC_I2C_DDC5_HW_STATUS 0x16dc +#define CAR_mmDC_I2C_DDC6_HW_STATUS 0x16dd +#define CAR_mmDC_I2C_DDC1_SPEED 0x16de +#define CAR_mmDC_I2C_DDC1_SETUP 0x16df +#define CAR_mmDC_I2C_DDC2_SPEED 0x16e0 +#define CAR_mmDC_I2C_DDC2_SETUP 0x16e1 +#define CAR_mmDC_I2C_DDC3_SPEED 0x16e2 +#define CAR_mmDC_I2C_DDC3_SETUP 0x16e3 +#define CAR_mmDC_I2C_DDC4_SPEED 0x16e4 +#define CAR_mmDC_I2C_DDC4_SETUP 0x16e5 +#define CAR_mmDC_I2C_DDC5_SPEED 0x16e6 +#define CAR_mmDC_I2C_DDC5_SETUP 0x16e7 +#define CAR_mmDC_I2C_DDC6_SPEED 0x16e8 +#define CAR_mmDC_I2C_DDC6_SETUP 0x16e9 +#define CAR_mmDC_I2C_TRANSACTION0 0x16ea +#define CAR_mmDC_I2C_TRANSACTION1 0x16eb +#define CAR_mmDC_I2C_TRANSACTION2 0x16ec +#define CAR_mmDC_I2C_TRANSACTION3 0x16ed +#define CAR_mmDC_I2C_DATA 0x16ee +#define CAR_mmDC_I2C_DDCVGA_HW_STATUS 0x16ef +#define CAR_mmDC_I2C_DDCVGA_SPEED 0x16f0 +#define CAR_mmDC_I2C_DDCVGA_SETUP 0x16f1 +#define CAR_mmDC_I2C_EDID_DETECT_CTRL 0x16f2 +#define CAR_mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 +#define CAR_mmGENERIC_I2C_CONTROL 0x16f4 +#define CAR_mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 +#define CAR_mmGENERIC_I2C_STATUS 0x16f6 +#define CAR_mmGENERIC_I2C_SPEED 0x16f7 +#define CAR_mmGENERIC_I2C_SETUP 0x16f8 +#define CAR_mmGENERIC_I2C_TRANSACTION 0x16f9 +#define CAR_mmGENERIC_I2C_DATA 0x16fa +#define CAR_mmGENERIC_I2C_PIN_SELECTION 0x16fb +#define CAR_mmGENERIC_I2C_PIN_DEBUG 0x16fc +#define CAR_mmBLNDV_CONTROL 0x476d +#define CAR_mmBLNDV_SM_CONTROL2 0x476e +#define CAR_mmBLNDV_CONTROL2 0x476f +#define CAR_mmBLNDV_UPDATE 0x4770 +#define CAR_mmBLNDV_UNDERFLOW_INTERRUPT 0x4771 +#define CAR_mmBLNDV_V_UPDATE_LOCK 0x4773 +#define CAR_mmBLNDV_REG_UPDATE_STATUS 0x4777 +#define CAR_mmBLNDV_DEBUG 0x4774 +#define CAR_mmBLNDV_TEST_DEBUG_INDEX 0x4775 +#define CAR_mmBLNDV_TEST_DEBUG_DATA 0x4776 +#define CAR_mmCRTCV_H_BLANK_EARLY_NUM 0x477d +#define CAR_mmCRTCV_H_TOTAL 0x4780 +#define CAR_mmCRTCV_H_BLANK_START_END 0x4781 +#define CAR_mmCRTCV_H_SYNC_A 0x4782 +#define CAR_mmCRTCV_H_SYNC_A_CNTL 0x4783 +#define CAR_mmCRTCV_H_SYNC_B 0x4784 +#define CAR_mmCRTCV_H_SYNC_B_CNTL 0x4785 +#define CAR_mmCRTCV_VBI_END 0x4786 +#define CAR_mmCRTCV_V_TOTAL 0x4787 +#define CAR_mmCRTCV_V_TOTAL_MIN 0x4788 +#define CAR_mmCRTCV_V_TOTAL_MAX 0x4789 +#define CAR_mmCRTCV_V_TOTAL_CONTROL 0x478a +#define CAR_mmCRTCV_V_TOTAL_INT_STATUS 0x478b +#define CAR_mmCRTCV_VSYNC_NOM_INT_STATUS 0x478c +#define CAR_mmCRTCV_V_BLANK_START_END 0x478d +#define CAR_mmCRTCV_V_SYNC_A 0x478e +#define CAR_mmCRTCV_V_SYNC_A_CNTL 0x478f +#define CAR_mmCRTCV_V_SYNC_B 0x4790 +#define CAR_mmCRTCV_V_SYNC_B_CNTL 0x4791 +#define CAR_mmCRTCV_DTMTEST_CNTL 0x4792 +#define CAR_mmCRTCV_DTMTEST_STATUS_POSITION 0x4793 +#define CAR_mmCRTCV_TRIGA_CNTL 0x4794 +#define CAR_mmCRTCV_TRIGA_MANUAL_TRIG 0x4795 +#define CAR_mmCRTCV_TRIGB_CNTL 0x4796 +#define CAR_mmCRTCV_TRIGB_MANUAL_TRIG 0x4797 +#define CAR_mmCRTCV_FORCE_COUNT_NOW_CNTL 0x4798 +#define CAR_mmCRTCV_FLOW_CONTROL 0x4799 +#define CAR_mmCRTCV_STEREO_FORCE_NEXT_EYE 0x479a +#define CAR_mmCRTCV_AVSYNC_COUNTER 0x479b +#define CAR_mmCRTCV_CONTROL 0x479c +#define CAR_mmCRTCV_BLANK_CONTROL 0x479d +#define CAR_mmCRTCV_INTERLACE_CONTROL 0x479e +#define CAR_mmCRTCV_INTERLACE_STATUS 0x479f +#define CAR_mmCRTCV_FIELD_INDICATION_CONTROL 0x47a0 +#define CAR_mmCRTCV_PIXEL_DATA_READBACK0 0x47a1 +#define CAR_mmCRTCV_PIXEL_DATA_READBACK1 0x47a2 +#define CAR_mmCRTCV_STATUS 0x47a3 +#define CAR_mmCRTCV_STATUS_POSITION 0x47a4 +#define CAR_mmCRTCV_NOM_VERT_POSITION 0x47a5 +#define CAR_mmCRTCV_STATUS_FRAME_COUNT 0x47a6 +#define CAR_mmCRTCV_STATUS_VF_COUNT 0x47a7 +#define CAR_mmCRTCV_STATUS_HV_COUNT 0x47a8 +#define CAR_mmCRTCV_COUNT_CONTROL 0x47a9 +#define CAR_mmCRTCV_COUNT_RESET 0x47aa +#define CAR_mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab +#define CAR_mmCRTCV_VERT_SYNC_CONTROL 0x47ac +#define CAR_mmCRTCV_STEREO_STATUS 0x47ad +#define CAR_mmCRTCV_STEREO_CONTROL 0x47ae +#define CAR_mmCRTCV_SNAPSHOT_STATUS 0x47af +#define CAR_mmCRTCV_SNAPSHOT_CONTROL 0x47b0 +#define CAR_mmCRTCV_SNAPSHOT_POSITION 0x47b1 +#define CAR_mmCRTCV_SNAPSHOT_FRAME 0x47b2 +#define CAR_mmCRTCV_START_LINE_CONTROL 0x47b3 +#define CAR_mmCRTCV_INTERRUPT_CONTROL 0x47b4 +#define CAR_mmCRTCV_UPDATE_LOCK 0x47b5 +#define CAR_mmCRTCV_DOUBLE_BUFFER_CONTROL 0x47b6 +#define CAR_mmCRTCV_VGA_PARAMETER_CAPTURE_MODE 0x47b7 +#define CAR_mmCRTCV_TEST_PATTERN_CONTROL 0x47ba +#define CAR_mmCRTCV_TEST_PATTERN_PARAMETERS 0x47bb +#define CAR_mmCRTCV_TEST_PATTERN_COLOR 0x47bc +#define CAR_mmCRTCV_MASTER_UPDATE_LOCK 0x47bd +#define CAR_mmCRTCV_MASTER_UPDATE_MODE 0x47be +#define CAR_mmCRTCV_MVP_INBAND_CNTL_INSERT 0x47bf +#define CAR_mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 +#define CAR_mmCRTCV_MVP_STATUS 0x47c1 +#define CAR_mmCRTCV_MASTER_EN 0x47c2 +#define CAR_mmCRTCV_ALLOW_STOP_OFF_V_CNT 0x47c3 +#define CAR_mmCRTCV_V_UPDATE_INT_STATUS 0x47c4 +#define CAR_mmCRTCV_OVERSCAN_COLOR 0x47c8 +#define CAR_mmCRTCV_OVERSCAN_COLOR_EXT 0x47c9 +#define CAR_mmCRTCV_BLANK_DATA_COLOR 0x47ca +#define CAR_mmCRTCV_BLANK_DATA_COLOR_EXT 0x47cb +#define CAR_mmCRTCV_BLACK_COLOR 0x47cc +#define CAR_mmCRTCV_BLACK_COLOR_EXT 0x47cd +#define CAR_mmCRTCV_VERTICAL_INTERRUPT0_POSITION 0x47ce +#define CAR_mmCRTCV_VERTICAL_INTERRUPT0_CONTROL 0x47cf +#define CAR_mmCRTCV_VERTICAL_INTERRUPT1_POSITION 0x47d0 +#define CAR_mmCRTCV_VERTICAL_INTERRUPT1_CONTROL 0x47d1 +#define CAR_mmCRTCV_VERTICAL_INTERRUPT2_POSITION 0x47d2 +#define CAR_mmCRTCV_VERTICAL_INTERRUPT2_CONTROL 0x47d3 +#define CAR_mmCRTCV_CRC_CNTL 0x47d4 +#define CAR_mmCRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5 +#define CAR_mmCRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6 +#define CAR_mmCRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7 +#define CAR_mmCRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8 +#define CAR_mmCRTCV_CRC0_DATA_RG 0x47d9 +#define CAR_mmCRTCV_CRC0_DATA_B 0x47da +#define CAR_mmCRTCV_CRC1_WINDOWA_X_CONTROL 0x47db +#define CAR_mmCRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc +#define CAR_mmCRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd +#define CAR_mmCRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de +#define CAR_mmCRTCV_CRC1_DATA_RG 0x47df +#define CAR_mmCRTCV_CRC1_DATA_B 0x47e0 +#define CAR_mmCRTCV_STATIC_SCREEN_CONTROL 0x47e7 +#define CAR_mmCRTCV_3D_STRUCTURE_CONTROL 0x4778 +#define CAR_mmCRTCV_GSL_VSYNC_GAP 0x4779 +#define CAR_mmCRTCV_GSL_WINDOW 0x477a +#define CAR_mmCRTCV_GSL_CONTROL 0x477b +#define CAR_mmCRTCV_TEST_DEBUG_INDEX 0x47c6 +#define CAR_mmCRTCV_TEST_DEBUG_DATA 0x47c7 +#define CAR_mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 +#define CAR_mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 +#define CAR_mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 +#define CAR_mmXDMA_INTERRUPT 0x3e3 +#define CAR_mmXDMA_CLOCK_GATING_CNTL 0x3e4 +#define CAR_mmXDMA_MEM_POWER_CNTL 0x3e6 +#define CAR_mmXDMA_IF_BIF_STATUS 0x3e7 +#define CAR_mmXDMA_PERF_MEAS_STATUS 0x3e8 +#define CAR_mmXDMA_IF_STATUS 0x3e9 +#define CAR_mmXDMA_TEST_DEBUG_INDEX 0x3ea +#define CAR_mmXDMA_TEST_DEBUG_DATA 0x3eb +#define CAR_mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 +#define CAR_mmXDMA_PG_CONTROL 0x3f9 +#define CAR_mmXDMA_PG_WDATA 0x3fa +#define CAR_mmXDMA_PG_STATUS 0x3fb +#define CAR_mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc +#define CAR_mmXDMA_AON_TEST_DEBUG_DATA 0x3fd +#define CAR_mmXDMA_MSTR_CNTL 0x3ec +#define CAR_mmXDMA_MSTR_STATUS 0x3ed +#define CAR_mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee +#define CAR_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef +#define CAR_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 +#define CAR_mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 +#define CAR_mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 +#define CAR_mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 +#define CAR_mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 +#define CAR_mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 +#define CAR_mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 +#define CAR_mmXDMA_MSTR_PIPE_CNTL 0x400 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 +#define CAR_mmXDMA_MSTR_READ_COMMAND 0x401 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 +#define CAR_mmXDMA_MSTR_CHANNEL_DIM 0x402 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 +#define CAR_mmXDMA_MSTR_HEIGHT 0x403 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 +#define CAR_mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 +#define CAR_mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 +#define CAR_mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 +#define CAR_mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 +#define CAR_mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 +#define CAR_mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 +#define CAR_mmXDMA_MSTR_CACHE 0x40a +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a +#define CAR_mmXDMA_MSTR_CHANNEL_START 0x40b +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b +#define CAR_mmXDMA_MSTR_PERFMEAS_STATUS 0x40e +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e +#define CAR_mmXDMA_MSTR_PERFMEAS_CNTL 0x40f +#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f +#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f +#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f +#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f +#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f +#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f +#define CAR_mmXDMA_SLV_CNTL 0x460 +#define CAR_mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 +#define CAR_mmXDMA_SLV_SLS_PITCH 0x462 +#define CAR_mmXDMA_SLV_READ_URGENT_CNTL 0x463 +#define CAR_mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 +#define CAR_mmXDMA_SLV_WB_RATE_CNTL 0x465 +#define CAR_mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 +#define CAR_mmXDMA_SLV_READ_LATENCY_AVE 0x467 +#define CAR_mmXDMA_SLV_PCIE_NACK_STATUS 0x468 +#define CAR_mmXDMA_SLV_MEM_NACK_STATUS 0x469 +#define CAR_mmXDMA_SLV_RDRET_BUF_STATUS 0x46a +#define CAR_mmXDMA_SLV_READ_LATENCY_TIMER 0x46b +#define CAR_mmXDMA_SLV_FLIP_PENDING 0x46c +#define CAR_mmXDMA_SLV_CHANNEL_CNTL 0x470 +#define CAR_mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 +#define CAR_mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 +#define CAR_mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 +#define CAR_mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 +#define CAR_mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 +#define CAR_mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 +#define CAR_mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define CAR_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define CAR_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 +#define CAR_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 +#define CAR_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 +#define CAR_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 +#define CAR_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 +#define CAR_mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define CAR_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define CAR_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a +#define CAR_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 +#define CAR_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a +#define CAR_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 +#define CAR_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a + +#endif /* DCE_11_0_D_H */ diff --git a/headers/private/graphics/radeon_hd/radeon_hd.h b/headers/private/graphics/radeon_hd/radeon_hd.h index d31f58ced5..b9ca70e535 100644 --- a/headers/private/graphics/radeon_hd/radeon_hd.h +++ b/headers/private/graphics/radeon_hd/radeon_hd.h @@ -14,13 +14,16 @@ #include "radeon_reg.h" -//#include "r500_reg.h" // Not used atm -#include "avivo_reg.h" -#include "r600_reg.h" -#include "r700_reg.h" -#include "evergreen_reg.h" -#include "si_reg.h" -#include "ni_reg.h" +//#include "r500_reg.h" // Not used atm. DCE 0 +#include "avivo_reg.h" // DCE 1 +#include "r600_reg.h" // DCE 2 +#include "r700_reg.h" // DCE 3 +#include "evergreen_reg.h" // DCE 4 +#include "ni_reg.h" // DCE 5 +#include "si_reg.h" // DCE 6 +#include "sea_reg.h" // DCE 8 +#include "vol_reg.h" // DCE 10 +#include "car_reg.h" // DCE 11 #include #include diff --git a/headers/private/graphics/radeon_hd/sea_reg.h b/headers/private/graphics/radeon_hd/sea_reg.h new file mode 100644 index 0000000000..21a31b17e1 --- /dev/null +++ b/headers/private/graphics/radeon_hd/sea_reg.h @@ -0,0 +1,5703 @@ +/* + * DCE_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_8_0_D_H +#define DCE_8_0_D_H + +#define SEA_mmPIPE0_PG_CONFIG 0x1760 +#define SEA_mmPIPE0_PG_ENABLE 0x1761 +#define SEA_mmPIPE0_PG_STATUS 0x1762 +#define SEA_mmPIPE1_PG_CONFIG 0x1764 +#define SEA_mmPIPE1_PG_ENABLE 0x1765 +#define SEA_mmPIPE1_PG_STATUS 0x1766 +#define SEA_mmPIPE2_PG_CONFIG 0x1768 +#define SEA_mmPIPE2_PG_ENABLE 0x1769 +#define SEA_mmPIPE2_PG_STATUS 0x176a +#define SEA_mmPIPE3_PG_CONFIG 0x176c +#define SEA_mmPIPE3_PG_ENABLE 0x176d +#define SEA_mmPIPE3_PG_STATUS 0x176e +#define SEA_mmPIPE4_PG_CONFIG 0x1770 +#define SEA_mmPIPE4_PG_ENABLE 0x1771 +#define SEA_mmPIPE4_PG_STATUS 0x1772 +#define SEA_mmPIPE5_PG_CONFIG 0x1774 +#define SEA_mmPIPE5_PG_ENABLE 0x1775 +#define SEA_mmPIPE5_PG_STATUS 0x1776 +#define SEA_mmDC_IP_REQUEST_CNTL 0x1778 +#define SEA_mmDC_PGFSM_CONFIG_REG 0x177c +#define SEA_mmDC_PGFSM_WRITE_REG 0x177d +#define SEA_mmDC_PGCNTL_STATUS_REG 0x177e +#define SEA_mmDCPG_TEST_DEBUG_INDEX 0x1779 +#define SEA_mmDCPG_TEST_DEBUG_DATA 0x177b +#define SEA_mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define SEA_mmBL1_PWM_USER_LEVEL 0x1629 +#define SEA_mmBL1_PWM_TARGET_ABM_LEVEL 0x162a +#define SEA_mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b +#define SEA_mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c +#define SEA_mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d +#define SEA_mmBL1_PWM_ABM_CNTL 0x162e +#define SEA_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f +#define SEA_mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define SEA_mmDC_ABM1_CNTL 0x1638 +#define SEA_mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a +#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b +#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c +#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d +#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e +#define SEA_mmDC_ABM1_ACE_THRES_12 0x163f +#define SEA_mmDC_ABM1_ACE_THRES_34 0x1640 +#define SEA_mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define SEA_mmDC_ABM1_DEBUG_MISC 0x1649 +#define SEA_mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a +#define SEA_mmDC_ABM1_HG_MISC_CTRL 0x164b +#define SEA_mmDC_ABM1_LS_SUM_OF_LUMA 0x164c +#define SEA_mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d +#define SEA_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e +#define SEA_mmDC_ABM1_LS_PIXEL_COUNT 0x164f +#define SEA_mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define SEA_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define SEA_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define SEA_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define SEA_mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define SEA_mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define SEA_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define SEA_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define SEA_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define SEA_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define SEA_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a +#define SEA_mmDC_ABM1_HG_RESULT_1 0x165b +#define SEA_mmDC_ABM1_HG_RESULT_2 0x165c +#define SEA_mmDC_ABM1_HG_RESULT_3 0x165d +#define SEA_mmDC_ABM1_HG_RESULT_4 0x165e +#define SEA_mmDC_ABM1_HG_RESULT_5 0x165f +#define SEA_mmDC_ABM1_HG_RESULT_6 0x1660 +#define SEA_mmDC_ABM1_HG_RESULT_7 0x1661 +#define SEA_mmDC_ABM1_HG_RESULT_8 0x1662 +#define SEA_mmDC_ABM1_HG_RESULT_9 0x1663 +#define SEA_mmDC_ABM1_HG_RESULT_10 0x1664 +#define SEA_mmDC_ABM1_HG_RESULT_11 0x1665 +#define SEA_mmDC_ABM1_HG_RESULT_12 0x1666 +#define SEA_mmDC_ABM1_HG_RESULT_13 0x1667 +#define SEA_mmDC_ABM1_HG_RESULT_14 0x1668 +#define SEA_mmDC_ABM1_HG_RESULT_15 0x1669 +#define SEA_mmDC_ABM1_HG_RESULT_16 0x166a +#define SEA_mmDC_ABM1_HG_RESULT_17 0x166b +#define SEA_mmDC_ABM1_HG_RESULT_18 0x166c +#define SEA_mmDC_ABM1_HG_RESULT_19 0x166d +#define SEA_mmDC_ABM1_HG_RESULT_20 0x166e +#define SEA_mmDC_ABM1_HG_RESULT_21 0x166f +#define SEA_mmDC_ABM1_HG_RESULT_22 0x1670 +#define SEA_mmDC_ABM1_HG_RESULT_23 0x1671 +#define SEA_mmDC_ABM1_HG_RESULT_24 0x1672 +#define SEA_mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b +#define SEA_mmDC_ABM1_BL_MASTER_LOCK 0x169c +#define SEA_mmABM_TEST_DEBUG_INDEX 0x169e +#define SEA_mmABM_TEST_DEBUG_DATA 0x169f +#define SEA_mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c +#define SEA_mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c +#define SEA_mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1e7c +#define SEA_mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417c +#define SEA_mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447c +#define SEA_mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477c +#define SEA_mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4a7c +#define SEA_mmCRTC_H_BLANK_EARLY_NUM 0x1b7d +#define SEA_mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d +#define SEA_mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1e7d +#define SEA_mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417d +#define SEA_mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447d +#define SEA_mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477d +#define SEA_mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4a7d +#define SEA_mmDCFE_DBG_SEL 0x1b7e +#define SEA_mmCRTC0_DCFE_DBG_SEL 0x1b7e +#define SEA_mmCRTC1_DCFE_DBG_SEL 0x1e7e +#define SEA_mmCRTC2_DCFE_DBG_SEL 0x417e +#define SEA_mmCRTC3_DCFE_DBG_SEL 0x447e +#define SEA_mmCRTC4_DCFE_DBG_SEL 0x477e +#define SEA_mmCRTC5_DCFE_DBG_SEL 0x4a7e +#define SEA_mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f +#define SEA_mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f +#define SEA_mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1e7f +#define SEA_mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417f +#define SEA_mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447f +#define SEA_mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477f +#define SEA_mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4a7f +#define SEA_mmCRTC_H_TOTAL 0x1b80 +#define SEA_mmCRTC0_CRTC_H_TOTAL 0x1b80 +#define SEA_mmCRTC1_CRTC_H_TOTAL 0x1e80 +#define SEA_mmCRTC2_CRTC_H_TOTAL 0x4180 +#define SEA_mmCRTC3_CRTC_H_TOTAL 0x4480 +#define SEA_mmCRTC4_CRTC_H_TOTAL 0x4780 +#define SEA_mmCRTC5_CRTC_H_TOTAL 0x4a80 +#define SEA_mmCRTC_H_BLANK_START_END 0x1b81 +#define SEA_mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 +#define SEA_mmCRTC1_CRTC_H_BLANK_START_END 0x1e81 +#define SEA_mmCRTC2_CRTC_H_BLANK_START_END 0x4181 +#define SEA_mmCRTC3_CRTC_H_BLANK_START_END 0x4481 +#define SEA_mmCRTC4_CRTC_H_BLANK_START_END 0x4781 +#define SEA_mmCRTC5_CRTC_H_BLANK_START_END 0x4a81 +#define SEA_mmCRTC_H_SYNC_A 0x1b82 +#define SEA_mmCRTC0_CRTC_H_SYNC_A 0x1b82 +#define SEA_mmCRTC1_CRTC_H_SYNC_A 0x1e82 +#define SEA_mmCRTC2_CRTC_H_SYNC_A 0x4182 +#define SEA_mmCRTC3_CRTC_H_SYNC_A 0x4482 +#define SEA_mmCRTC4_CRTC_H_SYNC_A 0x4782 +#define SEA_mmCRTC5_CRTC_H_SYNC_A 0x4a82 +#define SEA_mmCRTC_H_SYNC_A_CNTL 0x1b83 +#define SEA_mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 +#define SEA_mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1e83 +#define SEA_mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 +#define SEA_mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 +#define SEA_mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 +#define SEA_mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4a83 +#define SEA_mmCRTC_H_SYNC_B 0x1b84 +#define SEA_mmCRTC0_CRTC_H_SYNC_B 0x1b84 +#define SEA_mmCRTC1_CRTC_H_SYNC_B 0x1e84 +#define SEA_mmCRTC2_CRTC_H_SYNC_B 0x4184 +#define SEA_mmCRTC3_CRTC_H_SYNC_B 0x4484 +#define SEA_mmCRTC4_CRTC_H_SYNC_B 0x4784 +#define SEA_mmCRTC5_CRTC_H_SYNC_B 0x4a84 +#define SEA_mmCRTC_H_SYNC_B_CNTL 0x1b85 +#define SEA_mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 +#define SEA_mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1e85 +#define SEA_mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 +#define SEA_mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 +#define SEA_mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 +#define SEA_mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4a85 +#define SEA_mmCRTC_VBI_END 0x1b86 +#define SEA_mmCRTC0_CRTC_VBI_END 0x1b86 +#define SEA_mmCRTC1_CRTC_VBI_END 0x1e86 +#define SEA_mmCRTC2_CRTC_VBI_END 0x4186 +#define SEA_mmCRTC3_CRTC_VBI_END 0x4486 +#define SEA_mmCRTC4_CRTC_VBI_END 0x4786 +#define SEA_mmCRTC5_CRTC_VBI_END 0x4a86 +#define SEA_mmCRTC_V_TOTAL 0x1b87 +#define SEA_mmCRTC0_CRTC_V_TOTAL 0x1b87 +#define SEA_mmCRTC1_CRTC_V_TOTAL 0x1e87 +#define SEA_mmCRTC2_CRTC_V_TOTAL 0x4187 +#define SEA_mmCRTC3_CRTC_V_TOTAL 0x4487 +#define SEA_mmCRTC4_CRTC_V_TOTAL 0x4787 +#define SEA_mmCRTC5_CRTC_V_TOTAL 0x4a87 +#define SEA_mmCRTC_V_TOTAL_MIN 0x1b88 +#define SEA_mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 +#define SEA_mmCRTC1_CRTC_V_TOTAL_MIN 0x1e88 +#define SEA_mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 +#define SEA_mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 +#define SEA_mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 +#define SEA_mmCRTC5_CRTC_V_TOTAL_MIN 0x4a88 +#define SEA_mmCRTC_V_TOTAL_MAX 0x1b89 +#define SEA_mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 +#define SEA_mmCRTC1_CRTC_V_TOTAL_MAX 0x1e89 +#define SEA_mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 +#define SEA_mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 +#define SEA_mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 +#define SEA_mmCRTC5_CRTC_V_TOTAL_MAX 0x4a89 +#define SEA_mmCRTC_V_TOTAL_CONTROL 0x1b8a +#define SEA_mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a +#define SEA_mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1e8a +#define SEA_mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418a +#define SEA_mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448a +#define SEA_mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478a +#define SEA_mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4a8a +#define SEA_mmCRTC_V_TOTAL_INT_STATUS 0x1b8b +#define SEA_mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b +#define SEA_mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1e8b +#define SEA_mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418b +#define SEA_mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448b +#define SEA_mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478b +#define SEA_mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4a8b +#define SEA_mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define SEA_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define SEA_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1e8c +#define SEA_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418c +#define SEA_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448c +#define SEA_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478c +#define SEA_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4a8c +#define SEA_mmCRTC_V_BLANK_START_END 0x1b8d +#define SEA_mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d +#define SEA_mmCRTC1_CRTC_V_BLANK_START_END 0x1e8d +#define SEA_mmCRTC2_CRTC_V_BLANK_START_END 0x418d +#define SEA_mmCRTC3_CRTC_V_BLANK_START_END 0x448d +#define SEA_mmCRTC4_CRTC_V_BLANK_START_END 0x478d +#define SEA_mmCRTC5_CRTC_V_BLANK_START_END 0x4a8d +#define SEA_mmCRTC_V_SYNC_A 0x1b8e +#define SEA_mmCRTC0_CRTC_V_SYNC_A 0x1b8e +#define SEA_mmCRTC1_CRTC_V_SYNC_A 0x1e8e +#define SEA_mmCRTC2_CRTC_V_SYNC_A 0x418e +#define SEA_mmCRTC3_CRTC_V_SYNC_A 0x448e +#define SEA_mmCRTC4_CRTC_V_SYNC_A 0x478e +#define SEA_mmCRTC5_CRTC_V_SYNC_A 0x4a8e +#define SEA_mmCRTC_V_SYNC_A_CNTL 0x1b8f +#define SEA_mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f +#define SEA_mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1e8f +#define SEA_mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418f +#define SEA_mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448f +#define SEA_mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478f +#define SEA_mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4a8f +#define SEA_mmCRTC_V_SYNC_B 0x1b90 +#define SEA_mmCRTC0_CRTC_V_SYNC_B 0x1b90 +#define SEA_mmCRTC1_CRTC_V_SYNC_B 0x1e90 +#define SEA_mmCRTC2_CRTC_V_SYNC_B 0x4190 +#define SEA_mmCRTC3_CRTC_V_SYNC_B 0x4490 +#define SEA_mmCRTC4_CRTC_V_SYNC_B 0x4790 +#define SEA_mmCRTC5_CRTC_V_SYNC_B 0x4a90 +#define SEA_mmCRTC_V_SYNC_B_CNTL 0x1b91 +#define SEA_mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 +#define SEA_mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1e91 +#define SEA_mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 +#define SEA_mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 +#define SEA_mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 +#define SEA_mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4a91 +#define SEA_mmCRTC_DTMTEST_CNTL 0x1b92 +#define SEA_mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 +#define SEA_mmCRTC1_CRTC_DTMTEST_CNTL 0x1e92 +#define SEA_mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 +#define SEA_mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 +#define SEA_mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 +#define SEA_mmCRTC5_CRTC_DTMTEST_CNTL 0x4a92 +#define SEA_mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define SEA_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define SEA_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1e93 +#define SEA_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define SEA_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 +#define SEA_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 +#define SEA_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4a93 +#define SEA_mmCRTC_TRIGA_CNTL 0x1b94 +#define SEA_mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 +#define SEA_mmCRTC1_CRTC_TRIGA_CNTL 0x1e94 +#define SEA_mmCRTC2_CRTC_TRIGA_CNTL 0x4194 +#define SEA_mmCRTC3_CRTC_TRIGA_CNTL 0x4494 +#define SEA_mmCRTC4_CRTC_TRIGA_CNTL 0x4794 +#define SEA_mmCRTC5_CRTC_TRIGA_CNTL 0x4a94 +#define SEA_mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define SEA_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define SEA_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1e95 +#define SEA_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define SEA_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 +#define SEA_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 +#define SEA_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4a95 +#define SEA_mmCRTC_TRIGB_CNTL 0x1b96 +#define SEA_mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 +#define SEA_mmCRTC1_CRTC_TRIGB_CNTL 0x1e96 +#define SEA_mmCRTC2_CRTC_TRIGB_CNTL 0x4196 +#define SEA_mmCRTC3_CRTC_TRIGB_CNTL 0x4496 +#define SEA_mmCRTC4_CRTC_TRIGB_CNTL 0x4796 +#define SEA_mmCRTC5_CRTC_TRIGB_CNTL 0x4a96 +#define SEA_mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define SEA_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define SEA_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1e97 +#define SEA_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define SEA_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 +#define SEA_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 +#define SEA_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4a97 +#define SEA_mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define SEA_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define SEA_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1e98 +#define SEA_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define SEA_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 +#define SEA_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 +#define SEA_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4a98 +#define SEA_mmCRTC_FLOW_CONTROL 0x1b99 +#define SEA_mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 +#define SEA_mmCRTC1_CRTC_FLOW_CONTROL 0x1e99 +#define SEA_mmCRTC2_CRTC_FLOW_CONTROL 0x4199 +#define SEA_mmCRTC3_CRTC_FLOW_CONTROL 0x4499 +#define SEA_mmCRTC4_CRTC_FLOW_CONTROL 0x4799 +#define SEA_mmCRTC5_CRTC_FLOW_CONTROL 0x4a99 +#define SEA_mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9b +#define SEA_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9b +#define SEA_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1e9b +#define SEA_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419b +#define SEA_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449b +#define SEA_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479b +#define SEA_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4a9b +#define SEA_mmCRTC_CONTROL 0x1b9c +#define SEA_mmCRTC0_CRTC_CONTROL 0x1b9c +#define SEA_mmCRTC1_CRTC_CONTROL 0x1e9c +#define SEA_mmCRTC2_CRTC_CONTROL 0x419c +#define SEA_mmCRTC3_CRTC_CONTROL 0x449c +#define SEA_mmCRTC4_CRTC_CONTROL 0x479c +#define SEA_mmCRTC5_CRTC_CONTROL 0x4a9c +#define SEA_mmCRTC_BLANK_CONTROL 0x1b9d +#define SEA_mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d +#define SEA_mmCRTC1_CRTC_BLANK_CONTROL 0x1e9d +#define SEA_mmCRTC2_CRTC_BLANK_CONTROL 0x419d +#define SEA_mmCRTC3_CRTC_BLANK_CONTROL 0x449d +#define SEA_mmCRTC4_CRTC_BLANK_CONTROL 0x479d +#define SEA_mmCRTC5_CRTC_BLANK_CONTROL 0x4a9d +#define SEA_mmCRTC_INTERLACE_CONTROL 0x1b9e +#define SEA_mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e +#define SEA_mmCRTC1_CRTC_INTERLACE_CONTROL 0x1e9e +#define SEA_mmCRTC2_CRTC_INTERLACE_CONTROL 0x419e +#define SEA_mmCRTC3_CRTC_INTERLACE_CONTROL 0x449e +#define SEA_mmCRTC4_CRTC_INTERLACE_CONTROL 0x479e +#define SEA_mmCRTC5_CRTC_INTERLACE_CONTROL 0x4a9e +#define SEA_mmCRTC_INTERLACE_STATUS 0x1b9f +#define SEA_mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f +#define SEA_mmCRTC1_CRTC_INTERLACE_STATUS 0x1e9f +#define SEA_mmCRTC2_CRTC_INTERLACE_STATUS 0x419f +#define SEA_mmCRTC3_CRTC_INTERLACE_STATUS 0x449f +#define SEA_mmCRTC4_CRTC_INTERLACE_STATUS 0x479f +#define SEA_mmCRTC5_CRTC_INTERLACE_STATUS 0x4a9f +#define SEA_mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define SEA_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define SEA_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1ea0 +#define SEA_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x41a0 +#define SEA_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x44a0 +#define SEA_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x47a0 +#define SEA_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x4aa0 +#define SEA_mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define SEA_mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define SEA_mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1ea1 +#define SEA_mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x41a1 +#define SEA_mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x44a1 +#define SEA_mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x47a1 +#define SEA_mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x4aa1 +#define SEA_mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define SEA_mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define SEA_mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1ea2 +#define SEA_mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x41a2 +#define SEA_mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x44a2 +#define SEA_mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x47a2 +#define SEA_mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x4aa2 +#define SEA_mmCRTC_STATUS 0x1ba3 +#define SEA_mmCRTC0_CRTC_STATUS 0x1ba3 +#define SEA_mmCRTC1_CRTC_STATUS 0x1ea3 +#define SEA_mmCRTC2_CRTC_STATUS 0x41a3 +#define SEA_mmCRTC3_CRTC_STATUS 0x44a3 +#define SEA_mmCRTC4_CRTC_STATUS 0x47a3 +#define SEA_mmCRTC5_CRTC_STATUS 0x4aa3 +#define SEA_mmCRTC_STATUS_POSITION 0x1ba4 +#define SEA_mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 +#define SEA_mmCRTC1_CRTC_STATUS_POSITION 0x1ea4 +#define SEA_mmCRTC2_CRTC_STATUS_POSITION 0x41a4 +#define SEA_mmCRTC3_CRTC_STATUS_POSITION 0x44a4 +#define SEA_mmCRTC4_CRTC_STATUS_POSITION 0x47a4 +#define SEA_mmCRTC5_CRTC_STATUS_POSITION 0x4aa4 +#define SEA_mmCRTC_NOM_VERT_POSITION 0x1ba5 +#define SEA_mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 +#define SEA_mmCRTC1_CRTC_NOM_VERT_POSITION 0x1ea5 +#define SEA_mmCRTC2_CRTC_NOM_VERT_POSITION 0x41a5 +#define SEA_mmCRTC3_CRTC_NOM_VERT_POSITION 0x44a5 +#define SEA_mmCRTC4_CRTC_NOM_VERT_POSITION 0x47a5 +#define SEA_mmCRTC5_CRTC_NOM_VERT_POSITION 0x4aa5 +#define SEA_mmCRTC_STATUS_FRAME_COUNT 0x1ba6 +#define SEA_mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 +#define SEA_mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1ea6 +#define SEA_mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41a6 +#define SEA_mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44a6 +#define SEA_mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47a6 +#define SEA_mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4aa6 +#define SEA_mmCRTC_STATUS_VF_COUNT 0x1ba7 +#define SEA_mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 +#define SEA_mmCRTC1_CRTC_STATUS_VF_COUNT 0x1ea7 +#define SEA_mmCRTC2_CRTC_STATUS_VF_COUNT 0x41a7 +#define SEA_mmCRTC3_CRTC_STATUS_VF_COUNT 0x44a7 +#define SEA_mmCRTC4_CRTC_STATUS_VF_COUNT 0x47a7 +#define SEA_mmCRTC5_CRTC_STATUS_VF_COUNT 0x4aa7 +#define SEA_mmCRTC_STATUS_HV_COUNT 0x1ba8 +#define SEA_mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 +#define SEA_mmCRTC1_CRTC_STATUS_HV_COUNT 0x1ea8 +#define SEA_mmCRTC2_CRTC_STATUS_HV_COUNT 0x41a8 +#define SEA_mmCRTC3_CRTC_STATUS_HV_COUNT 0x44a8 +#define SEA_mmCRTC4_CRTC_STATUS_HV_COUNT 0x47a8 +#define SEA_mmCRTC5_CRTC_STATUS_HV_COUNT 0x4aa8 +#define SEA_mmCRTC_COUNT_CONTROL 0x1ba9 +#define SEA_mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 +#define SEA_mmCRTC1_CRTC_COUNT_CONTROL 0x1ea9 +#define SEA_mmCRTC2_CRTC_COUNT_CONTROL 0x41a9 +#define SEA_mmCRTC3_CRTC_COUNT_CONTROL 0x44a9 +#define SEA_mmCRTC4_CRTC_COUNT_CONTROL 0x47a9 +#define SEA_mmCRTC5_CRTC_COUNT_CONTROL 0x4aa9 +#define SEA_mmCRTC_COUNT_RESET 0x1baa +#define SEA_mmCRTC0_CRTC_COUNT_RESET 0x1baa +#define SEA_mmCRTC1_CRTC_COUNT_RESET 0x1eaa +#define SEA_mmCRTC2_CRTC_COUNT_RESET 0x41aa +#define SEA_mmCRTC3_CRTC_COUNT_RESET 0x44aa +#define SEA_mmCRTC4_CRTC_COUNT_RESET 0x47aa +#define SEA_mmCRTC5_CRTC_COUNT_RESET 0x4aaa +#define SEA_mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define SEA_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define SEA_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1eab +#define SEA_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab +#define SEA_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44ab +#define SEA_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab +#define SEA_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4aab +#define SEA_mmCRTC_VERT_SYNC_CONTROL 0x1bac +#define SEA_mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac +#define SEA_mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1eac +#define SEA_mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41ac +#define SEA_mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44ac +#define SEA_mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47ac +#define SEA_mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4aac +#define SEA_mmCRTC_STEREO_STATUS 0x1bad +#define SEA_mmCRTC0_CRTC_STEREO_STATUS 0x1bad +#define SEA_mmCRTC1_CRTC_STEREO_STATUS 0x1ead +#define SEA_mmCRTC2_CRTC_STEREO_STATUS 0x41ad +#define SEA_mmCRTC3_CRTC_STEREO_STATUS 0x44ad +#define SEA_mmCRTC4_CRTC_STEREO_STATUS 0x47ad +#define SEA_mmCRTC5_CRTC_STEREO_STATUS 0x4aad +#define SEA_mmCRTC_STEREO_CONTROL 0x1bae +#define SEA_mmCRTC0_CRTC_STEREO_CONTROL 0x1bae +#define SEA_mmCRTC1_CRTC_STEREO_CONTROL 0x1eae +#define SEA_mmCRTC2_CRTC_STEREO_CONTROL 0x41ae +#define SEA_mmCRTC3_CRTC_STEREO_CONTROL 0x44ae +#define SEA_mmCRTC4_CRTC_STEREO_CONTROL 0x47ae +#define SEA_mmCRTC5_CRTC_STEREO_CONTROL 0x4aae +#define SEA_mmCRTC_SNAPSHOT_STATUS 0x1baf +#define SEA_mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf +#define SEA_mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1eaf +#define SEA_mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41af +#define SEA_mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44af +#define SEA_mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47af +#define SEA_mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4aaf +#define SEA_mmCRTC_SNAPSHOT_CONTROL 0x1bb0 +#define SEA_mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 +#define SEA_mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1eb0 +#define SEA_mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41b0 +#define SEA_mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44b0 +#define SEA_mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47b0 +#define SEA_mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4ab0 +#define SEA_mmCRTC_SNAPSHOT_POSITION 0x1bb1 +#define SEA_mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 +#define SEA_mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1eb1 +#define SEA_mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41b1 +#define SEA_mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44b1 +#define SEA_mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47b1 +#define SEA_mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4ab1 +#define SEA_mmCRTC_SNAPSHOT_FRAME 0x1bb2 +#define SEA_mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 +#define SEA_mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1eb2 +#define SEA_mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41b2 +#define SEA_mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44b2 +#define SEA_mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47b2 +#define SEA_mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4ab2 +#define SEA_mmCRTC_START_LINE_CONTROL 0x1bb3 +#define SEA_mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 +#define SEA_mmCRTC1_CRTC_START_LINE_CONTROL 0x1eb3 +#define SEA_mmCRTC2_CRTC_START_LINE_CONTROL 0x41b3 +#define SEA_mmCRTC3_CRTC_START_LINE_CONTROL 0x44b3 +#define SEA_mmCRTC4_CRTC_START_LINE_CONTROL 0x47b3 +#define SEA_mmCRTC5_CRTC_START_LINE_CONTROL 0x4ab3 +#define SEA_mmCRTC_INTERRUPT_CONTROL 0x1bb4 +#define SEA_mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 +#define SEA_mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1eb4 +#define SEA_mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41b4 +#define SEA_mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44b4 +#define SEA_mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47b4 +#define SEA_mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4ab4 +#define SEA_mmCRTC_UPDATE_LOCK 0x1bb5 +#define SEA_mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 +#define SEA_mmCRTC1_CRTC_UPDATE_LOCK 0x1eb5 +#define SEA_mmCRTC2_CRTC_UPDATE_LOCK 0x41b5 +#define SEA_mmCRTC3_CRTC_UPDATE_LOCK 0x44b5 +#define SEA_mmCRTC4_CRTC_UPDATE_LOCK 0x47b5 +#define SEA_mmCRTC5_CRTC_UPDATE_LOCK 0x4ab5 +#define SEA_mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define SEA_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define SEA_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1eb6 +#define SEA_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 +#define SEA_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44b6 +#define SEA_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6 +#define SEA_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4ab6 +#define SEA_mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define SEA_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define SEA_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1eb7 +#define SEA_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 +#define SEA_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44b7 +#define SEA_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7 +#define SEA_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4ab7 +#define SEA_mmCRTC_TEST_PATTERN_CONTROL 0x1bba +#define SEA_mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba +#define SEA_mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1eba +#define SEA_mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41ba +#define SEA_mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44ba +#define SEA_mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47ba +#define SEA_mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4aba +#define SEA_mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define SEA_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define SEA_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1ebb +#define SEA_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41bb +#define SEA_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44bb +#define SEA_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47bb +#define SEA_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4abb +#define SEA_mmCRTC_TEST_PATTERN_COLOR 0x1bbc +#define SEA_mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc +#define SEA_mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1ebc +#define SEA_mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41bc +#define SEA_mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44bc +#define SEA_mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47bc +#define SEA_mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4abc +#define SEA_mmMASTER_UPDATE_LOCK 0x1bbd +#define SEA_mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd +#define SEA_mmCRTC1_MASTER_UPDATE_LOCK 0x1ebd +#define SEA_mmCRTC2_MASTER_UPDATE_LOCK 0x41bd +#define SEA_mmCRTC3_MASTER_UPDATE_LOCK 0x44bd +#define SEA_mmCRTC4_MASTER_UPDATE_LOCK 0x47bd +#define SEA_mmCRTC5_MASTER_UPDATE_LOCK 0x4abd +#define SEA_mmMASTER_UPDATE_MODE 0x1bbe +#define SEA_mmCRTC0_MASTER_UPDATE_MODE 0x1bbe +#define SEA_mmCRTC1_MASTER_UPDATE_MODE 0x1ebe +#define SEA_mmCRTC2_MASTER_UPDATE_MODE 0x41be +#define SEA_mmCRTC3_MASTER_UPDATE_MODE 0x44be +#define SEA_mmCRTC4_MASTER_UPDATE_MODE 0x47be +#define SEA_mmCRTC5_MASTER_UPDATE_MODE 0x4abe +#define SEA_mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define SEA_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define SEA_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1ebf +#define SEA_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf +#define SEA_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44bf +#define SEA_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf +#define SEA_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4abf +#define SEA_mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define SEA_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define SEA_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1ec0 +#define SEA_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 +#define SEA_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44c0 +#define SEA_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 +#define SEA_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4ac0 +#define SEA_mmCRTC_MVP_STATUS 0x1bc1 +#define SEA_mmCRTC0_CRTC_MVP_STATUS 0x1bc1 +#define SEA_mmCRTC1_CRTC_MVP_STATUS 0x1ec1 +#define SEA_mmCRTC2_CRTC_MVP_STATUS 0x41c1 +#define SEA_mmCRTC3_CRTC_MVP_STATUS 0x44c1 +#define SEA_mmCRTC4_CRTC_MVP_STATUS 0x47c1 +#define SEA_mmCRTC5_CRTC_MVP_STATUS 0x4ac1 +#define SEA_mmCRTC_MASTER_EN 0x1bc2 +#define SEA_mmCRTC0_CRTC_MASTER_EN 0x1bc2 +#define SEA_mmCRTC1_CRTC_MASTER_EN 0x1ec2 +#define SEA_mmCRTC2_CRTC_MASTER_EN 0x41c2 +#define SEA_mmCRTC3_CRTC_MASTER_EN 0x44c2 +#define SEA_mmCRTC4_CRTC_MASTER_EN 0x47c2 +#define SEA_mmCRTC5_CRTC_MASTER_EN 0x4ac2 +#define SEA_mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define SEA_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define SEA_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1ec3 +#define SEA_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 +#define SEA_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44c3 +#define SEA_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3 +#define SEA_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4ac3 +#define SEA_mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define SEA_mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define SEA_mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1ec4 +#define SEA_mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41c4 +#define SEA_mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44c4 +#define SEA_mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47c4 +#define SEA_mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4ac4 +#define SEA_mmCRTC_OVERSCAN_COLOR 0x1bc8 +#define SEA_mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 +#define SEA_mmCRTC1_CRTC_OVERSCAN_COLOR 0x1ec8 +#define SEA_mmCRTC2_CRTC_OVERSCAN_COLOR 0x41c8 +#define SEA_mmCRTC3_CRTC_OVERSCAN_COLOR 0x44c8 +#define SEA_mmCRTC4_CRTC_OVERSCAN_COLOR 0x47c8 +#define SEA_mmCRTC5_CRTC_OVERSCAN_COLOR 0x4ac8 +#define SEA_mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define SEA_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define SEA_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1ec9 +#define SEA_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x41c9 +#define SEA_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x44c9 +#define SEA_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x47c9 +#define SEA_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x4ac9 +#define SEA_mmCRTC_BLANK_DATA_COLOR 0x1bca +#define SEA_mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca +#define SEA_mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1eca +#define SEA_mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41ca +#define SEA_mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44ca +#define SEA_mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47ca +#define SEA_mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4aca +#define SEA_mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define SEA_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define SEA_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1ecb +#define SEA_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x41cb +#define SEA_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x44cb +#define SEA_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x47cb +#define SEA_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x4acb +#define SEA_mmCRTC_BLACK_COLOR 0x1bcc +#define SEA_mmCRTC0_CRTC_BLACK_COLOR 0x1bcc +#define SEA_mmCRTC1_CRTC_BLACK_COLOR 0x1ecc +#define SEA_mmCRTC2_CRTC_BLACK_COLOR 0x41cc +#define SEA_mmCRTC3_CRTC_BLACK_COLOR 0x44cc +#define SEA_mmCRTC4_CRTC_BLACK_COLOR 0x47cc +#define SEA_mmCRTC5_CRTC_BLACK_COLOR 0x4acc +#define SEA_mmCRTC_BLACK_COLOR_EXT 0x1bcd +#define SEA_mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd +#define SEA_mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1ecd +#define SEA_mmCRTC2_CRTC_BLACK_COLOR_EXT 0x41cd +#define SEA_mmCRTC3_CRTC_BLACK_COLOR_EXT 0x44cd +#define SEA_mmCRTC4_CRTC_BLACK_COLOR_EXT 0x47cd +#define SEA_mmCRTC5_CRTC_BLACK_COLOR_EXT 0x4acd +#define SEA_mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1ece +#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce +#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x44ce +#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce +#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x4ace +#define SEA_mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1ecf +#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf +#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x44cf +#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf +#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x4acf +#define SEA_mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1ed0 +#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 +#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x44d0 +#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0 +#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x4ad0 +#define SEA_mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1ed1 +#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 +#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x44d1 +#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1 +#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x4ad1 +#define SEA_mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1ed2 +#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 +#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x44d2 +#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2 +#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x4ad2 +#define SEA_mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1ed3 +#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 +#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x44d3 +#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3 +#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x4ad3 +#define SEA_mmCRTC_CRC_CNTL 0x1bd4 +#define SEA_mmCRTC0_CRTC_CRC_CNTL 0x1bd4 +#define SEA_mmCRTC1_CRTC_CRC_CNTL 0x1ed4 +#define SEA_mmCRTC2_CRTC_CRC_CNTL 0x41d4 +#define SEA_mmCRTC3_CRTC_CRC_CNTL 0x44d4 +#define SEA_mmCRTC4_CRTC_CRC_CNTL 0x47d4 +#define SEA_mmCRTC5_CRTC_CRC_CNTL 0x4ad4 +#define SEA_mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define SEA_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define SEA_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1ed5 +#define SEA_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 +#define SEA_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x44d5 +#define SEA_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5 +#define SEA_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x4ad5 +#define SEA_mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define SEA_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define SEA_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1ed6 +#define SEA_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 +#define SEA_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x44d6 +#define SEA_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6 +#define SEA_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x4ad6 +#define SEA_mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define SEA_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define SEA_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1ed7 +#define SEA_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 +#define SEA_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x44d7 +#define SEA_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7 +#define SEA_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x4ad7 +#define SEA_mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define SEA_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define SEA_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1ed8 +#define SEA_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 +#define SEA_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x44d8 +#define SEA_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8 +#define SEA_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x4ad8 +#define SEA_mmCRTC_CRC0_DATA_RG 0x1bd9 +#define SEA_mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 +#define SEA_mmCRTC1_CRTC_CRC0_DATA_RG 0x1ed9 +#define SEA_mmCRTC2_CRTC_CRC0_DATA_RG 0x41d9 +#define SEA_mmCRTC3_CRTC_CRC0_DATA_RG 0x44d9 +#define SEA_mmCRTC4_CRTC_CRC0_DATA_RG 0x47d9 +#define SEA_mmCRTC5_CRTC_CRC0_DATA_RG 0x4ad9 +#define SEA_mmCRTC_CRC0_DATA_B 0x1bda +#define SEA_mmCRTC0_CRTC_CRC0_DATA_B 0x1bda +#define SEA_mmCRTC1_CRTC_CRC0_DATA_B 0x1eda +#define SEA_mmCRTC2_CRTC_CRC0_DATA_B 0x41da +#define SEA_mmCRTC3_CRTC_CRC0_DATA_B 0x44da +#define SEA_mmCRTC4_CRTC_CRC0_DATA_B 0x47da +#define SEA_mmCRTC5_CRTC_CRC0_DATA_B 0x4ada +#define SEA_mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define SEA_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define SEA_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1edb +#define SEA_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db +#define SEA_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x44db +#define SEA_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db +#define SEA_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x4adb +#define SEA_mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define SEA_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define SEA_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1edc +#define SEA_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc +#define SEA_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x44dc +#define SEA_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc +#define SEA_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x4adc +#define SEA_mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define SEA_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define SEA_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1edd +#define SEA_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd +#define SEA_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x44dd +#define SEA_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd +#define SEA_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x4add +#define SEA_mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define SEA_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define SEA_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1ede +#define SEA_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de +#define SEA_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x44de +#define SEA_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de +#define SEA_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x4ade +#define SEA_mmCRTC_CRC1_DATA_RG 0x1bdf +#define SEA_mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf +#define SEA_mmCRTC1_CRTC_CRC1_DATA_RG 0x1edf +#define SEA_mmCRTC2_CRTC_CRC1_DATA_RG 0x41df +#define SEA_mmCRTC3_CRTC_CRC1_DATA_RG 0x44df +#define SEA_mmCRTC4_CRTC_CRC1_DATA_RG 0x47df +#define SEA_mmCRTC5_CRTC_CRC1_DATA_RG 0x4adf +#define SEA_mmCRTC_CRC1_DATA_B 0x1be0 +#define SEA_mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 +#define SEA_mmCRTC1_CRTC_CRC1_DATA_B 0x1ee0 +#define SEA_mmCRTC2_CRTC_CRC1_DATA_B 0x41e0 +#define SEA_mmCRTC3_CRTC_CRC1_DATA_B 0x44e0 +#define SEA_mmCRTC4_CRTC_CRC1_DATA_B 0x47e0 +#define SEA_mmCRTC5_CRTC_CRC1_DATA_B 0x4ae0 +#define SEA_mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1ee1 +#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 +#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x44e1 +#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1 +#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x4ae1 +#define SEA_mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1ee2 +#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 +#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x44e2 +#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2 +#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x4ae2 +#define SEA_mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1ee3 +#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 +#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x44e3 +#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3 +#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x4ae3 +#define SEA_mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1ee4 +#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 +#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x44e4 +#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4 +#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x4ae4 +#define SEA_mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1ee5 +#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 +#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x44e5 +#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5 +#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x4ae5 +#define SEA_mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1ee6 +#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 +#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x44e6 +#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6 +#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x4ae6 +#define SEA_mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define SEA_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define SEA_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1ee7 +#define SEA_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x41e7 +#define SEA_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x44e7 +#define SEA_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x47e7 +#define SEA_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x4ae7 +#define SEA_mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define SEA_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define SEA_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1e78 +#define SEA_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define SEA_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 +#define SEA_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 +#define SEA_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4a78 +#define SEA_mmCRTC_GSL_VSYNC_GAP 0x1b79 +#define SEA_mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 +#define SEA_mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1e79 +#define SEA_mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 +#define SEA_mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 +#define SEA_mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 +#define SEA_mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4a79 +#define SEA_mmCRTC_GSL_WINDOW 0x1b7a +#define SEA_mmCRTC0_CRTC_GSL_WINDOW 0x1b7a +#define SEA_mmCRTC1_CRTC_GSL_WINDOW 0x1e7a +#define SEA_mmCRTC2_CRTC_GSL_WINDOW 0x417a +#define SEA_mmCRTC3_CRTC_GSL_WINDOW 0x447a +#define SEA_mmCRTC4_CRTC_GSL_WINDOW 0x477a +#define SEA_mmCRTC5_CRTC_GSL_WINDOW 0x4a7a +#define SEA_mmCRTC_GSL_CONTROL 0x1b7b +#define SEA_mmCRTC0_CRTC_GSL_CONTROL 0x1b7b +#define SEA_mmCRTC1_CRTC_GSL_CONTROL 0x1e7b +#define SEA_mmCRTC2_CRTC_GSL_CONTROL 0x417b +#define SEA_mmCRTC3_CRTC_GSL_CONTROL 0x447b +#define SEA_mmCRTC4_CRTC_GSL_CONTROL 0x477b +#define SEA_mmCRTC5_CRTC_GSL_CONTROL 0x4a7b +#define SEA_mmCRTC_TEST_DEBUG_INDEX 0x1bc6 +#define SEA_mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 +#define SEA_mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1ec6 +#define SEA_mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41c6 +#define SEA_mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44c6 +#define SEA_mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47c6 +#define SEA_mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4ac6 +#define SEA_mmCRTC_TEST_DEBUG_DATA 0x1bc7 +#define SEA_mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 +#define SEA_mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1ec7 +#define SEA_mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41c7 +#define SEA_mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44c7 +#define SEA_mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47c7 +#define SEA_mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4ac7 +#define SEA_mmDAC_ENABLE 0x19e4 +#define SEA_mmDAC_SOURCE_SELECT 0x19e5 +#define SEA_mmDAC_CRC_EN 0x19e6 +#define SEA_mmDAC_CRC_CONTROL 0x19e7 +#define SEA_mmDAC_CRC_SIG_RGB_MASK 0x19e8 +#define SEA_mmDAC_CRC_SIG_CONTROL_MASK 0x19e9 +#define SEA_mmDAC_CRC_SIG_RGB 0x19ea +#define SEA_mmDAC_CRC_SIG_CONTROL 0x19eb +#define SEA_mmDAC_SYNC_TRISTATE_CONTROL 0x19ec +#define SEA_mmDAC_STEREOSYNC_SELECT 0x19ed +#define SEA_mmDAC_AUTODETECT_CONTROL 0x19ee +#define SEA_mmDAC_AUTODETECT_CONTROL2 0x19ef +#define SEA_mmDAC_AUTODETECT_CONTROL3 0x19f0 +#define SEA_mmDAC_AUTODETECT_STATUS 0x19f1 +#define SEA_mmDAC_AUTODETECT_INT_CONTROL 0x19f2 +#define SEA_mmDAC_FORCE_OUTPUT_CNTL 0x19f3 +#define SEA_mmDAC_FORCE_DATA 0x19f4 +#define SEA_mmDAC_POWERDOWN 0x19f5 +#define SEA_mmDAC_CONTROL 0x19f6 +#define SEA_mmDAC_COMPARATOR_ENABLE 0x19f7 +#define SEA_mmDAC_COMPARATOR_OUTPUT 0x19f8 +#define SEA_mmDAC_PWR_CNTL 0x19f9 +#define SEA_mmDAC_DFT_CONFIG 0x19fa +#define SEA_mmDAC_FIFO_STATUS 0x19fb +#define SEA_mmPERFCOUNTER_CNTL 0x170 +#define SEA_mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 +#define SEA_mmDC_PERFMON1_PERFCOUNTER_CNTL 0x1870 +#define SEA_mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1b24 +#define SEA_mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1e24 +#define SEA_mmDC_PERFMON4_PERFCOUNTER_CNTL 0x4124 +#define SEA_mmDC_PERFMON5_PERFCOUNTER_CNTL 0x4424 +#define SEA_mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4724 +#define SEA_mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4a24 +#define SEA_mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4c40 +#define SEA_mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4d14 +#define SEA_mmPERFCOUNTER_STATE 0x171 +#define SEA_mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 +#define SEA_mmDC_PERFMON1_PERFCOUNTER_STATE 0x1871 +#define SEA_mmDC_PERFMON2_PERFCOUNTER_STATE 0x1b25 +#define SEA_mmDC_PERFMON3_PERFCOUNTER_STATE 0x1e25 +#define SEA_mmDC_PERFMON4_PERFCOUNTER_STATE 0x4125 +#define SEA_mmDC_PERFMON5_PERFCOUNTER_STATE 0x4425 +#define SEA_mmDC_PERFMON6_PERFCOUNTER_STATE 0x4725 +#define SEA_mmDC_PERFMON7_PERFCOUNTER_STATE 0x4a25 +#define SEA_mmDC_PERFMON8_PERFCOUNTER_STATE 0x4c41 +#define SEA_mmDC_PERFMON9_PERFCOUNTER_STATE 0x4d15 +#define SEA_mmPERFMON_CNTL 0x173 +#define SEA_mmDC_PERFMON0_PERFMON_CNTL 0x173 +#define SEA_mmDC_PERFMON1_PERFMON_CNTL 0x1873 +#define SEA_mmDC_PERFMON2_PERFMON_CNTL 0x1b27 +#define SEA_mmDC_PERFMON3_PERFMON_CNTL 0x1e27 +#define SEA_mmDC_PERFMON4_PERFMON_CNTL 0x4127 +#define SEA_mmDC_PERFMON5_PERFMON_CNTL 0x4427 +#define SEA_mmDC_PERFMON6_PERFMON_CNTL 0x4727 +#define SEA_mmDC_PERFMON7_PERFMON_CNTL 0x4a27 +#define SEA_mmDC_PERFMON8_PERFMON_CNTL 0x4c43 +#define SEA_mmDC_PERFMON9_PERFMON_CNTL 0x4d17 +#define SEA_mmPERFMON_CVALUE_INT_MISC 0x172 +#define SEA_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 +#define SEA_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x1872 +#define SEA_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1b26 +#define SEA_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1e26 +#define SEA_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x4126 +#define SEA_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x4426 +#define SEA_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4726 +#define SEA_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4a26 +#define SEA_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4c42 +#define SEA_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4d16 +#define SEA_mmPERFMON_CVALUE_LOW 0x174 +#define SEA_mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 +#define SEA_mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x1874 +#define SEA_mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1b28 +#define SEA_mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1e28 +#define SEA_mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x4128 +#define SEA_mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x4428 +#define SEA_mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4728 +#define SEA_mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4a28 +#define SEA_mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4c44 +#define SEA_mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4d18 +#define SEA_mmPERFMON_HI 0x175 +#define SEA_mmDC_PERFMON0_PERFMON_HI 0x175 +#define SEA_mmDC_PERFMON1_PERFMON_HI 0x1875 +#define SEA_mmDC_PERFMON2_PERFMON_HI 0x1b29 +#define SEA_mmDC_PERFMON3_PERFMON_HI 0x1e29 +#define SEA_mmDC_PERFMON4_PERFMON_HI 0x4129 +#define SEA_mmDC_PERFMON5_PERFMON_HI 0x4429 +#define SEA_mmDC_PERFMON6_PERFMON_HI 0x4729 +#define SEA_mmDC_PERFMON7_PERFMON_HI 0x4a29 +#define SEA_mmDC_PERFMON8_PERFMON_HI 0x4c45 +#define SEA_mmDC_PERFMON9_PERFMON_HI 0x4d19 +#define SEA_mmPERFMON_LOW 0x176 +#define SEA_mmDC_PERFMON0_PERFMON_LOW 0x176 +#define SEA_mmDC_PERFMON1_PERFMON_LOW 0x1876 +#define SEA_mmDC_PERFMON2_PERFMON_LOW 0x1b2a +#define SEA_mmDC_PERFMON3_PERFMON_LOW 0x1e2a +#define SEA_mmDC_PERFMON4_PERFMON_LOW 0x412a +#define SEA_mmDC_PERFMON5_PERFMON_LOW 0x442a +#define SEA_mmDC_PERFMON6_PERFMON_LOW 0x472a +#define SEA_mmDC_PERFMON7_PERFMON_LOW 0x4a2a +#define SEA_mmDC_PERFMON8_PERFMON_LOW 0x4c46 +#define SEA_mmDC_PERFMON9_PERFMON_LOW 0x4d1a +#define SEA_mmPERFMON_TEST_DEBUG_INDEX 0x177 +#define SEA_mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 +#define SEA_mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x1877 +#define SEA_mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x1b2b +#define SEA_mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1e2b +#define SEA_mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x412b +#define SEA_mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x442b +#define SEA_mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x472b +#define SEA_mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x4a2b +#define SEA_mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x4c47 +#define SEA_mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x4d1b +#define SEA_mmPERFMON_TEST_DEBUG_DATA 0x178 +#define SEA_mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 +#define SEA_mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x1878 +#define SEA_mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x1b2c +#define SEA_mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1e2c +#define SEA_mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x412c +#define SEA_mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x442c +#define SEA_mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x472c +#define SEA_mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x4a2c +#define SEA_mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x4c48 +#define SEA_mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x4d1c +#define SEA_mmVGA25_PPLL_REF_DIV 0xd8 +#define SEA_mmVGA28_PPLL_REF_DIV 0xd9 +#define SEA_mmVGA41_PPLL_REF_DIV 0xda +#define SEA_mmVGA25_PPLL_FB_DIV 0xdc +#define SEA_mmVGA28_PPLL_FB_DIV 0xdd +#define SEA_mmVGA41_PPLL_FB_DIV 0xde +#define SEA_mmVGA25_PPLL_POST_DIV 0xe0 +#define SEA_mmVGA28_PPLL_POST_DIV 0xe1 +#define SEA_mmVGA41_PPLL_POST_DIV 0xe2 +#define SEA_mmVGA25_PPLL_ANALOG 0xe4 +#define SEA_mmVGA28_PPLL_ANALOG 0xe5 +#define SEA_mmVGA41_PPLL_ANALOG 0xe6 +#define SEA_mmDPREFCLK_CNTL 0x118 +#define SEA_mmSCANIN_SOFT_RESET 0x11e +#define SEA_mmDCCG_GTC_CNTL 0x120 +#define SEA_mmDCCG_GTC_DTO_INCR 0x121 +#define SEA_mmDCCG_GTC_DTO_MODULO 0x122 +#define SEA_mmDCCG_GTC_CURRENT 0x123 +#define SEA_mmDCCG_DS_DTO_INCR 0x113 +#define SEA_mmDCCG_DS_DTO_MODULO 0x114 +#define SEA_mmDCCG_DS_CNTL 0x115 +#define SEA_mmDCCG_DS_HW_CAL_INTERVAL 0x116 +#define SEA_mmDCCG_DS_DEBUG_CNTL 0x112 +#define SEA_mmDMCU_SMU_INTERRUPT_CNTL 0x12c +#define SEA_mmSMU_CONTROL 0x12d +#define SEA_mmSMU_INTERRUPT_CONTROL 0x12e +#define SEA_mmDAC_CLK_ENABLE 0x128 +#define SEA_mmDVO_CLK_ENABLE 0x129 +#define SEA_mmDCCG_GATE_DISABLE_CNTL 0x134 +#define SEA_mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 +#define SEA_mmSCLK_CGTT_BLK_CTRL_REG 0x136 +#define SEA_mmDCCG_CAC_STATUS 0x137 +#define SEA_mmPIXCLK1_RESYNC_CNTL 0x138 +#define SEA_mmPIXCLK2_RESYNC_CNTL 0x139 +#define SEA_mmPIXCLK0_RESYNC_CNTL 0x13a +#define SEA_mmMICROSECOND_TIME_BASE_DIV 0x13b +#define SEA_mmDCCG_DISP_CNTL_REG 0x13f +#define SEA_mmDISPPLL_BG_CNTL 0x13c +#define SEA_mmDIG_SOFT_RESET 0x13d +#define SEA_mmMILLISECOND_TIME_BASE_DIV 0x130 +#define SEA_mmDISPCLK_FREQ_CHANGE_CNTL 0x131 +#define SEA_mmLIGHT_SLEEP_CNTL 0x132 +#define SEA_mmDCCG_PERFMON_CNTL 0x133 +#define SEA_mmCRTC0_PIXEL_RATE_CNTL 0x140 +#define SEA_mmDP_DTO0_PHASE 0x141 +#define SEA_mmDP_DTO0_MODULO 0x142 +#define SEA_mmCRTC1_PIXEL_RATE_CNTL 0x144 +#define SEA_mmDP_DTO1_PHASE 0x145 +#define SEA_mmDP_DTO1_MODULO 0x146 +#define SEA_mmCRTC2_PIXEL_RATE_CNTL 0x148 +#define SEA_mmDP_DTO2_PHASE 0x149 +#define SEA_mmDP_DTO2_MODULO 0x14a +#define SEA_mmCRTC3_PIXEL_RATE_CNTL 0x14c +#define SEA_mmDP_DTO3_PHASE 0x14d +#define SEA_mmDP_DTO3_MODULO 0x14e +#define SEA_mmCRTC4_PIXEL_RATE_CNTL 0x150 +#define SEA_mmDP_DTO4_PHASE 0x151 +#define SEA_mmDP_DTO4_MODULO 0x152 +#define SEA_mmCRTC5_PIXEL_RATE_CNTL 0x154 +#define SEA_mmDP_DTO5_PHASE 0x155 +#define SEA_mmDP_DTO5_MODULO 0x156 +#define SEA_mmDCFE0_SOFT_RESET 0x158 +#define SEA_mmDCFE1_SOFT_RESET 0x159 +#define SEA_mmDCFE2_SOFT_RESET 0x15a +#define SEA_mmDCFE3_SOFT_RESET 0x15b +#define SEA_mmDCFE4_SOFT_RESET 0x15c +#define SEA_mmDCFE5_SOFT_RESET 0x15d +#define SEA_mmDCI_SOFT_RESET 0x15e +#define SEA_mmDCCG_SOFT_RESET 0x15f +#define SEA_mmSYMCLKA_CLOCK_ENABLE 0x160 +#define SEA_mmSYMCLKB_CLOCK_ENABLE 0x161 +#define SEA_mmSYMCLKC_CLOCK_ENABLE 0x162 +#define SEA_mmSYMCLKD_CLOCK_ENABLE 0x163 +#define SEA_mmSYMCLKE_CLOCK_ENABLE 0x164 +#define SEA_mmSYMCLKF_CLOCK_ENABLE 0x165 +#define SEA_mmSYMCLKG_CLOCK_ENABLE 0x117 +#define SEA_mmUNIPHY_SOFT_RESET 0x166 +#define SEA_mmDCO_SOFT_RESET 0x167 +#define SEA_mmDVOACLKD_CNTL 0x168 +#define SEA_mmDVOACLKC_MVP_CNTL 0x169 +#define SEA_mmDVOACLKC_CNTL 0x16a +#define SEA_mmDCCG_AUDIO_DTO_SOURCE 0x16b +#define SEA_mmDCCG_AUDIO_DTO0_PHASE 0x16c +#define SEA_mmDCCG_AUDIO_DTO0_MODULE 0x16d +#define SEA_mmDCCG_AUDIO_DTO1_PHASE 0x16e +#define SEA_mmDCCG_AUDIO_DTO1_MODULE 0x16f +#define SEA_mmDCCG_TEST_DEBUG_INDEX 0x17c +#define SEA_mmDCCG_TEST_DEBUG_DATA 0x17d +#define SEA_mmDCCG_TEST_CLK_SEL 0x17e +#define SEA_mmPLL_REF_DIV 0x1700 +#define SEA_mmDCCG_PLL0_PLL_REF_DIV 0x1700 +#define SEA_mmDCCG_PLL1_PLL_REF_DIV 0x1714 +#define SEA_mmDCCG_PLL2_PLL_REF_DIV 0x1728 +#define SEA_mmDCCG_PLL3_PLL_REF_DIV 0x173c +#define SEA_mmPLL_FB_DIV 0x1701 +#define SEA_mmDCCG_PLL0_PLL_FB_DIV 0x1701 +#define SEA_mmDCCG_PLL1_PLL_FB_DIV 0x1715 +#define SEA_mmDCCG_PLL2_PLL_FB_DIV 0x1729 +#define SEA_mmDCCG_PLL3_PLL_FB_DIV 0x173d +#define SEA_mmPLL_POST_DIV 0x1702 +#define SEA_mmDCCG_PLL0_PLL_POST_DIV 0x1702 +#define SEA_mmDCCG_PLL1_PLL_POST_DIV 0x1716 +#define SEA_mmDCCG_PLL2_PLL_POST_DIV 0x172a +#define SEA_mmDCCG_PLL3_PLL_POST_DIV 0x173e +#define SEA_mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define SEA_mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define SEA_mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1717 +#define SEA_mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x172b +#define SEA_mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC 0x173f +#define SEA_mmPLL_SS_CNTL 0x1704 +#define SEA_mmDCCG_PLL0_PLL_SS_CNTL 0x1704 +#define SEA_mmDCCG_PLL1_PLL_SS_CNTL 0x1718 +#define SEA_mmDCCG_PLL2_PLL_SS_CNTL 0x172c +#define SEA_mmDCCG_PLL3_PLL_SS_CNTL 0x1740 +#define SEA_mmPLL_DS_CNTL 0x1705 +#define SEA_mmDCCG_PLL0_PLL_DS_CNTL 0x1705 +#define SEA_mmDCCG_PLL1_PLL_DS_CNTL 0x1719 +#define SEA_mmDCCG_PLL2_PLL_DS_CNTL 0x172d +#define SEA_mmDCCG_PLL3_PLL_DS_CNTL 0x1741 +#define SEA_mmPLL_IDCLK_CNTL 0x1706 +#define SEA_mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 +#define SEA_mmDCCG_PLL1_PLL_IDCLK_CNTL 0x171a +#define SEA_mmDCCG_PLL2_PLL_IDCLK_CNTL 0x172e +#define SEA_mmDCCG_PLL3_PLL_IDCLK_CNTL 0x1742 +#define SEA_mmPLL_CNTL 0x1707 +#define SEA_mmDCCG_PLL0_PLL_CNTL 0x1707 +#define SEA_mmDCCG_PLL1_PLL_CNTL 0x171b +#define SEA_mmDCCG_PLL2_PLL_CNTL 0x172f +#define SEA_mmDCCG_PLL3_PLL_CNTL 0x1743 +#define SEA_mmPLL_ANALOG 0x1708 +#define SEA_mmDCCG_PLL0_PLL_ANALOG 0x1708 +#define SEA_mmDCCG_PLL1_PLL_ANALOG 0x171c +#define SEA_mmDCCG_PLL2_PLL_ANALOG 0x1730 +#define SEA_mmDCCG_PLL3_PLL_ANALOG 0x1744 +#define SEA_mmPLL_ANALOG_CNTL 0x1711 +#define SEA_mmDCCG_PLL0_PLL_ANALOG_CNTL 0x1711 +#define SEA_mmDCCG_PLL1_PLL_ANALOG_CNTL 0x1725 +#define SEA_mmDCCG_PLL2_PLL_ANALOG_CNTL 0x1739 +#define SEA_mmDCCG_PLL3_PLL_ANALOG_CNTL 0x174d +#define SEA_mmPLL_VREG_CNTL 0x1709 +#define SEA_mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 +#define SEA_mmDCCG_PLL1_PLL_VREG_CNTL 0x171d +#define SEA_mmDCCG_PLL2_PLL_VREG_CNTL 0x1731 +#define SEA_mmDCCG_PLL3_PLL_VREG_CNTL 0x1745 +#define SEA_mmPLL_XOR_LOCK 0x1710 +#define SEA_mmDCCG_PLL0_PLL_XOR_LOCK 0x1710 +#define SEA_mmDCCG_PLL1_PLL_XOR_LOCK 0x1724 +#define SEA_mmDCCG_PLL2_PLL_XOR_LOCK 0x1738 +#define SEA_mmDCCG_PLL3_PLL_XOR_LOCK 0x174c +#define SEA_mmPLL_UNLOCK_DETECT_CNTL 0x170a +#define SEA_mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a +#define SEA_mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171e +#define SEA_mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x1732 +#define SEA_mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL 0x1746 +#define SEA_mmPLL_DEBUG_CNTL 0x170b +#define SEA_mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170b +#define SEA_mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171f +#define SEA_mmDCCG_PLL2_PLL_DEBUG_CNTL 0x1733 +#define SEA_mmDCCG_PLL3_PLL_DEBUG_CNTL 0x1747 +#define SEA_mmPLL_UPDATE_LOCK 0x170c +#define SEA_mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170c +#define SEA_mmDCCG_PLL1_PLL_UPDATE_LOCK 0x1720 +#define SEA_mmDCCG_PLL2_PLL_UPDATE_LOCK 0x1734 +#define SEA_mmDCCG_PLL3_PLL_UPDATE_LOCK 0x1748 +#define SEA_mmPLL_UPDATE_CNTL 0x170d +#define SEA_mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170d +#define SEA_mmDCCG_PLL1_PLL_UPDATE_CNTL 0x1721 +#define SEA_mmDCCG_PLL2_PLL_UPDATE_CNTL 0x1735 +#define SEA_mmDCCG_PLL3_PLL_UPDATE_CNTL 0x1749 +#define SEA_mmPLL_DISPCLK_DTO_CNTL 0x170e +#define SEA_mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170e +#define SEA_mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x1722 +#define SEA_mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x1736 +#define SEA_mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL 0x174a +#define SEA_mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170f +#define SEA_mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170f +#define SEA_mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1723 +#define SEA_mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1737 +#define SEA_mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE 0x174b +#define SEA_mmDENTIST_DISPCLK_CNTL 0x124 +#define SEA_mmDCDEBUG_BUS_CLK1_SEL 0x1860 +#define SEA_mmDCDEBUG_BUS_CLK2_SEL 0x1861 +#define SEA_mmDCDEBUG_BUS_CLK3_SEL 0x1862 +#define SEA_mmDCDEBUG_BUS_CLK4_SEL 0x1863 +#define SEA_mmDCDEBUG_OUT_PIN_OVERRIDE 0x186a +#define SEA_mmDCDEBUG_OUT_CNTL 0x186b +#define SEA_mmDCDEBUG_OUT_DATA 0x186e +#define SEA_mmDMIF_ADDR_CONFIG 0x2f5 +#define SEA_mmDMIF_CONTROL 0x2f6 +#define SEA_mmDMIF_STATUS 0x2f7 +#define SEA_mmDMIF_HW_DEBUG 0x2f8 +#define SEA_mmDMIF_ARBITRATION_CONTROL 0x2f9 +#define SEA_mmPIPE0_ARBITRATION_CONTROL3 0x2fa +#define SEA_mmPIPE1_ARBITRATION_CONTROL3 0x2fb +#define SEA_mmPIPE2_ARBITRATION_CONTROL3 0x2fc +#define SEA_mmPIPE3_ARBITRATION_CONTROL3 0x2fd +#define SEA_mmPIPE4_ARBITRATION_CONTROL3 0x2fe +#define SEA_mmPIPE5_ARBITRATION_CONTROL3 0x2ff +#define SEA_mmDMIF_TEST_DEBUG_INDEX 0x312 +#define SEA_mmDMIF_TEST_DEBUG_DATA 0x313 +#define SEA_ixDMIF_DEBUG02_CORE0 0x2 +#define SEA_ixDMIF_DEBUG02_CORE1 0xa +#define SEA_mmDMIF_ADDR_CALC 0x300 +#define SEA_mmDMIF_STATUS2 0x301 +#define SEA_mmPIPE0_MAX_REQUESTS 0x302 +#define SEA_mmPIPE1_MAX_REQUESTS 0x303 +#define SEA_mmPIPE2_MAX_REQUESTS 0x304 +#define SEA_mmPIPE3_MAX_REQUESTS 0x305 +#define SEA_mmPIPE4_MAX_REQUESTS 0x306 +#define SEA_mmPIPE5_MAX_REQUESTS 0x307 +#define SEA_mmLOW_POWER_TILING_CONTROL 0x325 +#define SEA_mmMCIF_CONTROL 0x314 +#define SEA_mmMCIF_WRITE_COMBINE_CONTROL 0x315 +#define SEA_mmMCIF_TEST_DEBUG_INDEX 0x316 +#define SEA_mmMCIF_TEST_DEBUG_DATA 0x317 +#define SEA_ixIDDCCIF02_DBG_DCCIF_C 0x9 +#define SEA_ixIDDCCIF04_DBG_DCCIF_E 0xb +#define SEA_ixIDDCCIF05_DBG_DCCIF_F 0xc +#define SEA_mmMCIF_VMID 0x318 +#define SEA_mmMCIF_MEM_CONTROL 0x319 +#define SEA_mmCC_DC_PIPE_DIS 0x177f +#define SEA_mmMC_DC_INTERFACE_NACK_STATUS 0x31c +#define SEA_mmDC_RBBMIF_RDWR_CNTL1 0x31a +#define SEA_mmDC_RBBMIF_RDWR_CNTL2 0x31d +#define SEA_mmDC_RBBMIF_RDWR_CNTL3 0x311 +#define SEA_mmDCI_MEM_PWR_STATE 0x31b +#define SEA_mmDCI_MEM_PWR_STATE2 0x322 +#define SEA_mmDCI_CLK_CNTL 0x31e +#define SEA_mmDCCG_VPCLK_CNTL 0x31f +#define SEA_mmDCI_MEM_PWR_CNTL 0x326 +#define SEA_mmDC_XDMA_INTERFACE_CNTL 0x327 +#define SEA_mmDCI_TEST_DEBUG_INDEX 0x320 +#define SEA_mmDCI_TEST_DEBUG_DATA 0x321 +#define SEA_mmDCI_DEBUG_CONFIG 0x323 +#define SEA_mmPIPE0_DMIF_BUFFER_CONTROL 0x328 +#define SEA_mmPIPE1_DMIF_BUFFER_CONTROL 0x330 +#define SEA_mmPIPE2_DMIF_BUFFER_CONTROL 0x338 +#define SEA_mmPIPE3_DMIF_BUFFER_CONTROL 0x340 +#define SEA_mmPIPE4_DMIF_BUFFER_CONTROL 0x348 +#define SEA_mmPIPE5_DMIF_BUFFER_CONTROL 0x350 +#define SEA_mmMCIF_BUFMGR_SW_CONTROL 0x358 +#define SEA_mmMCIF_BUFMGR_STATUS 0x35a +#define SEA_mmMCIF_BUF_PITCH 0x35b +#define SEA_mmMCIF_BUF_1_ADDR_Y_LOW 0x35c +#define SEA_mmMCIF_BUF_2_ADDR_Y_LOW 0x360 +#define SEA_mmMCIF_BUF_3_ADDR_Y_LOW 0x364 +#define SEA_mmMCIF_BUF_4_ADDR_Y_LOW 0x368 +#define SEA_mmMCIF_BUF_1_ADDR_UP 0x35d +#define SEA_mmMCIF_BUF_2_ADDR_UP 0x361 +#define SEA_mmMCIF_BUF_3_ADDR_UP 0x365 +#define SEA_mmMCIF_BUF_4_ADDR_UP 0x369 +#define SEA_mmMCIF_BUF_1_ADDR_C_LOW 0x35e +#define SEA_mmMCIF_BUF_2_ADDR_C_LOW 0x362 +#define SEA_mmMCIF_BUF_3_ADDR_C_LOW 0x366 +#define SEA_mmMCIF_BUF_4_ADDR_C_LOW 0x36a +#define SEA_mmMCIF_BUF_1_STATUS 0x35f +#define SEA_mmMCIF_BUF_2_STATUS 0x363 +#define SEA_mmMCIF_BUF_3_STATUS 0x367 +#define SEA_mmMCIF_BUF_4_STATUS 0x36b +#define SEA_mmMCIF_SI_ARBITRATION_CONTROL 0x36c +#define SEA_mmMCIF_URGENCY_WATERMARK 0x36d +#define SEA_mmDC_GENERICA 0x1900 +#define SEA_mmDC_GENERICB 0x1901 +#define SEA_mmDC_PAD_EXTERN_SIG 0x1902 +#define SEA_mmDC_REF_CLK_CNTL 0x1903 +#define SEA_mmDC_GPIO_DEBUG 0x1904 +#define SEA_mmDCO_MEM_POWER_STATE 0x1906 +#define SEA_mmDCO_MEM_POWER_STATE_2 0x193a +#define SEA_mmDCO_LIGHT_SLEEP_DIS 0x1907 +#define SEA_mmUNIPHY_IMPCAL_LINKA 0x1908 +#define SEA_mmUNIPHY_IMPCAL_LINKB 0x1909 +#define SEA_mmUNIPHY_IMPCAL_PERIOD 0x190a +#define SEA_mmAUXP_IMPCAL 0x190b +#define SEA_mmAUXN_IMPCAL 0x190c +#define SEA_mmDCIO_IMPCAL_CNTL_AB 0x190d +#define SEA_mmUNIPHY_IMPCAL_PSW_AB 0x190e +#define SEA_mmUNIPHY_IMPCAL_LINKC 0x190f +#define SEA_mmUNIPHY_IMPCAL_LINKD 0x1910 +#define SEA_mmDCIO_IMPCAL_CNTL_CD 0x1911 +#define SEA_mmUNIPHY_IMPCAL_PSW_CD 0x1912 +#define SEA_mmUNIPHY_IMPCAL_LINKE 0x1913 +#define SEA_mmUNIPHY_IMPCAL_LINKF 0x1914 +#define SEA_mmDCIO_IMPCAL_CNTL_EF 0x1915 +#define SEA_mmUNIPHY_IMPCAL_PSW_EF 0x1916 +#define SEA_mmDC_PINSTRAPS 0x1917 +#define SEA_mmDC_DVODATA_CONFIG 0x1905 +#define SEA_mmLVTMA_PWRSEQ_CNTL 0x1919 +#define SEA_mmLVTMA_PWRSEQ_STATE 0x191a +#define SEA_mmLVTMA_PWRSEQ_REF_DIV 0x191b +#define SEA_mmLVTMA_PWRSEQ_DELAY1 0x191c +#define SEA_mmLVTMA_PWRSEQ_DELAY2 0x191d +#define SEA_mmBL_PWM_CNTL 0x191e +#define SEA_mmBL_PWM_CNTL2 0x191f +#define SEA_mmBL_PWM_PERIOD_CNTL 0x1920 +#define SEA_mmBL_PWM_GRP1_REG_LOCK 0x1921 +#define SEA_mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 +#define SEA_mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 +#define SEA_mmDCIO_GSL0_CNTL 0x1924 +#define SEA_mmDCIO_GSL1_CNTL 0x1925 +#define SEA_mmDCIO_GSL2_CNTL 0x1926 +#define SEA_mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 +#define SEA_mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 +#define SEA_mmDC_GPU_TIMER_READ 0x1929 +#define SEA_mmDC_GPU_TIMER_READ_CNTL 0x192a +#define SEA_mmDCO_CLK_CNTL 0x192b +#define SEA_mmDCO_CLK_RAMP_CNTL 0x192c +#define SEA_mmDCIO_DEBUG 0x192e +#define SEA_mmDCO_DCFE_EXT_VSYNC_CNTL 0x1937 +#define SEA_mmDCIO_TEST_DEBUG_INDEX 0x192f +#define SEA_mmDCIO_TEST_DEBUG_DATA 0x1930 +#define SEA_ixDCIO_DEBUG1 0x1 +#define SEA_ixDCIO_DEBUG2 0x2 +#define SEA_ixDCIO_DEBUG3 0x3 +#define SEA_ixDCIO_DEBUG4 0x4 +#define SEA_ixDCIO_DEBUG5 0x5 +#define SEA_ixDCIO_DEBUG6 0x6 +#define SEA_ixDCIO_DEBUG7 0x7 +#define SEA_ixDCIO_DEBUG8 0x8 +#define SEA_ixDCIO_DEBUG9 0x9 +#define SEA_ixDCIO_DEBUGA 0xa +#define SEA_ixDCIO_DEBUGB 0xb +#define SEA_ixDCIO_DEBUGC 0xc +#define SEA_ixDCIO_DEBUGD 0xd +#define SEA_ixDCIO_DEBUGE 0xe +#define SEA_ixDCIO_DEBUGF 0xf +#define SEA_ixDCIO_DEBUG10 0x10 +#define SEA_ixDCIO_DEBUG11 0x11 +#define SEA_ixDCIO_DEBUG12 0x12 +#define SEA_ixDCIO_DEBUG13 0x13 +#define SEA_ixDCIO_DEBUG14 0x14 +#define SEA_ixDCIO_DEBUG15 0x15 +#define SEA_ixDCIO_DEBUG_ID 0x0 +#define SEA_mmDC_GPIO_GENERIC_MASK 0x1944 +#define SEA_mmDC_GPIO_GENERIC_A 0x1945 +#define SEA_mmDC_GPIO_GENERIC_EN 0x1946 +#define SEA_mmDC_GPIO_GENERIC_Y 0x1947 +#define SEA_mmDC_GPIO_DVODATA_MASK 0x1948 +#define SEA_mmDC_GPIO_DVODATA_A 0x1949 +#define SEA_mmDC_GPIO_DVODATA_EN 0x194a +#define SEA_mmDC_GPIO_DVODATA_Y 0x194b +#define SEA_mmDC_GPIO_DDC1_MASK 0x194c +#define SEA_mmDC_GPIO_DDC1_A 0x194d +#define SEA_mmDC_GPIO_DDC1_EN 0x194e +#define SEA_mmDC_GPIO_DDC1_Y 0x194f +#define SEA_mmDC_GPIO_DDC2_MASK 0x1950 +#define SEA_mmDC_GPIO_DDC2_A 0x1951 +#define SEA_mmDC_GPIO_DDC2_EN 0x1952 +#define SEA_mmDC_GPIO_DDC2_Y 0x1953 +#define SEA_mmDC_GPIO_DDC3_MASK 0x1954 +#define SEA_mmDC_GPIO_DDC3_A 0x1955 +#define SEA_mmDC_GPIO_DDC3_EN 0x1956 +#define SEA_mmDC_GPIO_DDC3_Y 0x1957 +#define SEA_mmDC_GPIO_DDC4_MASK 0x1958 +#define SEA_mmDC_GPIO_DDC4_A 0x1959 +#define SEA_mmDC_GPIO_DDC4_EN 0x195a +#define SEA_mmDC_GPIO_DDC4_Y 0x195b +#define SEA_mmDC_GPIO_DDC5_MASK 0x195c +#define SEA_mmDC_GPIO_DDC5_A 0x195d +#define SEA_mmDC_GPIO_DDC5_EN 0x195e +#define SEA_mmDC_GPIO_DDC5_Y 0x195f +#define SEA_mmDC_GPIO_DDC6_MASK 0x1960 +#define SEA_mmDC_GPIO_DDC6_A 0x1961 +#define SEA_mmDC_GPIO_DDC6_EN 0x1962 +#define SEA_mmDC_GPIO_DDC6_Y 0x1963 +#define SEA_mmDC_GPIO_DDCVGA_MASK 0x1970 +#define SEA_mmDC_GPIO_DDCVGA_A 0x1971 +#define SEA_mmDC_GPIO_DDCVGA_EN 0x1972 +#define SEA_mmDC_GPIO_DDCVGA_Y 0x1973 +#define SEA_mmDC_GPIO_SYNCA_MASK 0x1964 +#define SEA_mmDC_GPIO_SYNCA_A 0x1965 +#define SEA_mmDC_GPIO_SYNCA_EN 0x1966 +#define SEA_mmDC_GPIO_SYNCA_Y 0x1967 +#define SEA_mmDC_GPIO_GENLK_MASK 0x1968 +#define SEA_mmDC_GPIO_GENLK_A 0x1969 +#define SEA_mmDC_GPIO_GENLK_EN 0x196a +#define SEA_mmDC_GPIO_GENLK_Y 0x196b +#define SEA_mmDC_GPIO_HPD_MASK 0x196c +#define SEA_mmDC_GPIO_HPD_A 0x196d +#define SEA_mmDC_GPIO_HPD_EN 0x196e +#define SEA_mmDC_GPIO_HPD_Y 0x196f +#define SEA_mmDC_GPIO_PWRSEQ_MASK 0x1940 +#define SEA_mmDC_GPIO_PWRSEQ_A 0x1941 +#define SEA_mmDC_GPIO_PWRSEQ_EN 0x1942 +#define SEA_mmDC_GPIO_PWRSEQ_Y 0x1943 +#define SEA_mmDC_GPIO_PAD_STRENGTH_1 0x1978 +#define SEA_mmDC_GPIO_PAD_STRENGTH_2 0x1979 +#define SEA_mmPHY_AUX_CNTL 0x197f +#define SEA_mmDC_GPIO_I2CPAD_A 0x1975 +#define SEA_mmDC_GPIO_I2CPAD_EN 0x1976 +#define SEA_mmDC_GPIO_I2CPAD_Y 0x1977 +#define SEA_mmDC_GPIO_I2CPAD_STRENGTH 0x197a +#define SEA_mmDVO_STRENGTH_CONTROL 0x197b +#define SEA_mmDVO_VREF_CONTROL 0x197c +#define SEA_mmDVO_SKEW_ADJUST 0x197d +#define SEA_mmUNIPHYAB_TPG_CONTROL 0x1931 +#define SEA_mmUNIPHYAB_TPG_SEED 0x1932 +#define SEA_mmUNIPHYCD_TPG_CONTROL 0x1933 +#define SEA_mmUNIPHYCD_TPG_SEED 0x1934 +#define SEA_mmUNIPHYEF_TPG_CONTROL 0x1935 +#define SEA_mmUNIPHYEF_TPG_SEED 0x1936 +#define SEA_mmUNIPHYGH_TPG_CONTROL 0x1938 +#define SEA_mmUNIPHYGH_TPG_SEED 0x1939 +#define SEA_mmDC_GPIO_I2S_SPDIF_MASK 0x193c +#define SEA_mmDC_GPIO_I2S_SPDIF_A 0x193d +#define SEA_mmDC_GPIO_I2S_SPDIF_EN 0x193e +#define SEA_mmDC_GPIO_I2S_SPDIF_Y 0x193f +#define SEA_mmDC_GPIO_I2S_SPDIF_STRENGTH 0x193b +#define SEA_mmDAC_MACRO_CNTL_RESERVED0 0x19fc +#define SEA_mmDAC_MACRO_CNTL_RESERVED1 0x19fd +#define SEA_mmDAC_MACRO_CNTL_RESERVED2 0x19fe +#define SEA_mmDAC_MACRO_CNTL_RESERVED3 0x19ff +#define SEA_mmUNIPHY_TX_CONTROL1 0x1980 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19a0 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19b0 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19c0 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19d0 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1 0x4df0 +#define SEA_mmUNIPHY_TX_CONTROL2 0x1981 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19a1 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19b1 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19c1 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19d1 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2 0x4df1 +#define SEA_mmUNIPHY_TX_CONTROL3 0x1982 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19a2 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19b2 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19c2 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19d2 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3 0x4df2 +#define SEA_mmUNIPHY_TX_CONTROL4 0x1983 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19a3 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19b3 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19c3 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19d3 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4 0x4df3 +#define SEA_mmUNIPHY_POWER_CONTROL 0x1984 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19a4 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19b4 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19c4 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19d4 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL 0x4df4 +#define SEA_mmUNIPHY_PLL_FBDIV 0x1985 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19a5 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19b5 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19c5 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19d5 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV 0x4df5 +#define SEA_mmUNIPHY_PLL_CONTROL1 0x1986 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19a6 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19b6 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19c6 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19d6 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4df6 +#define SEA_mmUNIPHY_PLL_CONTROL2 0x1987 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19a7 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19b7 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19c7 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19d7 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4df7 +#define SEA_mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19a8 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19b8 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19c8 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19d8 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4df8 +#define SEA_mmUNIPHY_PLL_SS_CNTL 0x1989 +#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 +#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 +#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19a9 +#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19b9 +#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19c9 +#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19d9 +#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4df9 +#define SEA_mmUNIPHY_DATA_SYNCHRONIZATION 0x198a +#define SEA_mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198a +#define SEA_mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199a +#define SEA_mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19aa +#define SEA_mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19ba +#define SEA_mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19ca +#define SEA_mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19da +#define SEA_mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x4dfa +#define SEA_mmUNIPHY_REG_TEST_OUTPUT 0x198b +#define SEA_mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198b +#define SEA_mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199b +#define SEA_mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19ab +#define SEA_mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19bb +#define SEA_mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19cb +#define SEA_mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19db +#define SEA_mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x4dfb +#define SEA_mmUNIPHY_ANG_BIST_CNTL 0x198c +#define SEA_mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198c +#define SEA_mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199c +#define SEA_mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19ac +#define SEA_mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19bc +#define SEA_mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19cc +#define SEA_mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19dc +#define SEA_mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x4dfc +#define SEA_mmUNIPHY_LINK_CNTL 0x198d +#define SEA_mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198d +#define SEA_mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199d +#define SEA_mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19ad +#define SEA_mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19bd +#define SEA_mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19cd +#define SEA_mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19dd +#define SEA_mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL 0x4dfd +#define SEA_mmUNIPHY_CHANNEL_XBAR_CNTL 0x198e +#define SEA_mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198e +#define SEA_mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199e +#define SEA_mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19ae +#define SEA_mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19be +#define SEA_mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19ce +#define SEA_mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19de +#define SEA_mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL 0x4dfe +#define SEA_mmUNIPHY_REG_TEST_OUTPUT2 0x198f +#define SEA_mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x198f +#define SEA_mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x199f +#define SEA_mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x19af +#define SEA_mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x19bf +#define SEA_mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x19cf +#define SEA_mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x19df +#define SEA_mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x4dff +#define SEA_mmGRPH_ENABLE 0x1a00 +#define SEA_mmDCP0_GRPH_ENABLE 0x1a00 +#define SEA_mmDCP1_GRPH_ENABLE 0x1d00 +#define SEA_mmDCP2_GRPH_ENABLE 0x4000 +#define SEA_mmDCP3_GRPH_ENABLE 0x4300 +#define SEA_mmDCP4_GRPH_ENABLE 0x4600 +#define SEA_mmDCP5_GRPH_ENABLE 0x4900 +#define SEA_mmGRPH_CONTROL 0x1a01 +#define SEA_mmDCP0_GRPH_CONTROL 0x1a01 +#define SEA_mmDCP1_GRPH_CONTROL 0x1d01 +#define SEA_mmDCP2_GRPH_CONTROL 0x4001 +#define SEA_mmDCP3_GRPH_CONTROL 0x4301 +#define SEA_mmDCP4_GRPH_CONTROL 0x4601 +#define SEA_mmDCP5_GRPH_CONTROL 0x4901 +#define SEA_mmGRPH_LUT_10BIT_BYPASS 0x1a02 +#define SEA_mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 +#define SEA_mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1d02 +#define SEA_mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 +#define SEA_mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 +#define SEA_mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 +#define SEA_mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 +#define SEA_mmGRPH_SWAP_CNTL 0x1a03 +#define SEA_mmDCP0_GRPH_SWAP_CNTL 0x1a03 +#define SEA_mmDCP1_GRPH_SWAP_CNTL 0x1d03 +#define SEA_mmDCP2_GRPH_SWAP_CNTL 0x4003 +#define SEA_mmDCP3_GRPH_SWAP_CNTL 0x4303 +#define SEA_mmDCP4_GRPH_SWAP_CNTL 0x4603 +#define SEA_mmDCP5_GRPH_SWAP_CNTL 0x4903 +#define SEA_mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define SEA_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define SEA_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1d04 +#define SEA_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define SEA_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 +#define SEA_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 +#define SEA_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 +#define SEA_mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define SEA_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define SEA_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1d05 +#define SEA_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define SEA_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 +#define SEA_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 +#define SEA_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 +#define SEA_mmGRPH_PITCH 0x1a06 +#define SEA_mmDCP0_GRPH_PITCH 0x1a06 +#define SEA_mmDCP1_GRPH_PITCH 0x1d06 +#define SEA_mmDCP2_GRPH_PITCH 0x4006 +#define SEA_mmDCP3_GRPH_PITCH 0x4306 +#define SEA_mmDCP4_GRPH_PITCH 0x4606 +#define SEA_mmDCP5_GRPH_PITCH 0x4906 +#define SEA_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define SEA_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define SEA_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1d07 +#define SEA_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define SEA_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 +#define SEA_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 +#define SEA_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 +#define SEA_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define SEA_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define SEA_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d08 +#define SEA_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define SEA_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 +#define SEA_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 +#define SEA_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 +#define SEA_mmGRPH_SURFACE_OFFSET_X 0x1a09 +#define SEA_mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 +#define SEA_mmDCP1_GRPH_SURFACE_OFFSET_X 0x1d09 +#define SEA_mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 +#define SEA_mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 +#define SEA_mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 +#define SEA_mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 +#define SEA_mmGRPH_SURFACE_OFFSET_Y 0x1a0a +#define SEA_mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a +#define SEA_mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1d0a +#define SEA_mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400a +#define SEA_mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430a +#define SEA_mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460a +#define SEA_mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490a +#define SEA_mmGRPH_X_START 0x1a0b +#define SEA_mmDCP0_GRPH_X_START 0x1a0b +#define SEA_mmDCP1_GRPH_X_START 0x1d0b +#define SEA_mmDCP2_GRPH_X_START 0x400b +#define SEA_mmDCP3_GRPH_X_START 0x430b +#define SEA_mmDCP4_GRPH_X_START 0x460b +#define SEA_mmDCP5_GRPH_X_START 0x490b +#define SEA_mmGRPH_Y_START 0x1a0c +#define SEA_mmDCP0_GRPH_Y_START 0x1a0c +#define SEA_mmDCP1_GRPH_Y_START 0x1d0c +#define SEA_mmDCP2_GRPH_Y_START 0x400c +#define SEA_mmDCP3_GRPH_Y_START 0x430c +#define SEA_mmDCP4_GRPH_Y_START 0x460c +#define SEA_mmDCP5_GRPH_Y_START 0x490c +#define SEA_mmGRPH_X_END 0x1a0d +#define SEA_mmDCP0_GRPH_X_END 0x1a0d +#define SEA_mmDCP1_GRPH_X_END 0x1d0d +#define SEA_mmDCP2_GRPH_X_END 0x400d +#define SEA_mmDCP3_GRPH_X_END 0x430d +#define SEA_mmDCP4_GRPH_X_END 0x460d +#define SEA_mmDCP5_GRPH_X_END 0x490d +#define SEA_mmGRPH_Y_END 0x1a0e +#define SEA_mmDCP0_GRPH_Y_END 0x1a0e +#define SEA_mmDCP1_GRPH_Y_END 0x1d0e +#define SEA_mmDCP2_GRPH_Y_END 0x400e +#define SEA_mmDCP3_GRPH_Y_END 0x430e +#define SEA_mmDCP4_GRPH_Y_END 0x460e +#define SEA_mmDCP5_GRPH_Y_END 0x490e +#define SEA_mmINPUT_GAMMA_CONTROL 0x1a10 +#define SEA_mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 +#define SEA_mmDCP1_INPUT_GAMMA_CONTROL 0x1d10 +#define SEA_mmDCP2_INPUT_GAMMA_CONTROL 0x4010 +#define SEA_mmDCP3_INPUT_GAMMA_CONTROL 0x4310 +#define SEA_mmDCP4_INPUT_GAMMA_CONTROL 0x4610 +#define SEA_mmDCP5_INPUT_GAMMA_CONTROL 0x4910 +#define SEA_mmGRPH_UPDATE 0x1a11 +#define SEA_mmDCP0_GRPH_UPDATE 0x1a11 +#define SEA_mmDCP1_GRPH_UPDATE 0x1d11 +#define SEA_mmDCP2_GRPH_UPDATE 0x4011 +#define SEA_mmDCP3_GRPH_UPDATE 0x4311 +#define SEA_mmDCP4_GRPH_UPDATE 0x4611 +#define SEA_mmDCP5_GRPH_UPDATE 0x4911 +#define SEA_mmGRPH_FLIP_CONTROL 0x1a12 +#define SEA_mmDCP0_GRPH_FLIP_CONTROL 0x1a12 +#define SEA_mmDCP1_GRPH_FLIP_CONTROL 0x1d12 +#define SEA_mmDCP2_GRPH_FLIP_CONTROL 0x4012 +#define SEA_mmDCP3_GRPH_FLIP_CONTROL 0x4312 +#define SEA_mmDCP4_GRPH_FLIP_CONTROL 0x4612 +#define SEA_mmDCP5_GRPH_FLIP_CONTROL 0x4912 +#define SEA_mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define SEA_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define SEA_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1d13 +#define SEA_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define SEA_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 +#define SEA_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 +#define SEA_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 +#define SEA_mmGRPH_DFQ_CONTROL 0x1a14 +#define SEA_mmDCP0_GRPH_DFQ_CONTROL 0x1a14 +#define SEA_mmDCP1_GRPH_DFQ_CONTROL 0x1d14 +#define SEA_mmDCP2_GRPH_DFQ_CONTROL 0x4014 +#define SEA_mmDCP3_GRPH_DFQ_CONTROL 0x4314 +#define SEA_mmDCP4_GRPH_DFQ_CONTROL 0x4614 +#define SEA_mmDCP5_GRPH_DFQ_CONTROL 0x4914 +#define SEA_mmGRPH_DFQ_STATUS 0x1a15 +#define SEA_mmDCP0_GRPH_DFQ_STATUS 0x1a15 +#define SEA_mmDCP1_GRPH_DFQ_STATUS 0x1d15 +#define SEA_mmDCP2_GRPH_DFQ_STATUS 0x4015 +#define SEA_mmDCP3_GRPH_DFQ_STATUS 0x4315 +#define SEA_mmDCP4_GRPH_DFQ_STATUS 0x4615 +#define SEA_mmDCP5_GRPH_DFQ_STATUS 0x4915 +#define SEA_mmGRPH_INTERRUPT_STATUS 0x1a16 +#define SEA_mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 +#define SEA_mmDCP1_GRPH_INTERRUPT_STATUS 0x1d16 +#define SEA_mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 +#define SEA_mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 +#define SEA_mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 +#define SEA_mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 +#define SEA_mmGRPH_INTERRUPT_CONTROL 0x1a17 +#define SEA_mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 +#define SEA_mmDCP1_GRPH_INTERRUPT_CONTROL 0x1d17 +#define SEA_mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 +#define SEA_mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 +#define SEA_mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 +#define SEA_mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 +#define SEA_mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define SEA_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define SEA_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1d18 +#define SEA_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define SEA_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 +#define SEA_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 +#define SEA_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 +#define SEA_mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define SEA_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define SEA_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1d19 +#define SEA_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define SEA_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 +#define SEA_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 +#define SEA_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 +#define SEA_mmGRPH_COMPRESS_PITCH 0x1a1a +#define SEA_mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a +#define SEA_mmDCP1_GRPH_COMPRESS_PITCH 0x1d1a +#define SEA_mmDCP2_GRPH_COMPRESS_PITCH 0x401a +#define SEA_mmDCP3_GRPH_COMPRESS_PITCH 0x431a +#define SEA_mmDCP4_GRPH_COMPRESS_PITCH 0x461a +#define SEA_mmDCP5_GRPH_COMPRESS_PITCH 0x491a +#define SEA_mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define SEA_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define SEA_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1d1b +#define SEA_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b +#define SEA_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431b +#define SEA_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461b +#define SEA_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491b +#define SEA_mmOVL_ENABLE 0x1a1c +#define SEA_mmDCP0_OVL_ENABLE 0x1a1c +#define SEA_mmDCP1_OVL_ENABLE 0x1d1c +#define SEA_mmDCP2_OVL_ENABLE 0x401c +#define SEA_mmDCP3_OVL_ENABLE 0x431c +#define SEA_mmDCP4_OVL_ENABLE 0x461c +#define SEA_mmDCP5_OVL_ENABLE 0x491c +#define SEA_mmOVL_CONTROL1 0x1a1d +#define SEA_mmDCP0_OVL_CONTROL1 0x1a1d +#define SEA_mmDCP1_OVL_CONTROL1 0x1d1d +#define SEA_mmDCP2_OVL_CONTROL1 0x401d +#define SEA_mmDCP3_OVL_CONTROL1 0x431d +#define SEA_mmDCP4_OVL_CONTROL1 0x461d +#define SEA_mmDCP5_OVL_CONTROL1 0x491d +#define SEA_mmOVL_CONTROL2 0x1a1e +#define SEA_mmDCP0_OVL_CONTROL2 0x1a1e +#define SEA_mmDCP1_OVL_CONTROL2 0x1d1e +#define SEA_mmDCP2_OVL_CONTROL2 0x401e +#define SEA_mmDCP3_OVL_CONTROL2 0x431e +#define SEA_mmDCP4_OVL_CONTROL2 0x461e +#define SEA_mmDCP5_OVL_CONTROL2 0x491e +#define SEA_mmOVL_SWAP_CNTL 0x1a1f +#define SEA_mmDCP0_OVL_SWAP_CNTL 0x1a1f +#define SEA_mmDCP1_OVL_SWAP_CNTL 0x1d1f +#define SEA_mmDCP2_OVL_SWAP_CNTL 0x401f +#define SEA_mmDCP3_OVL_SWAP_CNTL 0x431f +#define SEA_mmDCP4_OVL_SWAP_CNTL 0x461f +#define SEA_mmDCP5_OVL_SWAP_CNTL 0x491f +#define SEA_mmOVL_SURFACE_ADDRESS 0x1a20 +#define SEA_mmDCP0_OVL_SURFACE_ADDRESS 0x1a20 +#define SEA_mmDCP1_OVL_SURFACE_ADDRESS 0x1d20 +#define SEA_mmDCP2_OVL_SURFACE_ADDRESS 0x4020 +#define SEA_mmDCP3_OVL_SURFACE_ADDRESS 0x4320 +#define SEA_mmDCP4_OVL_SURFACE_ADDRESS 0x4620 +#define SEA_mmDCP5_OVL_SURFACE_ADDRESS 0x4920 +#define SEA_mmOVL_PITCH 0x1a21 +#define SEA_mmDCP0_OVL_PITCH 0x1a21 +#define SEA_mmDCP1_OVL_PITCH 0x1d21 +#define SEA_mmDCP2_OVL_PITCH 0x4021 +#define SEA_mmDCP3_OVL_PITCH 0x4321 +#define SEA_mmDCP4_OVL_PITCH 0x4621 +#define SEA_mmDCP5_OVL_PITCH 0x4921 +#define SEA_mmOVL_SURFACE_ADDRESS_HIGH 0x1a22 +#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22 +#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1d22 +#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 +#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 +#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 +#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 +#define SEA_mmOVL_SURFACE_OFFSET_X 0x1a23 +#define SEA_mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23 +#define SEA_mmDCP1_OVL_SURFACE_OFFSET_X 0x1d23 +#define SEA_mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 +#define SEA_mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 +#define SEA_mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 +#define SEA_mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 +#define SEA_mmOVL_SURFACE_OFFSET_Y 0x1a24 +#define SEA_mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24 +#define SEA_mmDCP1_OVL_SURFACE_OFFSET_Y 0x1d24 +#define SEA_mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 +#define SEA_mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 +#define SEA_mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 +#define SEA_mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 +#define SEA_mmOVL_START 0x1a25 +#define SEA_mmDCP0_OVL_START 0x1a25 +#define SEA_mmDCP1_OVL_START 0x1d25 +#define SEA_mmDCP2_OVL_START 0x4025 +#define SEA_mmDCP3_OVL_START 0x4325 +#define SEA_mmDCP4_OVL_START 0x4625 +#define SEA_mmDCP5_OVL_START 0x4925 +#define SEA_mmOVL_END 0x1a26 +#define SEA_mmDCP0_OVL_END 0x1a26 +#define SEA_mmDCP1_OVL_END 0x1d26 +#define SEA_mmDCP2_OVL_END 0x4026 +#define SEA_mmDCP3_OVL_END 0x4326 +#define SEA_mmDCP4_OVL_END 0x4626 +#define SEA_mmDCP5_OVL_END 0x4926 +#define SEA_mmOVL_UPDATE 0x1a27 +#define SEA_mmDCP0_OVL_UPDATE 0x1a27 +#define SEA_mmDCP1_OVL_UPDATE 0x1d27 +#define SEA_mmDCP2_OVL_UPDATE 0x4027 +#define SEA_mmDCP3_OVL_UPDATE 0x4327 +#define SEA_mmDCP4_OVL_UPDATE 0x4627 +#define SEA_mmDCP5_OVL_UPDATE 0x4927 +#define SEA_mmOVL_SURFACE_ADDRESS_INUSE 0x1a28 +#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28 +#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1d28 +#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 +#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 +#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 +#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 +#define SEA_mmOVL_DFQ_CONTROL 0x1a29 +#define SEA_mmDCP0_OVL_DFQ_CONTROL 0x1a29 +#define SEA_mmDCP1_OVL_DFQ_CONTROL 0x1d29 +#define SEA_mmDCP2_OVL_DFQ_CONTROL 0x4029 +#define SEA_mmDCP3_OVL_DFQ_CONTROL 0x4329 +#define SEA_mmDCP4_OVL_DFQ_CONTROL 0x4629 +#define SEA_mmDCP5_OVL_DFQ_CONTROL 0x4929 +#define SEA_mmOVL_DFQ_STATUS 0x1a2a +#define SEA_mmDCP0_OVL_DFQ_STATUS 0x1a2a +#define SEA_mmDCP1_OVL_DFQ_STATUS 0x1d2a +#define SEA_mmDCP2_OVL_DFQ_STATUS 0x402a +#define SEA_mmDCP3_OVL_DFQ_STATUS 0x432a +#define SEA_mmDCP4_OVL_DFQ_STATUS 0x462a +#define SEA_mmDCP5_OVL_DFQ_STATUS 0x492a +#define SEA_mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b +#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b +#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1d2b +#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b +#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432b +#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462b +#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492b +#define SEA_mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c +#define SEA_mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c +#define SEA_mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1d2c +#define SEA_mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402c +#define SEA_mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432c +#define SEA_mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462c +#define SEA_mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492c +#define SEA_mmPRESCALE_GRPH_CONTROL 0x1a2d +#define SEA_mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d +#define SEA_mmDCP1_PRESCALE_GRPH_CONTROL 0x1d2d +#define SEA_mmDCP2_PRESCALE_GRPH_CONTROL 0x402d +#define SEA_mmDCP3_PRESCALE_GRPH_CONTROL 0x432d +#define SEA_mmDCP4_PRESCALE_GRPH_CONTROL 0x462d +#define SEA_mmDCP5_PRESCALE_GRPH_CONTROL 0x492d +#define SEA_mmPRESCALE_VALUES_GRPH_R 0x1a2e +#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e +#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_R 0x1d2e +#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_R 0x402e +#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_R 0x432e +#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_R 0x462e +#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_R 0x492e +#define SEA_mmPRESCALE_VALUES_GRPH_G 0x1a2f +#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f +#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_G 0x1d2f +#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_G 0x402f +#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_G 0x432f +#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_G 0x462f +#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_G 0x492f +#define SEA_mmPRESCALE_VALUES_GRPH_B 0x1a30 +#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 +#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_B 0x1d30 +#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 +#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 +#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 +#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 +#define SEA_mmPRESCALE_OVL_CONTROL 0x1a31 +#define SEA_mmDCP0_PRESCALE_OVL_CONTROL 0x1a31 +#define SEA_mmDCP1_PRESCALE_OVL_CONTROL 0x1d31 +#define SEA_mmDCP2_PRESCALE_OVL_CONTROL 0x4031 +#define SEA_mmDCP3_PRESCALE_OVL_CONTROL 0x4331 +#define SEA_mmDCP4_PRESCALE_OVL_CONTROL 0x4631 +#define SEA_mmDCP5_PRESCALE_OVL_CONTROL 0x4931 +#define SEA_mmPRESCALE_VALUES_OVL_CB 0x1a32 +#define SEA_mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32 +#define SEA_mmDCP1_PRESCALE_VALUES_OVL_CB 0x1d32 +#define SEA_mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 +#define SEA_mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 +#define SEA_mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 +#define SEA_mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 +#define SEA_mmPRESCALE_VALUES_OVL_Y 0x1a33 +#define SEA_mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33 +#define SEA_mmDCP1_PRESCALE_VALUES_OVL_Y 0x1d33 +#define SEA_mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 +#define SEA_mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 +#define SEA_mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 +#define SEA_mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 +#define SEA_mmPRESCALE_VALUES_OVL_CR 0x1a34 +#define SEA_mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34 +#define SEA_mmDCP1_PRESCALE_VALUES_OVL_CR 0x1d34 +#define SEA_mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 +#define SEA_mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 +#define SEA_mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 +#define SEA_mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 +#define SEA_mmINPUT_CSC_CONTROL 0x1a35 +#define SEA_mmDCP0_INPUT_CSC_CONTROL 0x1a35 +#define SEA_mmDCP1_INPUT_CSC_CONTROL 0x1d35 +#define SEA_mmDCP2_INPUT_CSC_CONTROL 0x4035 +#define SEA_mmDCP3_INPUT_CSC_CONTROL 0x4335 +#define SEA_mmDCP4_INPUT_CSC_CONTROL 0x4635 +#define SEA_mmDCP5_INPUT_CSC_CONTROL 0x4935 +#define SEA_mmINPUT_CSC_C11_C12 0x1a36 +#define SEA_mmDCP0_INPUT_CSC_C11_C12 0x1a36 +#define SEA_mmDCP1_INPUT_CSC_C11_C12 0x1d36 +#define SEA_mmDCP2_INPUT_CSC_C11_C12 0x4036 +#define SEA_mmDCP3_INPUT_CSC_C11_C12 0x4336 +#define SEA_mmDCP4_INPUT_CSC_C11_C12 0x4636 +#define SEA_mmDCP5_INPUT_CSC_C11_C12 0x4936 +#define SEA_mmINPUT_CSC_C13_C14 0x1a37 +#define SEA_mmDCP0_INPUT_CSC_C13_C14 0x1a37 +#define SEA_mmDCP1_INPUT_CSC_C13_C14 0x1d37 +#define SEA_mmDCP2_INPUT_CSC_C13_C14 0x4037 +#define SEA_mmDCP3_INPUT_CSC_C13_C14 0x4337 +#define SEA_mmDCP4_INPUT_CSC_C13_C14 0x4637 +#define SEA_mmDCP5_INPUT_CSC_C13_C14 0x4937 +#define SEA_mmINPUT_CSC_C21_C22 0x1a38 +#define SEA_mmDCP0_INPUT_CSC_C21_C22 0x1a38 +#define SEA_mmDCP1_INPUT_CSC_C21_C22 0x1d38 +#define SEA_mmDCP2_INPUT_CSC_C21_C22 0x4038 +#define SEA_mmDCP3_INPUT_CSC_C21_C22 0x4338 +#define SEA_mmDCP4_INPUT_CSC_C21_C22 0x4638 +#define SEA_mmDCP5_INPUT_CSC_C21_C22 0x4938 +#define SEA_mmINPUT_CSC_C23_C24 0x1a39 +#define SEA_mmDCP0_INPUT_CSC_C23_C24 0x1a39 +#define SEA_mmDCP1_INPUT_CSC_C23_C24 0x1d39 +#define SEA_mmDCP2_INPUT_CSC_C23_C24 0x4039 +#define SEA_mmDCP3_INPUT_CSC_C23_C24 0x4339 +#define SEA_mmDCP4_INPUT_CSC_C23_C24 0x4639 +#define SEA_mmDCP5_INPUT_CSC_C23_C24 0x4939 +#define SEA_mmINPUT_CSC_C31_C32 0x1a3a +#define SEA_mmDCP0_INPUT_CSC_C31_C32 0x1a3a +#define SEA_mmDCP1_INPUT_CSC_C31_C32 0x1d3a +#define SEA_mmDCP2_INPUT_CSC_C31_C32 0x403a +#define SEA_mmDCP3_INPUT_CSC_C31_C32 0x433a +#define SEA_mmDCP4_INPUT_CSC_C31_C32 0x463a +#define SEA_mmDCP5_INPUT_CSC_C31_C32 0x493a +#define SEA_mmINPUT_CSC_C33_C34 0x1a3b +#define SEA_mmDCP0_INPUT_CSC_C33_C34 0x1a3b +#define SEA_mmDCP1_INPUT_CSC_C33_C34 0x1d3b +#define SEA_mmDCP2_INPUT_CSC_C33_C34 0x403b +#define SEA_mmDCP3_INPUT_CSC_C33_C34 0x433b +#define SEA_mmDCP4_INPUT_CSC_C33_C34 0x463b +#define SEA_mmDCP5_INPUT_CSC_C33_C34 0x493b +#define SEA_mmOUTPUT_CSC_CONTROL 0x1a3c +#define SEA_mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c +#define SEA_mmDCP1_OUTPUT_CSC_CONTROL 0x1d3c +#define SEA_mmDCP2_OUTPUT_CSC_CONTROL 0x403c +#define SEA_mmDCP3_OUTPUT_CSC_CONTROL 0x433c +#define SEA_mmDCP4_OUTPUT_CSC_CONTROL 0x463c +#define SEA_mmDCP5_OUTPUT_CSC_CONTROL 0x493c +#define SEA_mmOUTPUT_CSC_C11_C12 0x1a3d +#define SEA_mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d +#define SEA_mmDCP1_OUTPUT_CSC_C11_C12 0x1d3d +#define SEA_mmDCP2_OUTPUT_CSC_C11_C12 0x403d +#define SEA_mmDCP3_OUTPUT_CSC_C11_C12 0x433d +#define SEA_mmDCP4_OUTPUT_CSC_C11_C12 0x463d +#define SEA_mmDCP5_OUTPUT_CSC_C11_C12 0x493d +#define SEA_mmOUTPUT_CSC_C13_C14 0x1a3e +#define SEA_mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e +#define SEA_mmDCP1_OUTPUT_CSC_C13_C14 0x1d3e +#define SEA_mmDCP2_OUTPUT_CSC_C13_C14 0x403e +#define SEA_mmDCP3_OUTPUT_CSC_C13_C14 0x433e +#define SEA_mmDCP4_OUTPUT_CSC_C13_C14 0x463e +#define SEA_mmDCP5_OUTPUT_CSC_C13_C14 0x493e +#define SEA_mmOUTPUT_CSC_C21_C22 0x1a3f +#define SEA_mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f +#define SEA_mmDCP1_OUTPUT_CSC_C21_C22 0x1d3f +#define SEA_mmDCP2_OUTPUT_CSC_C21_C22 0x403f +#define SEA_mmDCP3_OUTPUT_CSC_C21_C22 0x433f +#define SEA_mmDCP4_OUTPUT_CSC_C21_C22 0x463f +#define SEA_mmDCP5_OUTPUT_CSC_C21_C22 0x493f +#define SEA_mmOUTPUT_CSC_C23_C24 0x1a40 +#define SEA_mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 +#define SEA_mmDCP1_OUTPUT_CSC_C23_C24 0x1d40 +#define SEA_mmDCP2_OUTPUT_CSC_C23_C24 0x4040 +#define SEA_mmDCP3_OUTPUT_CSC_C23_C24 0x4340 +#define SEA_mmDCP4_OUTPUT_CSC_C23_C24 0x4640 +#define SEA_mmDCP5_OUTPUT_CSC_C23_C24 0x4940 +#define SEA_mmOUTPUT_CSC_C31_C32 0x1a41 +#define SEA_mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 +#define SEA_mmDCP1_OUTPUT_CSC_C31_C32 0x1d41 +#define SEA_mmDCP2_OUTPUT_CSC_C31_C32 0x4041 +#define SEA_mmDCP3_OUTPUT_CSC_C31_C32 0x4341 +#define SEA_mmDCP4_OUTPUT_CSC_C31_C32 0x4641 +#define SEA_mmDCP5_OUTPUT_CSC_C31_C32 0x4941 +#define SEA_mmOUTPUT_CSC_C33_C34 0x1a42 +#define SEA_mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 +#define SEA_mmDCP1_OUTPUT_CSC_C33_C34 0x1d42 +#define SEA_mmDCP2_OUTPUT_CSC_C33_C34 0x4042 +#define SEA_mmDCP3_OUTPUT_CSC_C33_C34 0x4342 +#define SEA_mmDCP4_OUTPUT_CSC_C33_C34 0x4642 +#define SEA_mmDCP5_OUTPUT_CSC_C33_C34 0x4942 +#define SEA_mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1d43 +#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 +#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 +#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 +#define SEA_mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1d44 +#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 +#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 +#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 +#define SEA_mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1d45 +#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 +#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 +#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 +#define SEA_mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1d46 +#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 +#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 +#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 +#define SEA_mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1d47 +#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 +#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 +#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 +#define SEA_mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1d48 +#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 +#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 +#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 +#define SEA_mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1d49 +#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 +#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 +#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 +#define SEA_mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1d4a +#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404a +#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434a +#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464a +#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494a +#define SEA_mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1d4b +#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404b +#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434b +#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464b +#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494b +#define SEA_mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1d4c +#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404c +#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434c +#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464c +#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494c +#define SEA_mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1d4d +#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404d +#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434d +#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464d +#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494d +#define SEA_mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1d4e +#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404e +#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434e +#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464e +#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494e +#define SEA_mmDENORM_CONTROL 0x1a50 +#define SEA_mmDCP0_DENORM_CONTROL 0x1a50 +#define SEA_mmDCP1_DENORM_CONTROL 0x1d50 +#define SEA_mmDCP2_DENORM_CONTROL 0x4050 +#define SEA_mmDCP3_DENORM_CONTROL 0x4350 +#define SEA_mmDCP4_DENORM_CONTROL 0x4650 +#define SEA_mmDCP5_DENORM_CONTROL 0x4950 +#define SEA_mmOUT_ROUND_CONTROL 0x1a51 +#define SEA_mmDCP0_OUT_ROUND_CONTROL 0x1a51 +#define SEA_mmDCP1_OUT_ROUND_CONTROL 0x1d51 +#define SEA_mmDCP2_OUT_ROUND_CONTROL 0x4051 +#define SEA_mmDCP3_OUT_ROUND_CONTROL 0x4351 +#define SEA_mmDCP4_OUT_ROUND_CONTROL 0x4651 +#define SEA_mmDCP5_OUT_ROUND_CONTROL 0x4951 +#define SEA_mmOUT_CLAMP_CONTROL_R_CR 0x1a52 +#define SEA_mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 +#define SEA_mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1d52 +#define SEA_mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x4052 +#define SEA_mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4352 +#define SEA_mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4652 +#define SEA_mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4952 +#define SEA_mmOUT_CLAMP_CONTROL_G_Y 0x1a9c +#define SEA_mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c +#define SEA_mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1d9c +#define SEA_mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x409c +#define SEA_mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x439c +#define SEA_mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x469c +#define SEA_mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x499c +#define SEA_mmOUT_CLAMP_CONTROL_B_CB 0x1a9d +#define SEA_mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d +#define SEA_mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1d9d +#define SEA_mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x409d +#define SEA_mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x439d +#define SEA_mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x469d +#define SEA_mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x499d +#define SEA_mmKEY_CONTROL 0x1a53 +#define SEA_mmDCP0_KEY_CONTROL 0x1a53 +#define SEA_mmDCP1_KEY_CONTROL 0x1d53 +#define SEA_mmDCP2_KEY_CONTROL 0x4053 +#define SEA_mmDCP3_KEY_CONTROL 0x4353 +#define SEA_mmDCP4_KEY_CONTROL 0x4653 +#define SEA_mmDCP5_KEY_CONTROL 0x4953 +#define SEA_mmKEY_RANGE_ALPHA 0x1a54 +#define SEA_mmDCP0_KEY_RANGE_ALPHA 0x1a54 +#define SEA_mmDCP1_KEY_RANGE_ALPHA 0x1d54 +#define SEA_mmDCP2_KEY_RANGE_ALPHA 0x4054 +#define SEA_mmDCP3_KEY_RANGE_ALPHA 0x4354 +#define SEA_mmDCP4_KEY_RANGE_ALPHA 0x4654 +#define SEA_mmDCP5_KEY_RANGE_ALPHA 0x4954 +#define SEA_mmKEY_RANGE_RED 0x1a55 +#define SEA_mmDCP0_KEY_RANGE_RED 0x1a55 +#define SEA_mmDCP1_KEY_RANGE_RED 0x1d55 +#define SEA_mmDCP2_KEY_RANGE_RED 0x4055 +#define SEA_mmDCP3_KEY_RANGE_RED 0x4355 +#define SEA_mmDCP4_KEY_RANGE_RED 0x4655 +#define SEA_mmDCP5_KEY_RANGE_RED 0x4955 +#define SEA_mmKEY_RANGE_GREEN 0x1a56 +#define SEA_mmDCP0_KEY_RANGE_GREEN 0x1a56 +#define SEA_mmDCP1_KEY_RANGE_GREEN 0x1d56 +#define SEA_mmDCP2_KEY_RANGE_GREEN 0x4056 +#define SEA_mmDCP3_KEY_RANGE_GREEN 0x4356 +#define SEA_mmDCP4_KEY_RANGE_GREEN 0x4656 +#define SEA_mmDCP5_KEY_RANGE_GREEN 0x4956 +#define SEA_mmKEY_RANGE_BLUE 0x1a57 +#define SEA_mmDCP0_KEY_RANGE_BLUE 0x1a57 +#define SEA_mmDCP1_KEY_RANGE_BLUE 0x1d57 +#define SEA_mmDCP2_KEY_RANGE_BLUE 0x4057 +#define SEA_mmDCP3_KEY_RANGE_BLUE 0x4357 +#define SEA_mmDCP4_KEY_RANGE_BLUE 0x4657 +#define SEA_mmDCP5_KEY_RANGE_BLUE 0x4957 +#define SEA_mmDEGAMMA_CONTROL 0x1a58 +#define SEA_mmDCP0_DEGAMMA_CONTROL 0x1a58 +#define SEA_mmDCP1_DEGAMMA_CONTROL 0x1d58 +#define SEA_mmDCP2_DEGAMMA_CONTROL 0x4058 +#define SEA_mmDCP3_DEGAMMA_CONTROL 0x4358 +#define SEA_mmDCP4_DEGAMMA_CONTROL 0x4658 +#define SEA_mmDCP5_DEGAMMA_CONTROL 0x4958 +#define SEA_mmGAMUT_REMAP_CONTROL 0x1a59 +#define SEA_mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 +#define SEA_mmDCP1_GAMUT_REMAP_CONTROL 0x1d59 +#define SEA_mmDCP2_GAMUT_REMAP_CONTROL 0x4059 +#define SEA_mmDCP3_GAMUT_REMAP_CONTROL 0x4359 +#define SEA_mmDCP4_GAMUT_REMAP_CONTROL 0x4659 +#define SEA_mmDCP5_GAMUT_REMAP_CONTROL 0x4959 +#define SEA_mmGAMUT_REMAP_C11_C12 0x1a5a +#define SEA_mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a +#define SEA_mmDCP1_GAMUT_REMAP_C11_C12 0x1d5a +#define SEA_mmDCP2_GAMUT_REMAP_C11_C12 0x405a +#define SEA_mmDCP3_GAMUT_REMAP_C11_C12 0x435a +#define SEA_mmDCP4_GAMUT_REMAP_C11_C12 0x465a +#define SEA_mmDCP5_GAMUT_REMAP_C11_C12 0x495a +#define SEA_mmGAMUT_REMAP_C13_C14 0x1a5b +#define SEA_mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b +#define SEA_mmDCP1_GAMUT_REMAP_C13_C14 0x1d5b +#define SEA_mmDCP2_GAMUT_REMAP_C13_C14 0x405b +#define SEA_mmDCP3_GAMUT_REMAP_C13_C14 0x435b +#define SEA_mmDCP4_GAMUT_REMAP_C13_C14 0x465b +#define SEA_mmDCP5_GAMUT_REMAP_C13_C14 0x495b +#define SEA_mmGAMUT_REMAP_C21_C22 0x1a5c +#define SEA_mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c +#define SEA_mmDCP1_GAMUT_REMAP_C21_C22 0x1d5c +#define SEA_mmDCP2_GAMUT_REMAP_C21_C22 0x405c +#define SEA_mmDCP3_GAMUT_REMAP_C21_C22 0x435c +#define SEA_mmDCP4_GAMUT_REMAP_C21_C22 0x465c +#define SEA_mmDCP5_GAMUT_REMAP_C21_C22 0x495c +#define SEA_mmGAMUT_REMAP_C23_C24 0x1a5d +#define SEA_mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d +#define SEA_mmDCP1_GAMUT_REMAP_C23_C24 0x1d5d +#define SEA_mmDCP2_GAMUT_REMAP_C23_C24 0x405d +#define SEA_mmDCP3_GAMUT_REMAP_C23_C24 0x435d +#define SEA_mmDCP4_GAMUT_REMAP_C23_C24 0x465d +#define SEA_mmDCP5_GAMUT_REMAP_C23_C24 0x495d +#define SEA_mmGAMUT_REMAP_C31_C32 0x1a5e +#define SEA_mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e +#define SEA_mmDCP1_GAMUT_REMAP_C31_C32 0x1d5e +#define SEA_mmDCP2_GAMUT_REMAP_C31_C32 0x405e +#define SEA_mmDCP3_GAMUT_REMAP_C31_C32 0x435e +#define SEA_mmDCP4_GAMUT_REMAP_C31_C32 0x465e +#define SEA_mmDCP5_GAMUT_REMAP_C31_C32 0x495e +#define SEA_mmGAMUT_REMAP_C33_C34 0x1a5f +#define SEA_mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f +#define SEA_mmDCP1_GAMUT_REMAP_C33_C34 0x1d5f +#define SEA_mmDCP2_GAMUT_REMAP_C33_C34 0x405f +#define SEA_mmDCP3_GAMUT_REMAP_C33_C34 0x435f +#define SEA_mmDCP4_GAMUT_REMAP_C33_C34 0x465f +#define SEA_mmDCP5_GAMUT_REMAP_C33_C34 0x495f +#define SEA_mmDCP_SPATIAL_DITHER_CNTL 0x1a60 +#define SEA_mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 +#define SEA_mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1d60 +#define SEA_mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define SEA_mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 +#define SEA_mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 +#define SEA_mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 +#define SEA_mmDCP_RANDOM_SEEDS 0x1a61 +#define SEA_mmDCP0_DCP_RANDOM_SEEDS 0x1a61 +#define SEA_mmDCP1_DCP_RANDOM_SEEDS 0x1d61 +#define SEA_mmDCP2_DCP_RANDOM_SEEDS 0x4061 +#define SEA_mmDCP3_DCP_RANDOM_SEEDS 0x4361 +#define SEA_mmDCP4_DCP_RANDOM_SEEDS 0x4661 +#define SEA_mmDCP5_DCP_RANDOM_SEEDS 0x4961 +#define SEA_mmDCP_FP_CONVERTED_FIELD 0x1a65 +#define SEA_mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 +#define SEA_mmDCP1_DCP_FP_CONVERTED_FIELD 0x1d65 +#define SEA_mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 +#define SEA_mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 +#define SEA_mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 +#define SEA_mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 +#define SEA_mmCUR_CONTROL 0x1a66 +#define SEA_mmDCP0_CUR_CONTROL 0x1a66 +#define SEA_mmDCP1_CUR_CONTROL 0x1d66 +#define SEA_mmDCP2_CUR_CONTROL 0x4066 +#define SEA_mmDCP3_CUR_CONTROL 0x4366 +#define SEA_mmDCP4_CUR_CONTROL 0x4666 +#define SEA_mmDCP5_CUR_CONTROL 0x4966 +#define SEA_mmCUR_SURFACE_ADDRESS 0x1a67 +#define SEA_mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 +#define SEA_mmDCP1_CUR_SURFACE_ADDRESS 0x1d67 +#define SEA_mmDCP2_CUR_SURFACE_ADDRESS 0x4067 +#define SEA_mmDCP3_CUR_SURFACE_ADDRESS 0x4367 +#define SEA_mmDCP4_CUR_SURFACE_ADDRESS 0x4667 +#define SEA_mmDCP5_CUR_SURFACE_ADDRESS 0x4967 +#define SEA_mmCUR_SIZE 0x1a68 +#define SEA_mmDCP0_CUR_SIZE 0x1a68 +#define SEA_mmDCP1_CUR_SIZE 0x1d68 +#define SEA_mmDCP2_CUR_SIZE 0x4068 +#define SEA_mmDCP3_CUR_SIZE 0x4368 +#define SEA_mmDCP4_CUR_SIZE 0x4668 +#define SEA_mmDCP5_CUR_SIZE 0x4968 +#define SEA_mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define SEA_mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define SEA_mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1d69 +#define SEA_mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define SEA_mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 +#define SEA_mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 +#define SEA_mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 +#define SEA_mmCUR_POSITION 0x1a6a +#define SEA_mmDCP0_CUR_POSITION 0x1a6a +#define SEA_mmDCP1_CUR_POSITION 0x1d6a +#define SEA_mmDCP2_CUR_POSITION 0x406a +#define SEA_mmDCP3_CUR_POSITION 0x436a +#define SEA_mmDCP4_CUR_POSITION 0x466a +#define SEA_mmDCP5_CUR_POSITION 0x496a +#define SEA_mmCUR_HOT_SPOT 0x1a6b +#define SEA_mmDCP0_CUR_HOT_SPOT 0x1a6b +#define SEA_mmDCP1_CUR_HOT_SPOT 0x1d6b +#define SEA_mmDCP2_CUR_HOT_SPOT 0x406b +#define SEA_mmDCP3_CUR_HOT_SPOT 0x436b +#define SEA_mmDCP4_CUR_HOT_SPOT 0x466b +#define SEA_mmDCP5_CUR_HOT_SPOT 0x496b +#define SEA_mmCUR_COLOR1 0x1a6c +#define SEA_mmDCP0_CUR_COLOR1 0x1a6c +#define SEA_mmDCP1_CUR_COLOR1 0x1d6c +#define SEA_mmDCP2_CUR_COLOR1 0x406c +#define SEA_mmDCP3_CUR_COLOR1 0x436c +#define SEA_mmDCP4_CUR_COLOR1 0x466c +#define SEA_mmDCP5_CUR_COLOR1 0x496c +#define SEA_mmCUR_COLOR2 0x1a6d +#define SEA_mmDCP0_CUR_COLOR2 0x1a6d +#define SEA_mmDCP1_CUR_COLOR2 0x1d6d +#define SEA_mmDCP2_CUR_COLOR2 0x406d +#define SEA_mmDCP3_CUR_COLOR2 0x436d +#define SEA_mmDCP4_CUR_COLOR2 0x466d +#define SEA_mmDCP5_CUR_COLOR2 0x496d +#define SEA_mmCUR_UPDATE 0x1a6e +#define SEA_mmDCP0_CUR_UPDATE 0x1a6e +#define SEA_mmDCP1_CUR_UPDATE 0x1d6e +#define SEA_mmDCP2_CUR_UPDATE 0x406e +#define SEA_mmDCP3_CUR_UPDATE 0x436e +#define SEA_mmDCP4_CUR_UPDATE 0x466e +#define SEA_mmDCP5_CUR_UPDATE 0x496e +#define SEA_mmCUR2_CONTROL 0x1a6f +#define SEA_mmDCP0_CUR2_CONTROL 0x1a6f +#define SEA_mmDCP1_CUR2_CONTROL 0x1d6f +#define SEA_mmDCP2_CUR2_CONTROL 0x406f +#define SEA_mmDCP3_CUR2_CONTROL 0x436f +#define SEA_mmDCP4_CUR2_CONTROL 0x466f +#define SEA_mmDCP5_CUR2_CONTROL 0x496f +#define SEA_mmCUR2_SURFACE_ADDRESS 0x1a70 +#define SEA_mmDCP0_CUR2_SURFACE_ADDRESS 0x1a70 +#define SEA_mmDCP1_CUR2_SURFACE_ADDRESS 0x1d70 +#define SEA_mmDCP2_CUR2_SURFACE_ADDRESS 0x4070 +#define SEA_mmDCP3_CUR2_SURFACE_ADDRESS 0x4370 +#define SEA_mmDCP4_CUR2_SURFACE_ADDRESS 0x4670 +#define SEA_mmDCP5_CUR2_SURFACE_ADDRESS 0x4970 +#define SEA_mmCUR2_SIZE 0x1a71 +#define SEA_mmDCP0_CUR2_SIZE 0x1a71 +#define SEA_mmDCP1_CUR2_SIZE 0x1d71 +#define SEA_mmDCP2_CUR2_SIZE 0x4071 +#define SEA_mmDCP3_CUR2_SIZE 0x4371 +#define SEA_mmDCP4_CUR2_SIZE 0x4671 +#define SEA_mmDCP5_CUR2_SIZE 0x4971 +#define SEA_mmCUR2_SURFACE_ADDRESS_HIGH 0x1a72 +#define SEA_mmDCP0_CUR2_SURFACE_ADDRESS_HIGH 0x1a72 +#define SEA_mmDCP1_CUR2_SURFACE_ADDRESS_HIGH 0x1d72 +#define SEA_mmDCP2_CUR2_SURFACE_ADDRESS_HIGH 0x4072 +#define SEA_mmDCP3_CUR2_SURFACE_ADDRESS_HIGH 0x4372 +#define SEA_mmDCP4_CUR2_SURFACE_ADDRESS_HIGH 0x4672 +#define SEA_mmDCP5_CUR2_SURFACE_ADDRESS_HIGH 0x4972 +#define SEA_mmCUR2_POSITION 0x1a73 +#define SEA_mmDCP0_CUR2_POSITION 0x1a73 +#define SEA_mmDCP1_CUR2_POSITION 0x1d73 +#define SEA_mmDCP2_CUR2_POSITION 0x4073 +#define SEA_mmDCP3_CUR2_POSITION 0x4373 +#define SEA_mmDCP4_CUR2_POSITION 0x4673 +#define SEA_mmDCP5_CUR2_POSITION 0x4973 +#define SEA_mmCUR2_HOT_SPOT 0x1a74 +#define SEA_mmDCP0_CUR2_HOT_SPOT 0x1a74 +#define SEA_mmDCP1_CUR2_HOT_SPOT 0x1d74 +#define SEA_mmDCP2_CUR2_HOT_SPOT 0x4074 +#define SEA_mmDCP3_CUR2_HOT_SPOT 0x4374 +#define SEA_mmDCP4_CUR2_HOT_SPOT 0x4674 +#define SEA_mmDCP5_CUR2_HOT_SPOT 0x4974 +#define SEA_mmCUR2_COLOR1 0x1a75 +#define SEA_mmDCP0_CUR2_COLOR1 0x1a75 +#define SEA_mmDCP1_CUR2_COLOR1 0x1d75 +#define SEA_mmDCP2_CUR2_COLOR1 0x4075 +#define SEA_mmDCP3_CUR2_COLOR1 0x4375 +#define SEA_mmDCP4_CUR2_COLOR1 0x4675 +#define SEA_mmDCP5_CUR2_COLOR1 0x4975 +#define SEA_mmCUR2_COLOR2 0x1a76 +#define SEA_mmDCP0_CUR2_COLOR2 0x1a76 +#define SEA_mmDCP1_CUR2_COLOR2 0x1d76 +#define SEA_mmDCP2_CUR2_COLOR2 0x4076 +#define SEA_mmDCP3_CUR2_COLOR2 0x4376 +#define SEA_mmDCP4_CUR2_COLOR2 0x4676 +#define SEA_mmDCP5_CUR2_COLOR2 0x4976 +#define SEA_mmCUR2_UPDATE 0x1a77 +#define SEA_mmDCP0_CUR2_UPDATE 0x1a77 +#define SEA_mmDCP1_CUR2_UPDATE 0x1d77 +#define SEA_mmDCP2_CUR2_UPDATE 0x4077 +#define SEA_mmDCP3_CUR2_UPDATE 0x4377 +#define SEA_mmDCP4_CUR2_UPDATE 0x4677 +#define SEA_mmDCP5_CUR2_UPDATE 0x4977 +#define SEA_mmCUR_REQUEST_FILTER_CNTL 0x1a99 +#define SEA_mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 +#define SEA_mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1d99 +#define SEA_mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 +#define SEA_mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 +#define SEA_mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 +#define SEA_mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 +#define SEA_mmCUR_STEREO_CONTROL 0x1a9a +#define SEA_mmDCP0_CUR_STEREO_CONTROL 0x1a9a +#define SEA_mmDCP1_CUR_STEREO_CONTROL 0x1d9a +#define SEA_mmDCP2_CUR_STEREO_CONTROL 0x409a +#define SEA_mmDCP3_CUR_STEREO_CONTROL 0x439a +#define SEA_mmDCP4_CUR_STEREO_CONTROL 0x469a +#define SEA_mmDCP5_CUR_STEREO_CONTROL 0x499a +#define SEA_mmCUR2_STEREO_CONTROL 0x1a9b +#define SEA_mmDCP0_CUR2_STEREO_CONTROL 0x1a9b +#define SEA_mmDCP1_CUR2_STEREO_CONTROL 0x1d9b +#define SEA_mmDCP2_CUR2_STEREO_CONTROL 0x409b +#define SEA_mmDCP3_CUR2_STEREO_CONTROL 0x439b +#define SEA_mmDCP4_CUR2_STEREO_CONTROL 0x469b +#define SEA_mmDCP5_CUR2_STEREO_CONTROL 0x499b +#define SEA_mmDC_LUT_RW_MODE 0x1a78 +#define SEA_mmDCP0_DC_LUT_RW_MODE 0x1a78 +#define SEA_mmDCP1_DC_LUT_RW_MODE 0x1d78 +#define SEA_mmDCP2_DC_LUT_RW_MODE 0x4078 +#define SEA_mmDCP3_DC_LUT_RW_MODE 0x4378 +#define SEA_mmDCP4_DC_LUT_RW_MODE 0x4678 +#define SEA_mmDCP5_DC_LUT_RW_MODE 0x4978 +#define SEA_mmDC_LUT_RW_INDEX 0x1a79 +#define SEA_mmDCP0_DC_LUT_RW_INDEX 0x1a79 +#define SEA_mmDCP1_DC_LUT_RW_INDEX 0x1d79 +#define SEA_mmDCP2_DC_LUT_RW_INDEX 0x4079 +#define SEA_mmDCP3_DC_LUT_RW_INDEX 0x4379 +#define SEA_mmDCP4_DC_LUT_RW_INDEX 0x4679 +#define SEA_mmDCP5_DC_LUT_RW_INDEX 0x4979 +#define SEA_mmDC_LUT_SEQ_COLOR 0x1a7a +#define SEA_mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a +#define SEA_mmDCP1_DC_LUT_SEQ_COLOR 0x1d7a +#define SEA_mmDCP2_DC_LUT_SEQ_COLOR 0x407a +#define SEA_mmDCP3_DC_LUT_SEQ_COLOR 0x437a +#define SEA_mmDCP4_DC_LUT_SEQ_COLOR 0x467a +#define SEA_mmDCP5_DC_LUT_SEQ_COLOR 0x497a +#define SEA_mmDC_LUT_PWL_DATA 0x1a7b +#define SEA_mmDCP0_DC_LUT_PWL_DATA 0x1a7b +#define SEA_mmDCP1_DC_LUT_PWL_DATA 0x1d7b +#define SEA_mmDCP2_DC_LUT_PWL_DATA 0x407b +#define SEA_mmDCP3_DC_LUT_PWL_DATA 0x437b +#define SEA_mmDCP4_DC_LUT_PWL_DATA 0x467b +#define SEA_mmDCP5_DC_LUT_PWL_DATA 0x497b +#define SEA_mmDC_LUT_30_COLOR 0x1a7c +#define SEA_mmDCP0_DC_LUT_30_COLOR 0x1a7c +#define SEA_mmDCP1_DC_LUT_30_COLOR 0x1d7c +#define SEA_mmDCP2_DC_LUT_30_COLOR 0x407c +#define SEA_mmDCP3_DC_LUT_30_COLOR 0x437c +#define SEA_mmDCP4_DC_LUT_30_COLOR 0x467c +#define SEA_mmDCP5_DC_LUT_30_COLOR 0x497c +#define SEA_mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define SEA_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define SEA_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1d7d +#define SEA_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407d +#define SEA_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437d +#define SEA_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467d +#define SEA_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497d +#define SEA_mmDC_LUT_WRITE_EN_MASK 0x1a7e +#define SEA_mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e +#define SEA_mmDCP1_DC_LUT_WRITE_EN_MASK 0x1d7e +#define SEA_mmDCP2_DC_LUT_WRITE_EN_MASK 0x407e +#define SEA_mmDCP3_DC_LUT_WRITE_EN_MASK 0x437e +#define SEA_mmDCP4_DC_LUT_WRITE_EN_MASK 0x467e +#define SEA_mmDCP5_DC_LUT_WRITE_EN_MASK 0x497e +#define SEA_mmDC_LUT_AUTOFILL 0x1a7f +#define SEA_mmDCP0_DC_LUT_AUTOFILL 0x1a7f +#define SEA_mmDCP1_DC_LUT_AUTOFILL 0x1d7f +#define SEA_mmDCP2_DC_LUT_AUTOFILL 0x407f +#define SEA_mmDCP3_DC_LUT_AUTOFILL 0x437f +#define SEA_mmDCP4_DC_LUT_AUTOFILL 0x467f +#define SEA_mmDCP5_DC_LUT_AUTOFILL 0x497f +#define SEA_mmDC_LUT_CONTROL 0x1a80 +#define SEA_mmDCP0_DC_LUT_CONTROL 0x1a80 +#define SEA_mmDCP1_DC_LUT_CONTROL 0x1d80 +#define SEA_mmDCP2_DC_LUT_CONTROL 0x4080 +#define SEA_mmDCP3_DC_LUT_CONTROL 0x4380 +#define SEA_mmDCP4_DC_LUT_CONTROL 0x4680 +#define SEA_mmDCP5_DC_LUT_CONTROL 0x4980 +#define SEA_mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1d81 +#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 +#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 +#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 +#define SEA_mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1d82 +#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 +#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 +#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 +#define SEA_mmDC_LUT_BLACK_OFFSET_RED 0x1a83 +#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 +#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1d83 +#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 +#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 +#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 +#define SEA_mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1d84 +#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 +#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 +#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 +#define SEA_mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1d85 +#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 +#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 +#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 +#define SEA_mmDC_LUT_WHITE_OFFSET_RED 0x1a86 +#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 +#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1d86 +#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 +#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 +#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 +#define SEA_mmDCP_CRC_CONTROL 0x1a87 +#define SEA_mmDCP0_DCP_CRC_CONTROL 0x1a87 +#define SEA_mmDCP1_DCP_CRC_CONTROL 0x1d87 +#define SEA_mmDCP2_DCP_CRC_CONTROL 0x4087 +#define SEA_mmDCP3_DCP_CRC_CONTROL 0x4387 +#define SEA_mmDCP4_DCP_CRC_CONTROL 0x4687 +#define SEA_mmDCP5_DCP_CRC_CONTROL 0x4987 +#define SEA_mmDCP_CRC_MASK 0x1a88 +#define SEA_mmDCP0_DCP_CRC_MASK 0x1a88 +#define SEA_mmDCP1_DCP_CRC_MASK 0x1d88 +#define SEA_mmDCP2_DCP_CRC_MASK 0x4088 +#define SEA_mmDCP3_DCP_CRC_MASK 0x4388 +#define SEA_mmDCP4_DCP_CRC_MASK 0x4688 +#define SEA_mmDCP5_DCP_CRC_MASK 0x4988 +#define SEA_mmDCP_CRC_CURRENT 0x1a89 +#define SEA_mmDCP0_DCP_CRC_CURRENT 0x1a89 +#define SEA_mmDCP1_DCP_CRC_CURRENT 0x1d89 +#define SEA_mmDCP2_DCP_CRC_CURRENT 0x4089 +#define SEA_mmDCP3_DCP_CRC_CURRENT 0x4389 +#define SEA_mmDCP4_DCP_CRC_CURRENT 0x4689 +#define SEA_mmDCP5_DCP_CRC_CURRENT 0x4989 +#define SEA_mmDCP_CRC_LAST 0x1a8b +#define SEA_mmDCP0_DCP_CRC_LAST 0x1a8b +#define SEA_mmDCP1_DCP_CRC_LAST 0x1d8b +#define SEA_mmDCP2_DCP_CRC_LAST 0x408b +#define SEA_mmDCP3_DCP_CRC_LAST 0x438b +#define SEA_mmDCP4_DCP_CRC_LAST 0x468b +#define SEA_mmDCP5_DCP_CRC_LAST 0x498b +#define SEA_mmDCP_DEBUG 0x1a8d +#define SEA_mmDCP0_DCP_DEBUG 0x1a8d +#define SEA_mmDCP1_DCP_DEBUG 0x1d8d +#define SEA_mmDCP2_DCP_DEBUG 0x408d +#define SEA_mmDCP3_DCP_DEBUG 0x438d +#define SEA_mmDCP4_DCP_DEBUG 0x468d +#define SEA_mmDCP5_DCP_DEBUG 0x498d +#define SEA_mmGRPH_FLIP_RATE_CNTL 0x1a8e +#define SEA_mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e +#define SEA_mmDCP1_GRPH_FLIP_RATE_CNTL 0x1d8e +#define SEA_mmDCP2_GRPH_FLIP_RATE_CNTL 0x408e +#define SEA_mmDCP3_GRPH_FLIP_RATE_CNTL 0x438e +#define SEA_mmDCP4_GRPH_FLIP_RATE_CNTL 0x468e +#define SEA_mmDCP5_GRPH_FLIP_RATE_CNTL 0x498e +#define SEA_mmDCP_GSL_CONTROL 0x1a90 +#define SEA_mmDCP0_DCP_GSL_CONTROL 0x1a90 +#define SEA_mmDCP1_DCP_GSL_CONTROL 0x1d90 +#define SEA_mmDCP2_DCP_GSL_CONTROL 0x4090 +#define SEA_mmDCP3_DCP_GSL_CONTROL 0x4390 +#define SEA_mmDCP4_DCP_GSL_CONTROL 0x4690 +#define SEA_mmDCP5_DCP_GSL_CONTROL 0x4990 +#define SEA_mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define SEA_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define SEA_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1d91 +#define SEA_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define SEA_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 +#define SEA_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 +#define SEA_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 +#define SEA_mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92 +#define SEA_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92 +#define SEA_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1d92 +#define SEA_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 +#define SEA_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 +#define SEA_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 +#define SEA_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 +#define SEA_mmOVL_STEREOSYNC_FLIP 0x1a93 +#define SEA_mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93 +#define SEA_mmDCP1_OVL_STEREOSYNC_FLIP 0x1d93 +#define SEA_mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 +#define SEA_mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 +#define SEA_mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 +#define SEA_mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 +#define SEA_mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 +#define SEA_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 +#define SEA_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d94 +#define SEA_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 +#define SEA_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 +#define SEA_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 +#define SEA_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 +#define SEA_mmDCP_TEST_DEBUG_INDEX 0x1a95 +#define SEA_mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 +#define SEA_mmDCP1_DCP_TEST_DEBUG_INDEX 0x1d95 +#define SEA_mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 +#define SEA_mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 +#define SEA_mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 +#define SEA_mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 +#define SEA_mmDCP_TEST_DEBUG_DATA 0x1a96 +#define SEA_mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 +#define SEA_mmDCP1_DCP_TEST_DEBUG_DATA 0x1d96 +#define SEA_mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 +#define SEA_mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 +#define SEA_mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 +#define SEA_mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 +#define SEA_mmGRPH_STEREOSYNC_FLIP 0x1a97 +#define SEA_mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 +#define SEA_mmDCP1_GRPH_STEREOSYNC_FLIP 0x1d97 +#define SEA_mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 +#define SEA_mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 +#define SEA_mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 +#define SEA_mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 +#define SEA_mmDCP_DEBUG2 0x1a98 +#define SEA_mmDCP0_DCP_DEBUG2 0x1a98 +#define SEA_mmDCP1_DCP_DEBUG2 0x1d98 +#define SEA_mmDCP2_DCP_DEBUG2 0x4098 +#define SEA_mmDCP3_DCP_DEBUG2 0x4398 +#define SEA_mmDCP4_DCP_DEBUG2 0x4698 +#define SEA_mmDCP5_DCP_DEBUG2 0x4998 +#define SEA_mmHW_ROTATION 0x1a9e +#define SEA_mmDCP0_HW_ROTATION 0x1a9e +#define SEA_mmDCP1_HW_ROTATION 0x1d9e +#define SEA_mmDCP2_HW_ROTATION 0x409e +#define SEA_mmDCP3_HW_ROTATION 0x439e +#define SEA_mmDCP4_HW_ROTATION 0x469e +#define SEA_mmDCP5_HW_ROTATION 0x499e +#define SEA_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define SEA_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define SEA_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1d9f +#define SEA_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f +#define SEA_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x439f +#define SEA_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x469f +#define SEA_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x499f +#define SEA_mmREGAMMA_CONTROL 0x1aa0 +#define SEA_mmDCP0_REGAMMA_CONTROL 0x1aa0 +#define SEA_mmDCP1_REGAMMA_CONTROL 0x1da0 +#define SEA_mmDCP2_REGAMMA_CONTROL 0x40a0 +#define SEA_mmDCP3_REGAMMA_CONTROL 0x43a0 +#define SEA_mmDCP4_REGAMMA_CONTROL 0x46a0 +#define SEA_mmDCP5_REGAMMA_CONTROL 0x49a0 +#define SEA_mmREGAMMA_LUT_INDEX 0x1aa1 +#define SEA_mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 +#define SEA_mmDCP1_REGAMMA_LUT_INDEX 0x1da1 +#define SEA_mmDCP2_REGAMMA_LUT_INDEX 0x40a1 +#define SEA_mmDCP3_REGAMMA_LUT_INDEX 0x43a1 +#define SEA_mmDCP4_REGAMMA_LUT_INDEX 0x46a1 +#define SEA_mmDCP5_REGAMMA_LUT_INDEX 0x49a1 +#define SEA_mmREGAMMA_LUT_DATA 0x1aa2 +#define SEA_mmDCP0_REGAMMA_LUT_DATA 0x1aa2 +#define SEA_mmDCP1_REGAMMA_LUT_DATA 0x1da2 +#define SEA_mmDCP2_REGAMMA_LUT_DATA 0x40a2 +#define SEA_mmDCP3_REGAMMA_LUT_DATA 0x43a2 +#define SEA_mmDCP4_REGAMMA_LUT_DATA 0x46a2 +#define SEA_mmDCP5_REGAMMA_LUT_DATA 0x49a2 +#define SEA_mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define SEA_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define SEA_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1da3 +#define SEA_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 +#define SEA_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43a3 +#define SEA_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46a3 +#define SEA_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49a3 +#define SEA_mmREGAMMA_CNTLA_START_CNTL 0x1aa4 +#define SEA_mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 +#define SEA_mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1da4 +#define SEA_mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40a4 +#define SEA_mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43a4 +#define SEA_mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46a4 +#define SEA_mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49a4 +#define SEA_mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define SEA_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define SEA_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1da5 +#define SEA_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 +#define SEA_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43a5 +#define SEA_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46a5 +#define SEA_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49a5 +#define SEA_mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define SEA_mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define SEA_mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1da6 +#define SEA_mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40a6 +#define SEA_mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43a6 +#define SEA_mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46a6 +#define SEA_mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49a6 +#define SEA_mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define SEA_mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define SEA_mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1da7 +#define SEA_mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40a7 +#define SEA_mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43a7 +#define SEA_mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46a7 +#define SEA_mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49a7 +#define SEA_mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1da8 +#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40a8 +#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43a8 +#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46a8 +#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49a8 +#define SEA_mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1da9 +#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40a9 +#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43a9 +#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46a9 +#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49a9 +#define SEA_mmREGAMMA_CNTLA_REGION_4_5 0x1aaa +#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa +#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1daa +#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40aa +#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43aa +#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46aa +#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49aa +#define SEA_mmREGAMMA_CNTLA_REGION_6_7 0x1aab +#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab +#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1dab +#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40ab +#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43ab +#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46ab +#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49ab +#define SEA_mmREGAMMA_CNTLA_REGION_8_9 0x1aac +#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac +#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1dac +#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40ac +#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43ac +#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46ac +#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49ac +#define SEA_mmREGAMMA_CNTLA_REGION_10_11 0x1aad +#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad +#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1dad +#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40ad +#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43ad +#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46ad +#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49ad +#define SEA_mmREGAMMA_CNTLA_REGION_12_13 0x1aae +#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae +#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1dae +#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40ae +#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43ae +#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46ae +#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49ae +#define SEA_mmREGAMMA_CNTLA_REGION_14_15 0x1aaf +#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf +#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1daf +#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40af +#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43af +#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46af +#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49af +#define SEA_mmREGAMMA_CNTLB_START_CNTL 0x1ab0 +#define SEA_mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 +#define SEA_mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1db0 +#define SEA_mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40b0 +#define SEA_mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43b0 +#define SEA_mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46b0 +#define SEA_mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49b0 +#define SEA_mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define SEA_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define SEA_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1db1 +#define SEA_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 +#define SEA_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43b1 +#define SEA_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46b1 +#define SEA_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49b1 +#define SEA_mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define SEA_mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define SEA_mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1db2 +#define SEA_mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40b2 +#define SEA_mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43b2 +#define SEA_mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46b2 +#define SEA_mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49b2 +#define SEA_mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define SEA_mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define SEA_mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1db3 +#define SEA_mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40b3 +#define SEA_mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43b3 +#define SEA_mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46b3 +#define SEA_mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49b3 +#define SEA_mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1db4 +#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40b4 +#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43b4 +#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46b4 +#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49b4 +#define SEA_mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1db5 +#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40b5 +#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43b5 +#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46b5 +#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49b5 +#define SEA_mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1db6 +#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40b6 +#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43b6 +#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46b6 +#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49b6 +#define SEA_mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1db7 +#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40b7 +#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43b7 +#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46b7 +#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49b7 +#define SEA_mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1db8 +#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40b8 +#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43b8 +#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46b8 +#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49b8 +#define SEA_mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1db9 +#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40b9 +#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43b9 +#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46b9 +#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49b9 +#define SEA_mmREGAMMA_CNTLB_REGION_12_13 0x1aba +#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba +#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1dba +#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40ba +#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43ba +#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46ba +#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49ba +#define SEA_mmREGAMMA_CNTLB_REGION_14_15 0x1abb +#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb +#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1dbb +#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40bb +#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43bb +#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46bb +#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49bb +#define SEA_mmALPHA_CONTROL 0x1abc +#define SEA_mmDCP0_ALPHA_CONTROL 0x1abc +#define SEA_mmDCP1_ALPHA_CONTROL 0x1dbc +#define SEA_mmDCP2_ALPHA_CONTROL 0x40bc +#define SEA_mmDCP3_ALPHA_CONTROL 0x43bc +#define SEA_mmDCP4_ALPHA_CONTROL 0x46bc +#define SEA_mmDCP5_ALPHA_CONTROL 0x49bc +#define SEA_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define SEA_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define SEA_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1dbd +#define SEA_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd +#define SEA_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x43bd +#define SEA_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x46bd +#define SEA_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x49bd +#define SEA_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define SEA_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define SEA_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1dbe +#define SEA_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be +#define SEA_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x43be +#define SEA_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x46be +#define SEA_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x49be +#define SEA_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define SEA_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define SEA_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1dbf +#define SEA_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf +#define SEA_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x43bf +#define SEA_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x46bf +#define SEA_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x49bf +#define SEA_mmDIG_FE_CNTL 0x1c00 +#define SEA_mmDIG0_DIG_FE_CNTL 0x1c00 +#define SEA_mmDIG1_DIG_FE_CNTL 0x1f00 +#define SEA_mmDIG2_DIG_FE_CNTL 0x4200 +#define SEA_mmDIG3_DIG_FE_CNTL 0x4500 +#define SEA_mmDIG4_DIG_FE_CNTL 0x4800 +#define SEA_mmDIG5_DIG_FE_CNTL 0x4b00 +#define SEA_mmDIG6_DIG_FE_CNTL 0x4e00 +#define SEA_mmDIG_OUTPUT_CRC_CNTL 0x1c01 +#define SEA_mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1c01 +#define SEA_mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1f01 +#define SEA_mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 +#define SEA_mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 +#define SEA_mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 +#define SEA_mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4b01 +#define SEA_mmDIG6_DIG_OUTPUT_CRC_CNTL 0x4e01 +#define SEA_mmDIG_OUTPUT_CRC_RESULT 0x1c02 +#define SEA_mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1c02 +#define SEA_mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1f02 +#define SEA_mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 +#define SEA_mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 +#define SEA_mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 +#define SEA_mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4b02 +#define SEA_mmDIG6_DIG_OUTPUT_CRC_RESULT 0x4e02 +#define SEA_mmDIG_CLOCK_PATTERN 0x1c03 +#define SEA_mmDIG0_DIG_CLOCK_PATTERN 0x1c03 +#define SEA_mmDIG1_DIG_CLOCK_PATTERN 0x1f03 +#define SEA_mmDIG2_DIG_CLOCK_PATTERN 0x4203 +#define SEA_mmDIG3_DIG_CLOCK_PATTERN 0x4503 +#define SEA_mmDIG4_DIG_CLOCK_PATTERN 0x4803 +#define SEA_mmDIG5_DIG_CLOCK_PATTERN 0x4b03 +#define SEA_mmDIG6_DIG_CLOCK_PATTERN 0x4e03 +#define SEA_mmDIG_TEST_PATTERN 0x1c04 +#define SEA_mmDIG0_DIG_TEST_PATTERN 0x1c04 +#define SEA_mmDIG1_DIG_TEST_PATTERN 0x1f04 +#define SEA_mmDIG2_DIG_TEST_PATTERN 0x4204 +#define SEA_mmDIG3_DIG_TEST_PATTERN 0x4504 +#define SEA_mmDIG4_DIG_TEST_PATTERN 0x4804 +#define SEA_mmDIG5_DIG_TEST_PATTERN 0x4b04 +#define SEA_mmDIG6_DIG_TEST_PATTERN 0x4e04 +#define SEA_mmDIG_RANDOM_PATTERN_SEED 0x1c05 +#define SEA_mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1c05 +#define SEA_mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1f05 +#define SEA_mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 +#define SEA_mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 +#define SEA_mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 +#define SEA_mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4b05 +#define SEA_mmDIG6_DIG_RANDOM_PATTERN_SEED 0x4e05 +#define SEA_mmDIG_FIFO_STATUS 0x1c0a +#define SEA_mmDIG0_DIG_FIFO_STATUS 0x1c0a +#define SEA_mmDIG1_DIG_FIFO_STATUS 0x1f0a +#define SEA_mmDIG2_DIG_FIFO_STATUS 0x420a +#define SEA_mmDIG3_DIG_FIFO_STATUS 0x450a +#define SEA_mmDIG4_DIG_FIFO_STATUS 0x480a +#define SEA_mmDIG5_DIG_FIFO_STATUS 0x4b0a +#define SEA_mmDIG6_DIG_FIFO_STATUS 0x4e0a +#define SEA_mmDIG_DISPCLK_SWITCH_CNTL 0x1c08 +#define SEA_mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1c08 +#define SEA_mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1f08 +#define SEA_mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 +#define SEA_mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 +#define SEA_mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 +#define SEA_mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4b08 +#define SEA_mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x4e08 +#define SEA_mmDIG_DISPCLK_SWITCH_STATUS 0x1c09 +#define SEA_mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1c09 +#define SEA_mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1f09 +#define SEA_mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 +#define SEA_mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 +#define SEA_mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 +#define SEA_mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4b09 +#define SEA_mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x4e09 +#define SEA_mmHDMI_CONTROL 0x1c0c +#define SEA_mmDIG0_HDMI_CONTROL 0x1c0c +#define SEA_mmDIG1_HDMI_CONTROL 0x1f0c +#define SEA_mmDIG2_HDMI_CONTROL 0x420c +#define SEA_mmDIG3_HDMI_CONTROL 0x450c +#define SEA_mmDIG4_HDMI_CONTROL 0x480c +#define SEA_mmDIG5_HDMI_CONTROL 0x4b0c +#define SEA_mmDIG6_HDMI_CONTROL 0x4e0c +#define SEA_mmHDMI_STATUS 0x1c0d +#define SEA_mmDIG0_HDMI_STATUS 0x1c0d +#define SEA_mmDIG1_HDMI_STATUS 0x1f0d +#define SEA_mmDIG2_HDMI_STATUS 0x420d +#define SEA_mmDIG3_HDMI_STATUS 0x450d +#define SEA_mmDIG4_HDMI_STATUS 0x480d +#define SEA_mmDIG5_HDMI_STATUS 0x4b0d +#define SEA_mmDIG6_HDMI_STATUS 0x4e0d +#define SEA_mmHDMI_AUDIO_PACKET_CONTROL 0x1c0e +#define SEA_mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1c0e +#define SEA_mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1f0e +#define SEA_mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420e +#define SEA_mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450e +#define SEA_mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480e +#define SEA_mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4b0e +#define SEA_mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x4e0e +#define SEA_mmHDMI_ACR_PACKET_CONTROL 0x1c0f +#define SEA_mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1c0f +#define SEA_mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1f0f +#define SEA_mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420f +#define SEA_mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450f +#define SEA_mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480f +#define SEA_mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4b0f +#define SEA_mmDIG6_HDMI_ACR_PACKET_CONTROL 0x4e0f +#define SEA_mmHDMI_VBI_PACKET_CONTROL 0x1c10 +#define SEA_mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1c10 +#define SEA_mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1f10 +#define SEA_mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 +#define SEA_mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 +#define SEA_mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 +#define SEA_mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4b10 +#define SEA_mmDIG6_HDMI_VBI_PACKET_CONTROL 0x4e10 +#define SEA_mmHDMI_INFOFRAME_CONTROL0 0x1c11 +#define SEA_mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1c11 +#define SEA_mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1f11 +#define SEA_mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 +#define SEA_mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 +#define SEA_mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 +#define SEA_mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4b11 +#define SEA_mmDIG6_HDMI_INFOFRAME_CONTROL0 0x4e11 +#define SEA_mmHDMI_INFOFRAME_CONTROL1 0x1c12 +#define SEA_mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1c12 +#define SEA_mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1f12 +#define SEA_mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 +#define SEA_mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 +#define SEA_mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 +#define SEA_mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4b12 +#define SEA_mmDIG6_HDMI_INFOFRAME_CONTROL1 0x4e12 +#define SEA_mmHDMI_GENERIC_PACKET_CONTROL0 0x1c13 +#define SEA_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1c13 +#define SEA_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1f13 +#define SEA_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 +#define SEA_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 +#define SEA_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 +#define SEA_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4b13 +#define SEA_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x4e13 +#define SEA_mmAFMT_INTERRUPT_STATUS 0x1c14 +#define SEA_mmDIG0_AFMT_INTERRUPT_STATUS 0x1c14 +#define SEA_mmDIG1_AFMT_INTERRUPT_STATUS 0x1f14 +#define SEA_mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 +#define SEA_mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 +#define SEA_mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 +#define SEA_mmDIG5_AFMT_INTERRUPT_STATUS 0x4b14 +#define SEA_mmDIG6_AFMT_INTERRUPT_STATUS 0x4e14 +#define SEA_mmHDMI_GC 0x1c16 +#define SEA_mmDIG0_HDMI_GC 0x1c16 +#define SEA_mmDIG1_HDMI_GC 0x1f16 +#define SEA_mmDIG2_HDMI_GC 0x4216 +#define SEA_mmDIG3_HDMI_GC 0x4516 +#define SEA_mmDIG4_HDMI_GC 0x4816 +#define SEA_mmDIG5_HDMI_GC 0x4b16 +#define SEA_mmDIG6_HDMI_GC 0x4e16 +#define SEA_mmAFMT_AUDIO_PACKET_CONTROL2 0x1c17 +#define SEA_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1c17 +#define SEA_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1f17 +#define SEA_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 +#define SEA_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 +#define SEA_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 +#define SEA_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4b17 +#define SEA_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x4e17 +#define SEA_mmAFMT_ISRC1_0 0x1c18 +#define SEA_mmDIG0_AFMT_ISRC1_0 0x1c18 +#define SEA_mmDIG1_AFMT_ISRC1_0 0x1f18 +#define SEA_mmDIG2_AFMT_ISRC1_0 0x4218 +#define SEA_mmDIG3_AFMT_ISRC1_0 0x4518 +#define SEA_mmDIG4_AFMT_ISRC1_0 0x4818 +#define SEA_mmDIG5_AFMT_ISRC1_0 0x4b18 +#define SEA_mmDIG6_AFMT_ISRC1_0 0x4e18 +#define SEA_mmAFMT_ISRC1_1 0x1c19 +#define SEA_mmDIG0_AFMT_ISRC1_1 0x1c19 +#define SEA_mmDIG1_AFMT_ISRC1_1 0x1f19 +#define SEA_mmDIG2_AFMT_ISRC1_1 0x4219 +#define SEA_mmDIG3_AFMT_ISRC1_1 0x4519 +#define SEA_mmDIG4_AFMT_ISRC1_1 0x4819 +#define SEA_mmDIG5_AFMT_ISRC1_1 0x4b19 +#define SEA_mmDIG6_AFMT_ISRC1_1 0x4e19 +#define SEA_mmAFMT_ISRC1_2 0x1c1a +#define SEA_mmDIG0_AFMT_ISRC1_2 0x1c1a +#define SEA_mmDIG1_AFMT_ISRC1_2 0x1f1a +#define SEA_mmDIG2_AFMT_ISRC1_2 0x421a +#define SEA_mmDIG3_AFMT_ISRC1_2 0x451a +#define SEA_mmDIG4_AFMT_ISRC1_2 0x481a +#define SEA_mmDIG5_AFMT_ISRC1_2 0x4b1a +#define SEA_mmDIG6_AFMT_ISRC1_2 0x4e1a +#define SEA_mmAFMT_ISRC1_3 0x1c1b +#define SEA_mmDIG0_AFMT_ISRC1_3 0x1c1b +#define SEA_mmDIG1_AFMT_ISRC1_3 0x1f1b +#define SEA_mmDIG2_AFMT_ISRC1_3 0x421b +#define SEA_mmDIG3_AFMT_ISRC1_3 0x451b +#define SEA_mmDIG4_AFMT_ISRC1_3 0x481b +#define SEA_mmDIG5_AFMT_ISRC1_3 0x4b1b +#define SEA_mmDIG6_AFMT_ISRC1_3 0x4e1b +#define SEA_mmAFMT_ISRC1_4 0x1c1c +#define SEA_mmDIG0_AFMT_ISRC1_4 0x1c1c +#define SEA_mmDIG1_AFMT_ISRC1_4 0x1f1c +#define SEA_mmDIG2_AFMT_ISRC1_4 0x421c +#define SEA_mmDIG3_AFMT_ISRC1_4 0x451c +#define SEA_mmDIG4_AFMT_ISRC1_4 0x481c +#define SEA_mmDIG5_AFMT_ISRC1_4 0x4b1c +#define SEA_mmDIG6_AFMT_ISRC1_4 0x4e1c +#define SEA_mmAFMT_ISRC2_0 0x1c1d +#define SEA_mmDIG0_AFMT_ISRC2_0 0x1c1d +#define SEA_mmDIG1_AFMT_ISRC2_0 0x1f1d +#define SEA_mmDIG2_AFMT_ISRC2_0 0x421d +#define SEA_mmDIG3_AFMT_ISRC2_0 0x451d +#define SEA_mmDIG4_AFMT_ISRC2_0 0x481d +#define SEA_mmDIG5_AFMT_ISRC2_0 0x4b1d +#define SEA_mmDIG6_AFMT_ISRC2_0 0x4e1d +#define SEA_mmAFMT_ISRC2_1 0x1c1e +#define SEA_mmDIG0_AFMT_ISRC2_1 0x1c1e +#define SEA_mmDIG1_AFMT_ISRC2_1 0x1f1e +#define SEA_mmDIG2_AFMT_ISRC2_1 0x421e +#define SEA_mmDIG3_AFMT_ISRC2_1 0x451e +#define SEA_mmDIG4_AFMT_ISRC2_1 0x481e +#define SEA_mmDIG5_AFMT_ISRC2_1 0x4b1e +#define SEA_mmDIG6_AFMT_ISRC2_1 0x4e1e +#define SEA_mmAFMT_ISRC2_2 0x1c1f +#define SEA_mmDIG0_AFMT_ISRC2_2 0x1c1f +#define SEA_mmDIG1_AFMT_ISRC2_2 0x1f1f +#define SEA_mmDIG2_AFMT_ISRC2_2 0x421f +#define SEA_mmDIG3_AFMT_ISRC2_2 0x451f +#define SEA_mmDIG4_AFMT_ISRC2_2 0x481f +#define SEA_mmDIG5_AFMT_ISRC2_2 0x4b1f +#define SEA_mmDIG6_AFMT_ISRC2_2 0x4e1f +#define SEA_mmAFMT_ISRC2_3 0x1c20 +#define SEA_mmDIG0_AFMT_ISRC2_3 0x1c20 +#define SEA_mmDIG1_AFMT_ISRC2_3 0x1f20 +#define SEA_mmDIG2_AFMT_ISRC2_3 0x4220 +#define SEA_mmDIG3_AFMT_ISRC2_3 0x4520 +#define SEA_mmDIG4_AFMT_ISRC2_3 0x4820 +#define SEA_mmDIG5_AFMT_ISRC2_3 0x4b20 +#define SEA_mmDIG6_AFMT_ISRC2_3 0x4e20 +#define SEA_mmAFMT_AVI_INFO0 0x1c21 +#define SEA_mmDIG0_AFMT_AVI_INFO0 0x1c21 +#define SEA_mmDIG1_AFMT_AVI_INFO0 0x1f21 +#define SEA_mmDIG2_AFMT_AVI_INFO0 0x4221 +#define SEA_mmDIG3_AFMT_AVI_INFO0 0x4521 +#define SEA_mmDIG4_AFMT_AVI_INFO0 0x4821 +#define SEA_mmDIG5_AFMT_AVI_INFO0 0x4b21 +#define SEA_mmDIG6_AFMT_AVI_INFO0 0x4e21 +#define SEA_mmAFMT_AVI_INFO1 0x1c22 +#define SEA_mmDIG0_AFMT_AVI_INFO1 0x1c22 +#define SEA_mmDIG1_AFMT_AVI_INFO1 0x1f22 +#define SEA_mmDIG2_AFMT_AVI_INFO1 0x4222 +#define SEA_mmDIG3_AFMT_AVI_INFO1 0x4522 +#define SEA_mmDIG4_AFMT_AVI_INFO1 0x4822 +#define SEA_mmDIG5_AFMT_AVI_INFO1 0x4b22 +#define SEA_mmDIG6_AFMT_AVI_INFO1 0x4e22 +#define SEA_mmAFMT_AVI_INFO2 0x1c23 +#define SEA_mmDIG0_AFMT_AVI_INFO2 0x1c23 +#define SEA_mmDIG1_AFMT_AVI_INFO2 0x1f23 +#define SEA_mmDIG2_AFMT_AVI_INFO2 0x4223 +#define SEA_mmDIG3_AFMT_AVI_INFO2 0x4523 +#define SEA_mmDIG4_AFMT_AVI_INFO2 0x4823 +#define SEA_mmDIG5_AFMT_AVI_INFO2 0x4b23 +#define SEA_mmDIG6_AFMT_AVI_INFO2 0x4e23 +#define SEA_mmAFMT_AVI_INFO3 0x1c24 +#define SEA_mmDIG0_AFMT_AVI_INFO3 0x1c24 +#define SEA_mmDIG1_AFMT_AVI_INFO3 0x1f24 +#define SEA_mmDIG2_AFMT_AVI_INFO3 0x4224 +#define SEA_mmDIG3_AFMT_AVI_INFO3 0x4524 +#define SEA_mmDIG4_AFMT_AVI_INFO3 0x4824 +#define SEA_mmDIG5_AFMT_AVI_INFO3 0x4b24 +#define SEA_mmDIG6_AFMT_AVI_INFO3 0x4e24 +#define SEA_mmAFMT_MPEG_INFO0 0x1c25 +#define SEA_mmDIG0_AFMT_MPEG_INFO0 0x1c25 +#define SEA_mmDIG1_AFMT_MPEG_INFO0 0x1f25 +#define SEA_mmDIG2_AFMT_MPEG_INFO0 0x4225 +#define SEA_mmDIG3_AFMT_MPEG_INFO0 0x4525 +#define SEA_mmDIG4_AFMT_MPEG_INFO0 0x4825 +#define SEA_mmDIG5_AFMT_MPEG_INFO0 0x4b25 +#define SEA_mmDIG6_AFMT_MPEG_INFO0 0x4e25 +#define SEA_mmAFMT_MPEG_INFO1 0x1c26 +#define SEA_mmDIG0_AFMT_MPEG_INFO1 0x1c26 +#define SEA_mmDIG1_AFMT_MPEG_INFO1 0x1f26 +#define SEA_mmDIG2_AFMT_MPEG_INFO1 0x4226 +#define SEA_mmDIG3_AFMT_MPEG_INFO1 0x4526 +#define SEA_mmDIG4_AFMT_MPEG_INFO1 0x4826 +#define SEA_mmDIG5_AFMT_MPEG_INFO1 0x4b26 +#define SEA_mmDIG6_AFMT_MPEG_INFO1 0x4e26 +#define SEA_mmAFMT_GENERIC_HDR 0x1c27 +#define SEA_mmDIG0_AFMT_GENERIC_HDR 0x1c27 +#define SEA_mmDIG1_AFMT_GENERIC_HDR 0x1f27 +#define SEA_mmDIG2_AFMT_GENERIC_HDR 0x4227 +#define SEA_mmDIG3_AFMT_GENERIC_HDR 0x4527 +#define SEA_mmDIG4_AFMT_GENERIC_HDR 0x4827 +#define SEA_mmDIG5_AFMT_GENERIC_HDR 0x4b27 +#define SEA_mmDIG6_AFMT_GENERIC_HDR 0x4e27 +#define SEA_mmAFMT_GENERIC_0 0x1c28 +#define SEA_mmDIG0_AFMT_GENERIC_0 0x1c28 +#define SEA_mmDIG1_AFMT_GENERIC_0 0x1f28 +#define SEA_mmDIG2_AFMT_GENERIC_0 0x4228 +#define SEA_mmDIG3_AFMT_GENERIC_0 0x4528 +#define SEA_mmDIG4_AFMT_GENERIC_0 0x4828 +#define SEA_mmDIG5_AFMT_GENERIC_0 0x4b28 +#define SEA_mmDIG6_AFMT_GENERIC_0 0x4e28 +#define SEA_mmAFMT_GENERIC_1 0x1c29 +#define SEA_mmDIG0_AFMT_GENERIC_1 0x1c29 +#define SEA_mmDIG1_AFMT_GENERIC_1 0x1f29 +#define SEA_mmDIG2_AFMT_GENERIC_1 0x4229 +#define SEA_mmDIG3_AFMT_GENERIC_1 0x4529 +#define SEA_mmDIG4_AFMT_GENERIC_1 0x4829 +#define SEA_mmDIG5_AFMT_GENERIC_1 0x4b29 +#define SEA_mmDIG6_AFMT_GENERIC_1 0x4e29 +#define SEA_mmAFMT_GENERIC_2 0x1c2a +#define SEA_mmDIG0_AFMT_GENERIC_2 0x1c2a +#define SEA_mmDIG1_AFMT_GENERIC_2 0x1f2a +#define SEA_mmDIG2_AFMT_GENERIC_2 0x422a +#define SEA_mmDIG3_AFMT_GENERIC_2 0x452a +#define SEA_mmDIG4_AFMT_GENERIC_2 0x482a +#define SEA_mmDIG5_AFMT_GENERIC_2 0x4b2a +#define SEA_mmDIG6_AFMT_GENERIC_2 0x4e2a +#define SEA_mmAFMT_GENERIC_3 0x1c2b +#define SEA_mmDIG0_AFMT_GENERIC_3 0x1c2b +#define SEA_mmDIG1_AFMT_GENERIC_3 0x1f2b +#define SEA_mmDIG2_AFMT_GENERIC_3 0x422b +#define SEA_mmDIG3_AFMT_GENERIC_3 0x452b +#define SEA_mmDIG4_AFMT_GENERIC_3 0x482b +#define SEA_mmDIG5_AFMT_GENERIC_3 0x4b2b +#define SEA_mmDIG6_AFMT_GENERIC_3 0x4e2b +#define SEA_mmAFMT_GENERIC_4 0x1c2c +#define SEA_mmDIG0_AFMT_GENERIC_4 0x1c2c +#define SEA_mmDIG1_AFMT_GENERIC_4 0x1f2c +#define SEA_mmDIG2_AFMT_GENERIC_4 0x422c +#define SEA_mmDIG3_AFMT_GENERIC_4 0x452c +#define SEA_mmDIG4_AFMT_GENERIC_4 0x482c +#define SEA_mmDIG5_AFMT_GENERIC_4 0x4b2c +#define SEA_mmDIG6_AFMT_GENERIC_4 0x4e2c +#define SEA_mmAFMT_GENERIC_5 0x1c2d +#define SEA_mmDIG0_AFMT_GENERIC_5 0x1c2d +#define SEA_mmDIG1_AFMT_GENERIC_5 0x1f2d +#define SEA_mmDIG2_AFMT_GENERIC_5 0x422d +#define SEA_mmDIG3_AFMT_GENERIC_5 0x452d +#define SEA_mmDIG4_AFMT_GENERIC_5 0x482d +#define SEA_mmDIG5_AFMT_GENERIC_5 0x4b2d +#define SEA_mmDIG6_AFMT_GENERIC_5 0x4e2d +#define SEA_mmAFMT_GENERIC_6 0x1c2e +#define SEA_mmDIG0_AFMT_GENERIC_6 0x1c2e +#define SEA_mmDIG1_AFMT_GENERIC_6 0x1f2e +#define SEA_mmDIG2_AFMT_GENERIC_6 0x422e +#define SEA_mmDIG3_AFMT_GENERIC_6 0x452e +#define SEA_mmDIG4_AFMT_GENERIC_6 0x482e +#define SEA_mmDIG5_AFMT_GENERIC_6 0x4b2e +#define SEA_mmDIG6_AFMT_GENERIC_6 0x4e2e +#define SEA_mmAFMT_GENERIC_7 0x1c2f +#define SEA_mmDIG0_AFMT_GENERIC_7 0x1c2f +#define SEA_mmDIG1_AFMT_GENERIC_7 0x1f2f +#define SEA_mmDIG2_AFMT_GENERIC_7 0x422f +#define SEA_mmDIG3_AFMT_GENERIC_7 0x452f +#define SEA_mmDIG4_AFMT_GENERIC_7 0x482f +#define SEA_mmDIG5_AFMT_GENERIC_7 0x4b2f +#define SEA_mmDIG6_AFMT_GENERIC_7 0x4e2f +#define SEA_mmHDMI_GENERIC_PACKET_CONTROL1 0x1c30 +#define SEA_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1c30 +#define SEA_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1f30 +#define SEA_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 +#define SEA_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 +#define SEA_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 +#define SEA_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4b30 +#define SEA_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x4e30 +#define SEA_mmHDMI_ACR_32_0 0x1c37 +#define SEA_mmDIG0_HDMI_ACR_32_0 0x1c37 +#define SEA_mmDIG1_HDMI_ACR_32_0 0x1f37 +#define SEA_mmDIG2_HDMI_ACR_32_0 0x4237 +#define SEA_mmDIG3_HDMI_ACR_32_0 0x4537 +#define SEA_mmDIG4_HDMI_ACR_32_0 0x4837 +#define SEA_mmDIG5_HDMI_ACR_32_0 0x4b37 +#define SEA_mmDIG6_HDMI_ACR_32_0 0x4e37 +#define SEA_mmHDMI_ACR_32_1 0x1c38 +#define SEA_mmDIG0_HDMI_ACR_32_1 0x1c38 +#define SEA_mmDIG1_HDMI_ACR_32_1 0x1f38 +#define SEA_mmDIG2_HDMI_ACR_32_1 0x4238 +#define SEA_mmDIG3_HDMI_ACR_32_1 0x4538 +#define SEA_mmDIG4_HDMI_ACR_32_1 0x4838 +#define SEA_mmDIG5_HDMI_ACR_32_1 0x4b38 +#define SEA_mmDIG6_HDMI_ACR_32_1 0x4e38 +#define SEA_mmHDMI_ACR_44_0 0x1c39 +#define SEA_mmDIG0_HDMI_ACR_44_0 0x1c39 +#define SEA_mmDIG1_HDMI_ACR_44_0 0x1f39 +#define SEA_mmDIG2_HDMI_ACR_44_0 0x4239 +#define SEA_mmDIG3_HDMI_ACR_44_0 0x4539 +#define SEA_mmDIG4_HDMI_ACR_44_0 0x4839 +#define SEA_mmDIG5_HDMI_ACR_44_0 0x4b39 +#define SEA_mmDIG6_HDMI_ACR_44_0 0x4e39 +#define SEA_mmHDMI_ACR_44_1 0x1c3a +#define SEA_mmDIG0_HDMI_ACR_44_1 0x1c3a +#define SEA_mmDIG1_HDMI_ACR_44_1 0x1f3a +#define SEA_mmDIG2_HDMI_ACR_44_1 0x423a +#define SEA_mmDIG3_HDMI_ACR_44_1 0x453a +#define SEA_mmDIG4_HDMI_ACR_44_1 0x483a +#define SEA_mmDIG5_HDMI_ACR_44_1 0x4b3a +#define SEA_mmDIG6_HDMI_ACR_44_1 0x4e3a +#define SEA_mmHDMI_ACR_48_0 0x1c3b +#define SEA_mmDIG0_HDMI_ACR_48_0 0x1c3b +#define SEA_mmDIG1_HDMI_ACR_48_0 0x1f3b +#define SEA_mmDIG2_HDMI_ACR_48_0 0x423b +#define SEA_mmDIG3_HDMI_ACR_48_0 0x453b +#define SEA_mmDIG4_HDMI_ACR_48_0 0x483b +#define SEA_mmDIG5_HDMI_ACR_48_0 0x4b3b +#define SEA_mmDIG6_HDMI_ACR_48_0 0x4e3b +#define SEA_mmHDMI_ACR_48_1 0x1c3c +#define SEA_mmDIG0_HDMI_ACR_48_1 0x1c3c +#define SEA_mmDIG1_HDMI_ACR_48_1 0x1f3c +#define SEA_mmDIG2_HDMI_ACR_48_1 0x423c +#define SEA_mmDIG3_HDMI_ACR_48_1 0x453c +#define SEA_mmDIG4_HDMI_ACR_48_1 0x483c +#define SEA_mmDIG5_HDMI_ACR_48_1 0x4b3c +#define SEA_mmDIG6_HDMI_ACR_48_1 0x4e3c +#define SEA_mmHDMI_ACR_STATUS_0 0x1c3d +#define SEA_mmDIG0_HDMI_ACR_STATUS_0 0x1c3d +#define SEA_mmDIG1_HDMI_ACR_STATUS_0 0x1f3d +#define SEA_mmDIG2_HDMI_ACR_STATUS_0 0x423d +#define SEA_mmDIG3_HDMI_ACR_STATUS_0 0x453d +#define SEA_mmDIG4_HDMI_ACR_STATUS_0 0x483d +#define SEA_mmDIG5_HDMI_ACR_STATUS_0 0x4b3d +#define SEA_mmDIG6_HDMI_ACR_STATUS_0 0x4e3d +#define SEA_mmHDMI_ACR_STATUS_1 0x1c3e +#define SEA_mmDIG0_HDMI_ACR_STATUS_1 0x1c3e +#define SEA_mmDIG1_HDMI_ACR_STATUS_1 0x1f3e +#define SEA_mmDIG2_HDMI_ACR_STATUS_1 0x423e +#define SEA_mmDIG3_HDMI_ACR_STATUS_1 0x453e +#define SEA_mmDIG4_HDMI_ACR_STATUS_1 0x483e +#define SEA_mmDIG5_HDMI_ACR_STATUS_1 0x4b3e +#define SEA_mmDIG6_HDMI_ACR_STATUS_1 0x4e3e +#define SEA_mmAFMT_AUDIO_INFO0 0x1c3f +#define SEA_mmDIG0_AFMT_AUDIO_INFO0 0x1c3f +#define SEA_mmDIG1_AFMT_AUDIO_INFO0 0x1f3f +#define SEA_mmDIG2_AFMT_AUDIO_INFO0 0x423f +#define SEA_mmDIG3_AFMT_AUDIO_INFO0 0x453f +#define SEA_mmDIG4_AFMT_AUDIO_INFO0 0x483f +#define SEA_mmDIG5_AFMT_AUDIO_INFO0 0x4b3f +#define SEA_mmDIG6_AFMT_AUDIO_INFO0 0x4e3f +#define SEA_mmAFMT_AUDIO_INFO1 0x1c40 +#define SEA_mmDIG0_AFMT_AUDIO_INFO1 0x1c40 +#define SEA_mmDIG1_AFMT_AUDIO_INFO1 0x1f40 +#define SEA_mmDIG2_AFMT_AUDIO_INFO1 0x4240 +#define SEA_mmDIG3_AFMT_AUDIO_INFO1 0x4540 +#define SEA_mmDIG4_AFMT_AUDIO_INFO1 0x4840 +#define SEA_mmDIG5_AFMT_AUDIO_INFO1 0x4b40 +#define SEA_mmDIG6_AFMT_AUDIO_INFO1 0x4e40 +#define SEA_mmAFMT_60958_0 0x1c41 +#define SEA_mmDIG0_AFMT_60958_0 0x1c41 +#define SEA_mmDIG1_AFMT_60958_0 0x1f41 +#define SEA_mmDIG2_AFMT_60958_0 0x4241 +#define SEA_mmDIG3_AFMT_60958_0 0x4541 +#define SEA_mmDIG4_AFMT_60958_0 0x4841 +#define SEA_mmDIG5_AFMT_60958_0 0x4b41 +#define SEA_mmDIG6_AFMT_60958_0 0x4e41 +#define SEA_mmAFMT_60958_1 0x1c42 +#define SEA_mmDIG0_AFMT_60958_1 0x1c42 +#define SEA_mmDIG1_AFMT_60958_1 0x1f42 +#define SEA_mmDIG2_AFMT_60958_1 0x4242 +#define SEA_mmDIG3_AFMT_60958_1 0x4542 +#define SEA_mmDIG4_AFMT_60958_1 0x4842 +#define SEA_mmDIG5_AFMT_60958_1 0x4b42 +#define SEA_mmDIG6_AFMT_60958_1 0x4e42 +#define SEA_mmAFMT_AUDIO_CRC_CONTROL 0x1c43 +#define SEA_mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1c43 +#define SEA_mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1f43 +#define SEA_mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 +#define SEA_mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 +#define SEA_mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 +#define SEA_mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4b43 +#define SEA_mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x4e43 +#define SEA_mmAFMT_RAMP_CONTROL0 0x1c44 +#define SEA_mmDIG0_AFMT_RAMP_CONTROL0 0x1c44 +#define SEA_mmDIG1_AFMT_RAMP_CONTROL0 0x1f44 +#define SEA_mmDIG2_AFMT_RAMP_CONTROL0 0x4244 +#define SEA_mmDIG3_AFMT_RAMP_CONTROL0 0x4544 +#define SEA_mmDIG4_AFMT_RAMP_CONTROL0 0x4844 +#define SEA_mmDIG5_AFMT_RAMP_CONTROL0 0x4b44 +#define SEA_mmDIG6_AFMT_RAMP_CONTROL0 0x4e44 +#define SEA_mmAFMT_RAMP_CONTROL1 0x1c45 +#define SEA_mmDIG0_AFMT_RAMP_CONTROL1 0x1c45 +#define SEA_mmDIG1_AFMT_RAMP_CONTROL1 0x1f45 +#define SEA_mmDIG2_AFMT_RAMP_CONTROL1 0x4245 +#define SEA_mmDIG3_AFMT_RAMP_CONTROL1 0x4545 +#define SEA_mmDIG4_AFMT_RAMP_CONTROL1 0x4845 +#define SEA_mmDIG5_AFMT_RAMP_CONTROL1 0x4b45 +#define SEA_mmDIG6_AFMT_RAMP_CONTROL1 0x4e45 +#define SEA_mmAFMT_RAMP_CONTROL2 0x1c46 +#define SEA_mmDIG0_AFMT_RAMP_CONTROL2 0x1c46 +#define SEA_mmDIG1_AFMT_RAMP_CONTROL2 0x1f46 +#define SEA_mmDIG2_AFMT_RAMP_CONTROL2 0x4246 +#define SEA_mmDIG3_AFMT_RAMP_CONTROL2 0x4546 +#define SEA_mmDIG4_AFMT_RAMP_CONTROL2 0x4846 +#define SEA_mmDIG5_AFMT_RAMP_CONTROL2 0x4b46 +#define SEA_mmDIG6_AFMT_RAMP_CONTROL2 0x4e46 +#define SEA_mmAFMT_RAMP_CONTROL3 0x1c47 +#define SEA_mmDIG0_AFMT_RAMP_CONTROL3 0x1c47 +#define SEA_mmDIG1_AFMT_RAMP_CONTROL3 0x1f47 +#define SEA_mmDIG2_AFMT_RAMP_CONTROL3 0x4247 +#define SEA_mmDIG3_AFMT_RAMP_CONTROL3 0x4547 +#define SEA_mmDIG4_AFMT_RAMP_CONTROL3 0x4847 +#define SEA_mmDIG5_AFMT_RAMP_CONTROL3 0x4b47 +#define SEA_mmDIG6_AFMT_RAMP_CONTROL3 0x4e47 +#define SEA_mmAFMT_60958_2 0x1c48 +#define SEA_mmDIG0_AFMT_60958_2 0x1c48 +#define SEA_mmDIG1_AFMT_60958_2 0x1f48 +#define SEA_mmDIG2_AFMT_60958_2 0x4248 +#define SEA_mmDIG3_AFMT_60958_2 0x4548 +#define SEA_mmDIG4_AFMT_60958_2 0x4848 +#define SEA_mmDIG5_AFMT_60958_2 0x4b48 +#define SEA_mmDIG6_AFMT_60958_2 0x4e48 +#define SEA_mmAFMT_AUDIO_CRC_RESULT 0x1c49 +#define SEA_mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1c49 +#define SEA_mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1f49 +#define SEA_mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 +#define SEA_mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 +#define SEA_mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 +#define SEA_mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4b49 +#define SEA_mmDIG6_AFMT_AUDIO_CRC_RESULT 0x4e49 +#define SEA_mmAFMT_STATUS 0x1c4a +#define SEA_mmDIG0_AFMT_STATUS 0x1c4a +#define SEA_mmDIG1_AFMT_STATUS 0x1f4a +#define SEA_mmDIG2_AFMT_STATUS 0x424a +#define SEA_mmDIG3_AFMT_STATUS 0x454a +#define SEA_mmDIG4_AFMT_STATUS 0x484a +#define SEA_mmDIG5_AFMT_STATUS 0x4b4a +#define SEA_mmDIG6_AFMT_STATUS 0x4e4a +#define SEA_mmAFMT_AUDIO_PACKET_CONTROL 0x1c4b +#define SEA_mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1c4b +#define SEA_mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1f4b +#define SEA_mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424b +#define SEA_mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454b +#define SEA_mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484b +#define SEA_mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4b4b +#define SEA_mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x4e4b +#define SEA_mmAFMT_VBI_PACKET_CONTROL 0x1c4c +#define SEA_mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1c4c +#define SEA_mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1f4c +#define SEA_mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424c +#define SEA_mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454c +#define SEA_mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484c +#define SEA_mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4b4c +#define SEA_mmDIG6_AFMT_VBI_PACKET_CONTROL 0x4e4c +#define SEA_mmAFMT_INFOFRAME_CONTROL0 0x1c4d +#define SEA_mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1c4d +#define SEA_mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1f4d +#define SEA_mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424d +#define SEA_mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454d +#define SEA_mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484d +#define SEA_mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4b4d +#define SEA_mmDIG6_AFMT_INFOFRAME_CONTROL0 0x4e4d +#define SEA_mmAFMT_AUDIO_SRC_CONTROL 0x1c4f +#define SEA_mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1c4f +#define SEA_mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1f4f +#define SEA_mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424f +#define SEA_mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454f +#define SEA_mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484f +#define SEA_mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4b4f +#define SEA_mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x4e4f +#define SEA_mmAFMT_AUDIO_DBG_DTO_CNTL 0x1c52 +#define SEA_mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1c52 +#define SEA_mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1f52 +#define SEA_mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 +#define SEA_mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 +#define SEA_mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 +#define SEA_mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4b52 +#define SEA_mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x4e52 +#define SEA_mmDIG_BE_CNTL 0x1c50 +#define SEA_mmDIG0_DIG_BE_CNTL 0x1c50 +#define SEA_mmDIG1_DIG_BE_CNTL 0x1f50 +#define SEA_mmDIG2_DIG_BE_CNTL 0x4250 +#define SEA_mmDIG3_DIG_BE_CNTL 0x4550 +#define SEA_mmDIG4_DIG_BE_CNTL 0x4850 +#define SEA_mmDIG5_DIG_BE_CNTL 0x4b50 +#define SEA_mmDIG6_DIG_BE_CNTL 0x4e50 +#define SEA_mmDIG_BE_EN_CNTL 0x1c51 +#define SEA_mmDIG0_DIG_BE_EN_CNTL 0x1c51 +#define SEA_mmDIG1_DIG_BE_EN_CNTL 0x1f51 +#define SEA_mmDIG2_DIG_BE_EN_CNTL 0x4251 +#define SEA_mmDIG3_DIG_BE_EN_CNTL 0x4551 +#define SEA_mmDIG4_DIG_BE_EN_CNTL 0x4851 +#define SEA_mmDIG5_DIG_BE_EN_CNTL 0x4b51 +#define SEA_mmDIG6_DIG_BE_EN_CNTL 0x4e51 +#define SEA_mmTMDS_CNTL 0x1c7c +#define SEA_mmDIG0_TMDS_CNTL 0x1c7c +#define SEA_mmDIG1_TMDS_CNTL 0x1f7c +#define SEA_mmDIG2_TMDS_CNTL 0x427c +#define SEA_mmDIG3_TMDS_CNTL 0x457c +#define SEA_mmDIG4_TMDS_CNTL 0x487c +#define SEA_mmDIG5_TMDS_CNTL 0x4b7c +#define SEA_mmDIG6_TMDS_CNTL 0x4e7c +#define SEA_mmTMDS_CONTROL_CHAR 0x1c7d +#define SEA_mmDIG0_TMDS_CONTROL_CHAR 0x1c7d +#define SEA_mmDIG1_TMDS_CONTROL_CHAR 0x1f7d +#define SEA_mmDIG2_TMDS_CONTROL_CHAR 0x427d +#define SEA_mmDIG3_TMDS_CONTROL_CHAR 0x457d +#define SEA_mmDIG4_TMDS_CONTROL_CHAR 0x487d +#define SEA_mmDIG5_TMDS_CONTROL_CHAR 0x4b7d +#define SEA_mmDIG6_TMDS_CONTROL_CHAR 0x4e7d +#define SEA_mmTMDS_CONTROL0_FEEDBACK 0x1c7e +#define SEA_mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1c7e +#define SEA_mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1f7e +#define SEA_mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427e +#define SEA_mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457e +#define SEA_mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487e +#define SEA_mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4b7e +#define SEA_mmDIG6_TMDS_CONTROL0_FEEDBACK 0x4e7e +#define SEA_mmTMDS_STEREOSYNC_CTL_SEL 0x1c7f +#define SEA_mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1c7f +#define SEA_mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1f7f +#define SEA_mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427f +#define SEA_mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457f +#define SEA_mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487f +#define SEA_mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4b7f +#define SEA_mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x4e7f +#define SEA_mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 +#define SEA_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 +#define SEA_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1f80 +#define SEA_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 +#define SEA_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 +#define SEA_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 +#define SEA_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b80 +#define SEA_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e80 +#define SEA_mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 +#define SEA_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 +#define SEA_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1f81 +#define SEA_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 +#define SEA_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 +#define SEA_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 +#define SEA_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b81 +#define SEA_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e81 +#define SEA_mmTMDS_DEBUG 0x1c82 +#define SEA_mmDIG0_TMDS_DEBUG 0x1c82 +#define SEA_mmDIG1_TMDS_DEBUG 0x1f82 +#define SEA_mmDIG2_TMDS_DEBUG 0x4282 +#define SEA_mmDIG3_TMDS_DEBUG 0x4582 +#define SEA_mmDIG4_TMDS_DEBUG 0x4882 +#define SEA_mmDIG5_TMDS_DEBUG 0x4b82 +#define SEA_mmDIG6_TMDS_DEBUG 0x4e82 +#define SEA_mmTMDS_CTL_BITS 0x1c83 +#define SEA_mmDIG0_TMDS_CTL_BITS 0x1c83 +#define SEA_mmDIG1_TMDS_CTL_BITS 0x1f83 +#define SEA_mmDIG2_TMDS_CTL_BITS 0x4283 +#define SEA_mmDIG3_TMDS_CTL_BITS 0x4583 +#define SEA_mmDIG4_TMDS_CTL_BITS 0x4883 +#define SEA_mmDIG5_TMDS_CTL_BITS 0x4b83 +#define SEA_mmDIG6_TMDS_CTL_BITS 0x4e83 +#define SEA_mmTMDS_DCBALANCER_CONTROL 0x1c84 +#define SEA_mmDIG0_TMDS_DCBALANCER_CONTROL 0x1c84 +#define SEA_mmDIG1_TMDS_DCBALANCER_CONTROL 0x1f84 +#define SEA_mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 +#define SEA_mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 +#define SEA_mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 +#define SEA_mmDIG5_TMDS_DCBALANCER_CONTROL 0x4b84 +#define SEA_mmDIG6_TMDS_DCBALANCER_CONTROL 0x4e84 +#define SEA_mmTMDS_CTL0_1_GEN_CNTL 0x1c86 +#define SEA_mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1c86 +#define SEA_mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1f86 +#define SEA_mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 +#define SEA_mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 +#define SEA_mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 +#define SEA_mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4b86 +#define SEA_mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x4e86 +#define SEA_mmTMDS_CTL2_3_GEN_CNTL 0x1c87 +#define SEA_mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1c87 +#define SEA_mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1f87 +#define SEA_mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 +#define SEA_mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 +#define SEA_mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 +#define SEA_mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4b87 +#define SEA_mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x4e87 +#define SEA_mmLVDS_DATA_CNTL 0x1c8c +#define SEA_mmDIG0_LVDS_DATA_CNTL 0x1c8c +#define SEA_mmDIG1_LVDS_DATA_CNTL 0x1f8c +#define SEA_mmDIG2_LVDS_DATA_CNTL 0x428c +#define SEA_mmDIG3_LVDS_DATA_CNTL 0x458c +#define SEA_mmDIG4_LVDS_DATA_CNTL 0x488c +#define SEA_mmDIG5_LVDS_DATA_CNTL 0x4b8c +#define SEA_mmDIG6_LVDS_DATA_CNTL 0x4e8c +#define SEA_mmDIG_LANE_ENABLE 0x1c8d +#define SEA_mmDIG0_DIG_LANE_ENABLE 0x1c8d +#define SEA_mmDIG1_DIG_LANE_ENABLE 0x1f8d +#define SEA_mmDIG2_DIG_LANE_ENABLE 0x428d +#define SEA_mmDIG3_DIG_LANE_ENABLE 0x458d +#define SEA_mmDIG4_DIG_LANE_ENABLE 0x488d +#define SEA_mmDIG5_DIG_LANE_ENABLE 0x4b8d +#define SEA_mmDIG6_DIG_LANE_ENABLE 0x4e8d +#define SEA_mmDOUT_SCRATCH0 0x1844 +#define SEA_mmDOUT_SCRATCH1 0x1845 +#define SEA_mmDOUT_SCRATCH2 0x1846 +#define SEA_mmDOUT_SCRATCH3 0x1847 +#define SEA_mmDOUT_SCRATCH4 0x1848 +#define SEA_mmDOUT_SCRATCH5 0x1849 +#define SEA_mmDOUT_SCRATCH6 0x184a +#define SEA_mmDOUT_SCRATCH7 0x184b +#define SEA_mmDOUT_DCE_VCE_CONTROL 0x18ff +#define SEA_mmDC_HPD1_INT_STATUS 0x1807 +#define SEA_mmDC_HPD1_INT_CONTROL 0x1808 +#define SEA_mmDC_HPD1_CONTROL 0x1809 +#define SEA_mmDC_HPD2_INT_STATUS 0x180a +#define SEA_mmDC_HPD2_INT_CONTROL 0x180b +#define SEA_mmDC_HPD2_CONTROL 0x180c +#define SEA_mmDC_HPD3_INT_STATUS 0x180d +#define SEA_mmDC_HPD3_INT_CONTROL 0x180e +#define SEA_mmDC_HPD3_CONTROL 0x180f +#define SEA_mmDC_HPD4_INT_STATUS 0x1810 +#define SEA_mmDC_HPD4_INT_CONTROL 0x1811 +#define SEA_mmDC_HPD4_CONTROL 0x1812 +#define SEA_mmDC_HPD5_INT_STATUS 0x1813 +#define SEA_mmDC_HPD5_INT_CONTROL 0x1814 +#define SEA_mmDC_HPD5_CONTROL 0x1815 +#define SEA_mmDC_HPD6_INT_STATUS 0x1816 +#define SEA_mmDC_HPD6_INT_CONTROL 0x1817 +#define SEA_mmDC_HPD6_CONTROL 0x1818 +#define SEA_mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 +#define SEA_mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 +#define SEA_mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 +#define SEA_mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 +#define SEA_mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 +#define SEA_mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 +#define SEA_mmDC_HPD1_TOGGLE_FILT_CNTL 0x18bc +#define SEA_mmDC_HPD2_TOGGLE_FILT_CNTL 0x18bd +#define SEA_mmDC_HPD3_TOGGLE_FILT_CNTL 0x18be +#define SEA_mmDC_HPD4_TOGGLE_FILT_CNTL 0x18fc +#define SEA_mmDC_HPD5_TOGGLE_FILT_CNTL 0x18fd +#define SEA_mmDC_HPD6_TOGGLE_FILT_CNTL 0x18fe +#define SEA_mmDC_I2C_CONTROL 0x1819 +#define SEA_mmDC_I2C_ARBITRATION 0x181a +#define SEA_mmDC_I2C_INTERRUPT_CONTROL 0x181b +#define SEA_mmDC_I2C_SW_STATUS 0x181c +#define SEA_mmDC_I2C_DDC1_HW_STATUS 0x181d +#define SEA_mmDC_I2C_DDC2_HW_STATUS 0x181e +#define SEA_mmDC_I2C_DDC3_HW_STATUS 0x181f +#define SEA_mmDC_I2C_DDC4_HW_STATUS 0x1820 +#define SEA_mmDC_I2C_DDC5_HW_STATUS 0x1821 +#define SEA_mmDC_I2C_DDC6_HW_STATUS 0x1822 +#define SEA_mmDC_I2C_DDC1_SPEED 0x1823 +#define SEA_mmDC_I2C_DDC1_SETUP 0x1824 +#define SEA_mmDC_I2C_DDC2_SPEED 0x1825 +#define SEA_mmDC_I2C_DDC2_SETUP 0x1826 +#define SEA_mmDC_I2C_DDC3_SPEED 0x1827 +#define SEA_mmDC_I2C_DDC3_SETUP 0x1828 +#define SEA_mmDC_I2C_DDC4_SPEED 0x1829 +#define SEA_mmDC_I2C_DDC4_SETUP 0x182a +#define SEA_mmDC_I2C_DDC5_SPEED 0x182b +#define SEA_mmDC_I2C_DDC5_SETUP 0x182c +#define SEA_mmDC_I2C_DDC6_SPEED 0x182d +#define SEA_mmDC_I2C_DDC6_SETUP 0x182e +#define SEA_mmDC_I2C_TRANSACTION0 0x182f +#define SEA_mmDC_I2C_TRANSACTION1 0x1830 +#define SEA_mmDC_I2C_TRANSACTION2 0x1831 +#define SEA_mmDC_I2C_TRANSACTION3 0x1832 +#define SEA_mmDC_I2C_DATA 0x1833 +#define SEA_mmGENERIC_I2C_CONTROL 0x1834 +#define SEA_mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 +#define SEA_mmGENERIC_I2C_STATUS 0x1836 +#define SEA_mmGENERIC_I2C_SPEED 0x1837 +#define SEA_mmGENERIC_I2C_SETUP 0x1838 +#define SEA_mmGENERIC_I2C_TRANSACTION 0x1839 +#define SEA_mmGENERIC_I2C_DATA 0x183a +#define SEA_mmGENERIC_I2C_PIN_SELECTION 0x183b +#define SEA_mmGENERIC_I2C_PIN_DEBUG 0x183c +#define SEA_mmDISP_INTERRUPT_STATUS 0x183d +#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE 0x183e +#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183f +#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 +#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 +#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 +#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE6 0x19e0 +#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE7 0x19e1 +#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE8 0x19e2 +#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE9 0x19e3 +#define SEA_mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 +#define SEA_mmDISP_TIMER_CONTROL 0x1842 +#define SEA_mmDC_I2C_DDCVGA_HW_STATUS 0x1855 +#define SEA_mmDC_I2C_DDCVGA_SPEED 0x1856 +#define SEA_mmDC_I2C_DDCVGA_SETUP 0x1857 +#define SEA_mmDC_I2C_EDID_DETECT_CTRL 0x186f +#define SEA_mmDISPOUT_STEREOSYNC_SEL 0x18bf +#define SEA_mmDOUT_TEST_DEBUG_INDEX 0x184d +#define SEA_mmDOUT_TEST_DEBUG_DATA 0x184e +#define SEA_ixDP_AUX1_DEBUG_A 0x10 +#define SEA_ixDP_AUX1_DEBUG_B 0x11 +#define SEA_ixDP_AUX1_DEBUG_C 0x12 +#define SEA_ixDP_AUX1_DEBUG_D 0x13 +#define SEA_ixDP_AUX1_DEBUG_E 0x14 +#define SEA_ixDP_AUX1_DEBUG_F 0x15 +#define SEA_ixDP_AUX1_DEBUG_G 0x16 +#define SEA_ixDP_AUX1_DEBUG_H 0x17 +#define SEA_ixDP_AUX1_DEBUG_I 0x18 +#define SEA_ixDP_AUX1_DEBUG_J 0x19 +#define SEA_ixDP_AUX1_DEBUG_K 0x1a +#define SEA_ixDP_AUX1_DEBUG_L 0x1b +#define SEA_ixDP_AUX1_DEBUG_M 0x1c +#define SEA_ixDP_AUX1_DEBUG_N 0x1d +#define SEA_ixDP_AUX1_DEBUG_O 0x1e +#define SEA_ixDP_AUX1_DEBUG_P 0x1f +#define SEA_ixDP_AUX1_DEBUG_Q 0x90 +#define SEA_ixDP_AUX2_DEBUG_A 0x20 +#define SEA_ixDP_AUX2_DEBUG_B 0x21 +#define SEA_ixDP_AUX2_DEBUG_C 0x22 +#define SEA_ixDP_AUX2_DEBUG_D 0x23 +#define SEA_ixDP_AUX2_DEBUG_E 0x24 +#define SEA_ixDP_AUX2_DEBUG_F 0x25 +#define SEA_ixDP_AUX2_DEBUG_G 0x26 +#define SEA_ixDP_AUX2_DEBUG_H 0x27 +#define SEA_ixDP_AUX2_DEBUG_I 0x28 +#define SEA_ixDP_AUX2_DEBUG_J 0x29 +#define SEA_ixDP_AUX2_DEBUG_K 0x2a +#define SEA_ixDP_AUX2_DEBUG_L 0x2b +#define SEA_ixDP_AUX2_DEBUG_M 0x2c +#define SEA_ixDP_AUX2_DEBUG_N 0x2d +#define SEA_ixDP_AUX2_DEBUG_O 0x2e +#define SEA_ixDP_AUX2_DEBUG_P 0x2f +#define SEA_ixDP_AUX2_DEBUG_Q 0x91 +#define SEA_ixDP_AUX3_DEBUG_A 0x30 +#define SEA_ixDP_AUX3_DEBUG_B 0x31 +#define SEA_ixDP_AUX3_DEBUG_C 0x32 +#define SEA_ixDP_AUX3_DEBUG_D 0x33 +#define SEA_ixDP_AUX3_DEBUG_E 0x34 +#define SEA_ixDP_AUX3_DEBUG_F 0x35 +#define SEA_ixDP_AUX3_DEBUG_G 0x36 +#define SEA_ixDP_AUX3_DEBUG_H 0x37 +#define SEA_ixDP_AUX3_DEBUG_I 0x38 +#define SEA_ixDP_AUX3_DEBUG_J 0x39 +#define SEA_ixDP_AUX3_DEBUG_K 0x3a +#define SEA_ixDP_AUX3_DEBUG_L 0x3b +#define SEA_ixDP_AUX3_DEBUG_M 0x3c +#define SEA_ixDP_AUX3_DEBUG_N 0x3d +#define SEA_ixDP_AUX3_DEBUG_O 0x3e +#define SEA_ixDP_AUX3_DEBUG_P 0x3f +#define SEA_ixDP_AUX3_DEBUG_Q 0x92 +#define SEA_ixDP_AUX4_DEBUG_A 0x40 +#define SEA_ixDP_AUX4_DEBUG_B 0x41 +#define SEA_ixDP_AUX4_DEBUG_C 0x42 +#define SEA_ixDP_AUX4_DEBUG_D 0x43 +#define SEA_ixDP_AUX4_DEBUG_E 0x44 +#define SEA_ixDP_AUX4_DEBUG_F 0x45 +#define SEA_ixDP_AUX4_DEBUG_G 0x46 +#define SEA_ixDP_AUX4_DEBUG_H 0x47 +#define SEA_ixDP_AUX4_DEBUG_I 0x48 +#define SEA_ixDP_AUX4_DEBUG_J 0x49 +#define SEA_ixDP_AUX4_DEBUG_K 0x4a +#define SEA_ixDP_AUX4_DEBUG_L 0x4b +#define SEA_ixDP_AUX4_DEBUG_M 0x4c +#define SEA_ixDP_AUX4_DEBUG_N 0x4d +#define SEA_ixDP_AUX4_DEBUG_O 0x4e +#define SEA_ixDP_AUX4_DEBUG_P 0x4f +#define SEA_ixDP_AUX4_DEBUG_Q 0x93 +#define SEA_ixDP_AUX5_DEBUG_A 0x70 +#define SEA_ixDP_AUX5_DEBUG_B 0x71 +#define SEA_ixDP_AUX5_DEBUG_C 0x72 +#define SEA_ixDP_AUX5_DEBUG_D 0x73 +#define SEA_ixDP_AUX5_DEBUG_E 0x74 +#define SEA_ixDP_AUX5_DEBUG_F 0x75 +#define SEA_ixDP_AUX5_DEBUG_G 0x76 +#define SEA_ixDP_AUX5_DEBUG_H 0x77 +#define SEA_ixDP_AUX5_DEBUG_I 0x78 +#define SEA_ixDP_AUX5_DEBUG_J 0x79 +#define SEA_ixDP_AUX5_DEBUG_K 0x7a +#define SEA_ixDP_AUX5_DEBUG_L 0x7b +#define SEA_ixDP_AUX5_DEBUG_M 0x7c +#define SEA_ixDP_AUX5_DEBUG_N 0x7d +#define SEA_ixDP_AUX5_DEBUG_O 0x7f +#define SEA_ixDP_AUX5_DEBUG_P 0x94 +#define SEA_ixDP_AUX5_DEBUG_Q 0x95 +#define SEA_ixDP_AUX6_DEBUG_A 0x80 +#define SEA_ixDP_AUX6_DEBUG_B 0x81 +#define SEA_ixDP_AUX6_DEBUG_C 0x82 +#define SEA_ixDP_AUX6_DEBUG_D 0x83 +#define SEA_ixDP_AUX6_DEBUG_E 0x84 +#define SEA_ixDP_AUX6_DEBUG_F 0x85 +#define SEA_ixDP_AUX6_DEBUG_G 0x86 +#define SEA_ixDP_AUX6_DEBUG_H 0x87 +#define SEA_ixDP_AUX6_DEBUG_I 0x88 +#define SEA_ixDP_AUX6_DEBUG_J 0x89 +#define SEA_ixDP_AUX6_DEBUG_K 0x8a +#define SEA_ixDP_AUX6_DEBUG_L 0x8b +#define SEA_ixDP_AUX6_DEBUG_M 0x8c +#define SEA_ixDP_AUX6_DEBUG_N 0x8d +#define SEA_ixDP_AUX6_DEBUG_O 0x8f +#define SEA_ixDP_AUX6_DEBUG_P 0x96 +#define SEA_ixDP_AUX6_DEBUG_Q 0x97 +#define SEA_mmDMCU_CTRL 0x1600 +#define SEA_mmDMCU_STATUS 0x1601 +#define SEA_mmDMCU_PC_START_ADDR 0x1602 +#define SEA_mmDMCU_FW_START_ADDR 0x1603 +#define SEA_mmDMCU_FW_END_ADDR 0x1604 +#define SEA_mmDMCU_FW_ISR_START_ADDR 0x1605 +#define SEA_mmDMCU_FW_CS_HI 0x1606 +#define SEA_mmDMCU_FW_CS_LO 0x1607 +#define SEA_mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define SEA_mmDMCU_ERAM_WR_CTRL 0x1609 +#define SEA_mmDMCU_ERAM_WR_DATA 0x160a +#define SEA_mmDMCU_ERAM_RD_CTRL 0x160b +#define SEA_mmDMCU_ERAM_RD_DATA 0x160c +#define SEA_mmDMCU_IRAM_WR_CTRL 0x160d +#define SEA_mmDMCU_IRAM_WR_DATA 0x160e +#define SEA_mmDMCU_IRAM_RD_CTRL 0x160f +#define SEA_mmDMCU_IRAM_RD_DATA 0x1610 +#define SEA_mmDMCU_EVENT_TRIGGER 0x1611 +#define SEA_mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define SEA_mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 +#define SEA_mmDMCU_INTERRUPT_STATUS 0x1614 +#define SEA_mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define SEA_mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define SEA_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define SEA_mmDC_DMCU_SCRATCH 0x1618 +#define SEA_mmDMCU_INT_CNT 0x1619 +#define SEA_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a +#define SEA_mmDMCU_UC_CLK_GATING_CNTL 0x161b +#define SEA_mmMASTER_COMM_DATA_REG1 0x161c +#define SEA_mmMASTER_COMM_DATA_REG2 0x161d +#define SEA_mmMASTER_COMM_DATA_REG3 0x161e +#define SEA_mmMASTER_COMM_CMD_REG 0x161f +#define SEA_mmMASTER_COMM_CNTL_REG 0x1620 +#define SEA_mmSLAVE_COMM_DATA_REG1 0x1621 +#define SEA_mmSLAVE_COMM_DATA_REG2 0x1622 +#define SEA_mmSLAVE_COMM_DATA_REG3 0x1623 +#define SEA_mmSLAVE_COMM_CMD_REG 0x1624 +#define SEA_mmSLAVE_COMM_CNTL_REG 0x1625 +#define SEA_mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define SEA_mmDMCU_TEST_DEBUG_DATA 0x1627 +#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1750 +#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1751 +#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1752 +#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1753 +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1754 +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1755 +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1756 +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1757 +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1758 +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1759 +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x175a +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x175b +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x175c +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x175d +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x175e +#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x175f +#define SEA_mmDP_LINK_CNTL 0x1cc0 +#define SEA_mmDP0_DP_LINK_CNTL 0x1cc0 +#define SEA_mmDP1_DP_LINK_CNTL 0x1fc0 +#define SEA_mmDP2_DP_LINK_CNTL 0x42c0 +#define SEA_mmDP3_DP_LINK_CNTL 0x45c0 +#define SEA_mmDP4_DP_LINK_CNTL 0x48c0 +#define SEA_mmDP5_DP_LINK_CNTL 0x4bc0 +#define SEA_mmDP6_DP_LINK_CNTL 0x4ec0 +#define SEA_mmDP_PIXEL_FORMAT 0x1cc1 +#define SEA_mmDP0_DP_PIXEL_FORMAT 0x1cc1 +#define SEA_mmDP1_DP_PIXEL_FORMAT 0x1fc1 +#define SEA_mmDP2_DP_PIXEL_FORMAT 0x42c1 +#define SEA_mmDP3_DP_PIXEL_FORMAT 0x45c1 +#define SEA_mmDP4_DP_PIXEL_FORMAT 0x48c1 +#define SEA_mmDP5_DP_PIXEL_FORMAT 0x4bc1 +#define SEA_mmDP6_DP_PIXEL_FORMAT 0x4ec1 +#define SEA_mmDP_MSA_COLORIMETRY 0x1cda +#define SEA_mmDP0_DP_MSA_COLORIMETRY 0x1cda +#define SEA_mmDP1_DP_MSA_COLORIMETRY 0x1fda +#define SEA_mmDP2_DP_MSA_COLORIMETRY 0x42da +#define SEA_mmDP3_DP_MSA_COLORIMETRY 0x45da +#define SEA_mmDP4_DP_MSA_COLORIMETRY 0x48da +#define SEA_mmDP5_DP_MSA_COLORIMETRY 0x4bda +#define SEA_mmDP6_DP_MSA_COLORIMETRY 0x4eda +#define SEA_mmDP_CONFIG 0x1cc2 +#define SEA_mmDP0_DP_CONFIG 0x1cc2 +#define SEA_mmDP1_DP_CONFIG 0x1fc2 +#define SEA_mmDP2_DP_CONFIG 0x42c2 +#define SEA_mmDP3_DP_CONFIG 0x45c2 +#define SEA_mmDP4_DP_CONFIG 0x48c2 +#define SEA_mmDP5_DP_CONFIG 0x4bc2 +#define SEA_mmDP6_DP_CONFIG 0x4ec2 +#define SEA_mmDP_VID_STREAM_CNTL 0x1cc3 +#define SEA_mmDP0_DP_VID_STREAM_CNTL 0x1cc3 +#define SEA_mmDP1_DP_VID_STREAM_CNTL 0x1fc3 +#define SEA_mmDP2_DP_VID_STREAM_CNTL 0x42c3 +#define SEA_mmDP3_DP_VID_STREAM_CNTL 0x45c3 +#define SEA_mmDP4_DP_VID_STREAM_CNTL 0x48c3 +#define SEA_mmDP5_DP_VID_STREAM_CNTL 0x4bc3 +#define SEA_mmDP6_DP_VID_STREAM_CNTL 0x4ec3 +#define SEA_mmDP_STEER_FIFO 0x1cc4 +#define SEA_mmDP0_DP_STEER_FIFO 0x1cc4 +#define SEA_mmDP1_DP_STEER_FIFO 0x1fc4 +#define SEA_mmDP2_DP_STEER_FIFO 0x42c4 +#define SEA_mmDP3_DP_STEER_FIFO 0x45c4 +#define SEA_mmDP4_DP_STEER_FIFO 0x48c4 +#define SEA_mmDP5_DP_STEER_FIFO 0x4bc4 +#define SEA_mmDP6_DP_STEER_FIFO 0x4ec4 +#define SEA_mmDP_MSA_MISC 0x1cc5 +#define SEA_mmDP0_DP_MSA_MISC 0x1cc5 +#define SEA_mmDP1_DP_MSA_MISC 0x1fc5 +#define SEA_mmDP2_DP_MSA_MISC 0x42c5 +#define SEA_mmDP3_DP_MSA_MISC 0x45c5 +#define SEA_mmDP4_DP_MSA_MISC 0x48c5 +#define SEA_mmDP5_DP_MSA_MISC 0x4bc5 +#define SEA_mmDP6_DP_MSA_MISC 0x4ec5 +#define SEA_mmDP_VID_TIMING 0x1cc9 +#define SEA_mmDP0_DP_VID_TIMING 0x1cc9 +#define SEA_mmDP1_DP_VID_TIMING 0x1fc9 +#define SEA_mmDP2_DP_VID_TIMING 0x42c9 +#define SEA_mmDP3_DP_VID_TIMING 0x45c9 +#define SEA_mmDP4_DP_VID_TIMING 0x48c9 +#define SEA_mmDP5_DP_VID_TIMING 0x4bc9 +#define SEA_mmDP6_DP_VID_TIMING 0x4ec9 +#define SEA_mmDP_VID_N 0x1cca +#define SEA_mmDP0_DP_VID_N 0x1cca +#define SEA_mmDP1_DP_VID_N 0x1fca +#define SEA_mmDP2_DP_VID_N 0x42ca +#define SEA_mmDP3_DP_VID_N 0x45ca +#define SEA_mmDP4_DP_VID_N 0x48ca +#define SEA_mmDP5_DP_VID_N 0x4bca +#define SEA_mmDP6_DP_VID_N 0x4eca +#define SEA_mmDP_VID_M 0x1ccb +#define SEA_mmDP0_DP_VID_M 0x1ccb +#define SEA_mmDP1_DP_VID_M 0x1fcb +#define SEA_mmDP2_DP_VID_M 0x42cb +#define SEA_mmDP3_DP_VID_M 0x45cb +#define SEA_mmDP4_DP_VID_M 0x48cb +#define SEA_mmDP5_DP_VID_M 0x4bcb +#define SEA_mmDP6_DP_VID_M 0x4ecb +#define SEA_mmDP_LINK_FRAMING_CNTL 0x1ccc +#define SEA_mmDP0_DP_LINK_FRAMING_CNTL 0x1ccc +#define SEA_mmDP1_DP_LINK_FRAMING_CNTL 0x1fcc +#define SEA_mmDP2_DP_LINK_FRAMING_CNTL 0x42cc +#define SEA_mmDP3_DP_LINK_FRAMING_CNTL 0x45cc +#define SEA_mmDP4_DP_LINK_FRAMING_CNTL 0x48cc +#define SEA_mmDP5_DP_LINK_FRAMING_CNTL 0x4bcc +#define SEA_mmDP6_DP_LINK_FRAMING_CNTL 0x4ecc +#define SEA_mmDP_HBR2_EYE_PATTERN 0x1cc8 +#define SEA_mmDP0_DP_HBR2_EYE_PATTERN 0x1cc8 +#define SEA_mmDP1_DP_HBR2_EYE_PATTERN 0x1fc8 +#define SEA_mmDP2_DP_HBR2_EYE_PATTERN 0x42c8 +#define SEA_mmDP3_DP_HBR2_EYE_PATTERN 0x45c8 +#define SEA_mmDP4_DP_HBR2_EYE_PATTERN 0x48c8 +#define SEA_mmDP5_DP_HBR2_EYE_PATTERN 0x4bc8 +#define SEA_mmDP6_DP_HBR2_EYE_PATTERN 0x4ec8 +#define SEA_mmDP_VID_MSA_VBID 0x1ccd +#define SEA_mmDP0_DP_VID_MSA_VBID 0x1ccd +#define SEA_mmDP1_DP_VID_MSA_VBID 0x1fcd +#define SEA_mmDP2_DP_VID_MSA_VBID 0x42cd +#define SEA_mmDP3_DP_VID_MSA_VBID 0x45cd +#define SEA_mmDP4_DP_VID_MSA_VBID 0x48cd +#define SEA_mmDP5_DP_VID_MSA_VBID 0x4bcd +#define SEA_mmDP6_DP_VID_MSA_VBID 0x4ecd +#define SEA_mmDP_VID_INTERRUPT_CNTL 0x1ccf +#define SEA_mmDP0_DP_VID_INTERRUPT_CNTL 0x1ccf +#define SEA_mmDP1_DP_VID_INTERRUPT_CNTL 0x1fcf +#define SEA_mmDP2_DP_VID_INTERRUPT_CNTL 0x42cf +#define SEA_mmDP3_DP_VID_INTERRUPT_CNTL 0x45cf +#define SEA_mmDP4_DP_VID_INTERRUPT_CNTL 0x48cf +#define SEA_mmDP5_DP_VID_INTERRUPT_CNTL 0x4bcf +#define SEA_mmDP6_DP_VID_INTERRUPT_CNTL 0x4ecf +#define SEA_mmDP_DPHY_CNTL 0x1cd0 +#define SEA_mmDP0_DP_DPHY_CNTL 0x1cd0 +#define SEA_mmDP1_DP_DPHY_CNTL 0x1fd0 +#define SEA_mmDP2_DP_DPHY_CNTL 0x42d0 +#define SEA_mmDP3_DP_DPHY_CNTL 0x45d0 +#define SEA_mmDP4_DP_DPHY_CNTL 0x48d0 +#define SEA_mmDP5_DP_DPHY_CNTL 0x4bd0 +#define SEA_mmDP6_DP_DPHY_CNTL 0x4ed0 +#define SEA_mmDP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 +#define SEA_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 +#define SEA_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1fd1 +#define SEA_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42d1 +#define SEA_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45d1 +#define SEA_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48d1 +#define SEA_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4bd1 +#define SEA_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x4ed1 +#define SEA_mmDP_DPHY_SYM0 0x1cd2 +#define SEA_mmDP0_DP_DPHY_SYM0 0x1cd2 +#define SEA_mmDP1_DP_DPHY_SYM0 0x1fd2 +#define SEA_mmDP2_DP_DPHY_SYM0 0x42d2 +#define SEA_mmDP3_DP_DPHY_SYM0 0x45d2 +#define SEA_mmDP4_DP_DPHY_SYM0 0x48d2 +#define SEA_mmDP5_DP_DPHY_SYM0 0x4bd2 +#define SEA_mmDP6_DP_DPHY_SYM0 0x4ed2 +#define SEA_mmDP_DPHY_SYM1 0x1ce0 +#define SEA_mmDP0_DP_DPHY_SYM1 0x1ce0 +#define SEA_mmDP1_DP_DPHY_SYM1 0x1fe0 +#define SEA_mmDP2_DP_DPHY_SYM1 0x42e0 +#define SEA_mmDP3_DP_DPHY_SYM1 0x45e0 +#define SEA_mmDP4_DP_DPHY_SYM1 0x48e0 +#define SEA_mmDP5_DP_DPHY_SYM1 0x4be0 +#define SEA_mmDP6_DP_DPHY_SYM1 0x4ee0 +#define SEA_mmDP_DPHY_SYM2 0x1cdf +#define SEA_mmDP0_DP_DPHY_SYM2 0x1cdf +#define SEA_mmDP1_DP_DPHY_SYM2 0x1fdf +#define SEA_mmDP2_DP_DPHY_SYM2 0x42df +#define SEA_mmDP3_DP_DPHY_SYM2 0x45df +#define SEA_mmDP4_DP_DPHY_SYM2 0x48df +#define SEA_mmDP5_DP_DPHY_SYM2 0x4bdf +#define SEA_mmDP6_DP_DPHY_SYM2 0x4edf +#define SEA_mmDP_DPHY_8B10B_CNTL 0x1cd3 +#define SEA_mmDP0_DP_DPHY_8B10B_CNTL 0x1cd3 +#define SEA_mmDP1_DP_DPHY_8B10B_CNTL 0x1fd3 +#define SEA_mmDP2_DP_DPHY_8B10B_CNTL 0x42d3 +#define SEA_mmDP3_DP_DPHY_8B10B_CNTL 0x45d3 +#define SEA_mmDP4_DP_DPHY_8B10B_CNTL 0x48d3 +#define SEA_mmDP5_DP_DPHY_8B10B_CNTL 0x4bd3 +#define SEA_mmDP6_DP_DPHY_8B10B_CNTL 0x4ed3 +#define SEA_mmDP_DPHY_PRBS_CNTL 0x1cd4 +#define SEA_mmDP0_DP_DPHY_PRBS_CNTL 0x1cd4 +#define SEA_mmDP1_DP_DPHY_PRBS_CNTL 0x1fd4 +#define SEA_mmDP2_DP_DPHY_PRBS_CNTL 0x42d4 +#define SEA_mmDP3_DP_DPHY_PRBS_CNTL 0x45d4 +#define SEA_mmDP4_DP_DPHY_PRBS_CNTL 0x48d4 +#define SEA_mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4 +#define SEA_mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4 +#define SEA_mmDP_DPHY_CRC_EN 0x1cd6 +#define SEA_mmDP0_DP_DPHY_CRC_EN 0x1cd6 +#define SEA_mmDP1_DP_DPHY_CRC_EN 0x1fd6 +#define SEA_mmDP2_DP_DPHY_CRC_EN 0x42d6 +#define SEA_mmDP3_DP_DPHY_CRC_EN 0x45d6 +#define SEA_mmDP4_DP_DPHY_CRC_EN 0x48d6 +#define SEA_mmDP5_DP_DPHY_CRC_EN 0x4bd6 +#define SEA_mmDP6_DP_DPHY_CRC_EN 0x4ed6 +#define SEA_mmDP_DPHY_CRC_CNTL 0x1cd7 +#define SEA_mmDP0_DP_DPHY_CRC_CNTL 0x1cd7 +#define SEA_mmDP1_DP_DPHY_CRC_CNTL 0x1fd7 +#define SEA_mmDP2_DP_DPHY_CRC_CNTL 0x42d7 +#define SEA_mmDP3_DP_DPHY_CRC_CNTL 0x45d7 +#define SEA_mmDP4_DP_DPHY_CRC_CNTL 0x48d7 +#define SEA_mmDP5_DP_DPHY_CRC_CNTL 0x4bd7 +#define SEA_mmDP6_DP_DPHY_CRC_CNTL 0x4ed7 +#define SEA_mmDP_DPHY_CRC_RESULT 0x1cd8 +#define SEA_mmDP0_DP_DPHY_CRC_RESULT 0x1cd8 +#define SEA_mmDP1_DP_DPHY_CRC_RESULT 0x1fd8 +#define SEA_mmDP2_DP_DPHY_CRC_RESULT 0x42d8 +#define SEA_mmDP3_DP_DPHY_CRC_RESULT 0x45d8 +#define SEA_mmDP4_DP_DPHY_CRC_RESULT 0x48d8 +#define SEA_mmDP5_DP_DPHY_CRC_RESULT 0x4bd8 +#define SEA_mmDP6_DP_DPHY_CRC_RESULT 0x4ed8 +#define SEA_mmDP_DPHY_CRC_MST_CNTL 0x1cc6 +#define SEA_mmDP0_DP_DPHY_CRC_MST_CNTL 0x1cc6 +#define SEA_mmDP1_DP_DPHY_CRC_MST_CNTL 0x1fc6 +#define SEA_mmDP2_DP_DPHY_CRC_MST_CNTL 0x42c6 +#define SEA_mmDP3_DP_DPHY_CRC_MST_CNTL 0x45c6 +#define SEA_mmDP4_DP_DPHY_CRC_MST_CNTL 0x48c6 +#define SEA_mmDP5_DP_DPHY_CRC_MST_CNTL 0x4bc6 +#define SEA_mmDP6_DP_DPHY_CRC_MST_CNTL 0x4ec6 +#define SEA_mmDP_DPHY_CRC_MST_STATUS 0x1cc7 +#define SEA_mmDP0_DP_DPHY_CRC_MST_STATUS 0x1cc7 +#define SEA_mmDP1_DP_DPHY_CRC_MST_STATUS 0x1fc7 +#define SEA_mmDP2_DP_DPHY_CRC_MST_STATUS 0x42c7 +#define SEA_mmDP3_DP_DPHY_CRC_MST_STATUS 0x45c7 +#define SEA_mmDP4_DP_DPHY_CRC_MST_STATUS 0x48c7 +#define SEA_mmDP5_DP_DPHY_CRC_MST_STATUS 0x4bc7 +#define SEA_mmDP6_DP_DPHY_CRC_MST_STATUS 0x4ec7 +#define SEA_mmDP_DPHY_FAST_TRAINING 0x1cce +#define SEA_mmDP0_DP_DPHY_FAST_TRAINING 0x1cce +#define SEA_mmDP1_DP_DPHY_FAST_TRAINING 0x1fce +#define SEA_mmDP2_DP_DPHY_FAST_TRAINING 0x42ce +#define SEA_mmDP3_DP_DPHY_FAST_TRAINING 0x45ce +#define SEA_mmDP4_DP_DPHY_FAST_TRAINING 0x48ce +#define SEA_mmDP5_DP_DPHY_FAST_TRAINING 0x4bce +#define SEA_mmDP6_DP_DPHY_FAST_TRAINING 0x4ece +#define SEA_mmDP_DPHY_FAST_TRAINING_STATUS 0x1ce9 +#define SEA_mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1ce9 +#define SEA_mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1fe9 +#define SEA_mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42e9 +#define SEA_mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45e9 +#define SEA_mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48e9 +#define SEA_mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4be9 +#define SEA_mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x4ee9 +#define SEA_mmDP_MSA_V_TIMING_OVERRIDE1 0x1cea +#define SEA_mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1cea +#define SEA_mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1fea +#define SEA_mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42ea +#define SEA_mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45ea +#define SEA_mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48ea +#define SEA_mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4bea +#define SEA_mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x4eea +#define SEA_mmDP_MSA_V_TIMING_OVERRIDE2 0x1ceb +#define SEA_mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1ceb +#define SEA_mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1feb +#define SEA_mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42eb +#define SEA_mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45eb +#define SEA_mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48eb +#define SEA_mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4beb +#define SEA_mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x4eeb +#define SEA_mmDP_SEC_CNTL 0x1ca0 +#define SEA_mmDP0_DP_SEC_CNTL 0x1ca0 +#define SEA_mmDP1_DP_SEC_CNTL 0x1fa0 +#define SEA_mmDP2_DP_SEC_CNTL 0x42a0 +#define SEA_mmDP3_DP_SEC_CNTL 0x45a0 +#define SEA_mmDP4_DP_SEC_CNTL 0x48a0 +#define SEA_mmDP5_DP_SEC_CNTL 0x4ba0 +#define SEA_mmDP6_DP_SEC_CNTL 0x4ea0 +#define SEA_mmDP_SEC_CNTL1 0x1cab +#define SEA_mmDP0_DP_SEC_CNTL1 0x1cab +#define SEA_mmDP1_DP_SEC_CNTL1 0x1fab +#define SEA_mmDP2_DP_SEC_CNTL1 0x42ab +#define SEA_mmDP3_DP_SEC_CNTL1 0x45ab +#define SEA_mmDP4_DP_SEC_CNTL1 0x48ab +#define SEA_mmDP5_DP_SEC_CNTL1 0x4bab +#define SEA_mmDP6_DP_SEC_CNTL1 0x4eab +#define SEA_mmDP_SEC_FRAMING1 0x1ca1 +#define SEA_mmDP0_DP_SEC_FRAMING1 0x1ca1 +#define SEA_mmDP1_DP_SEC_FRAMING1 0x1fa1 +#define SEA_mmDP2_DP_SEC_FRAMING1 0x42a1 +#define SEA_mmDP3_DP_SEC_FRAMING1 0x45a1 +#define SEA_mmDP4_DP_SEC_FRAMING1 0x48a1 +#define SEA_mmDP5_DP_SEC_FRAMING1 0x4ba1 +#define SEA_mmDP6_DP_SEC_FRAMING1 0x4ea1 +#define SEA_mmDP_SEC_FRAMING2 0x1ca2 +#define SEA_mmDP0_DP_SEC_FRAMING2 0x1ca2 +#define SEA_mmDP1_DP_SEC_FRAMING2 0x1fa2 +#define SEA_mmDP2_DP_SEC_FRAMING2 0x42a2 +#define SEA_mmDP3_DP_SEC_FRAMING2 0x45a2 +#define SEA_mmDP4_DP_SEC_FRAMING2 0x48a2 +#define SEA_mmDP5_DP_SEC_FRAMING2 0x4ba2 +#define SEA_mmDP6_DP_SEC_FRAMING2 0x4ea2 +#define SEA_mmDP_SEC_FRAMING3 0x1ca3 +#define SEA_mmDP0_DP_SEC_FRAMING3 0x1ca3 +#define SEA_mmDP1_DP_SEC_FRAMING3 0x1fa3 +#define SEA_mmDP2_DP_SEC_FRAMING3 0x42a3 +#define SEA_mmDP3_DP_SEC_FRAMING3 0x45a3 +#define SEA_mmDP4_DP_SEC_FRAMING3 0x48a3 +#define SEA_mmDP5_DP_SEC_FRAMING3 0x4ba3 +#define SEA_mmDP6_DP_SEC_FRAMING3 0x4ea3 +#define SEA_mmDP_SEC_FRAMING4 0x1ca4 +#define SEA_mmDP0_DP_SEC_FRAMING4 0x1ca4 +#define SEA_mmDP1_DP_SEC_FRAMING4 0x1fa4 +#define SEA_mmDP2_DP_SEC_FRAMING4 0x42a4 +#define SEA_mmDP3_DP_SEC_FRAMING4 0x45a4 +#define SEA_mmDP4_DP_SEC_FRAMING4 0x48a4 +#define SEA_mmDP5_DP_SEC_FRAMING4 0x4ba4 +#define SEA_mmDP6_DP_SEC_FRAMING4 0x4ea4 +#define SEA_mmDP_SEC_AUD_N 0x1ca5 +#define SEA_mmDP0_DP_SEC_AUD_N 0x1ca5 +#define SEA_mmDP1_DP_SEC_AUD_N 0x1fa5 +#define SEA_mmDP2_DP_SEC_AUD_N 0x42a5 +#define SEA_mmDP3_DP_SEC_AUD_N 0x45a5 +#define SEA_mmDP4_DP_SEC_AUD_N 0x48a5 +#define SEA_mmDP5_DP_SEC_AUD_N 0x4ba5 +#define SEA_mmDP6_DP_SEC_AUD_N 0x4ea5 +#define SEA_mmDP_SEC_AUD_N_READBACK 0x1ca6 +#define SEA_mmDP0_DP_SEC_AUD_N_READBACK 0x1ca6 +#define SEA_mmDP1_DP_SEC_AUD_N_READBACK 0x1fa6 +#define SEA_mmDP2_DP_SEC_AUD_N_READBACK 0x42a6 +#define SEA_mmDP3_DP_SEC_AUD_N_READBACK 0x45a6 +#define SEA_mmDP4_DP_SEC_AUD_N_READBACK 0x48a6 +#define SEA_mmDP5_DP_SEC_AUD_N_READBACK 0x4ba6 +#define SEA_mmDP6_DP_SEC_AUD_N_READBACK 0x4ea6 +#define SEA_mmDP_SEC_AUD_M 0x1ca7 +#define SEA_mmDP0_DP_SEC_AUD_M 0x1ca7 +#define SEA_mmDP1_DP_SEC_AUD_M 0x1fa7 +#define SEA_mmDP2_DP_SEC_AUD_M 0x42a7 +#define SEA_mmDP3_DP_SEC_AUD_M 0x45a7 +#define SEA_mmDP4_DP_SEC_AUD_M 0x48a7 +#define SEA_mmDP5_DP_SEC_AUD_M 0x4ba7 +#define SEA_mmDP6_DP_SEC_AUD_M 0x4ea7 +#define SEA_mmDP_SEC_AUD_M_READBACK 0x1ca8 +#define SEA_mmDP0_DP_SEC_AUD_M_READBACK 0x1ca8 +#define SEA_mmDP1_DP_SEC_AUD_M_READBACK 0x1fa8 +#define SEA_mmDP2_DP_SEC_AUD_M_READBACK 0x42a8 +#define SEA_mmDP3_DP_SEC_AUD_M_READBACK 0x45a8 +#define SEA_mmDP4_DP_SEC_AUD_M_READBACK 0x48a8 +#define SEA_mmDP5_DP_SEC_AUD_M_READBACK 0x4ba8 +#define SEA_mmDP6_DP_SEC_AUD_M_READBACK 0x4ea8 +#define SEA_mmDP_SEC_TIMESTAMP 0x1ca9 +#define SEA_mmDP0_DP_SEC_TIMESTAMP 0x1ca9 +#define SEA_mmDP1_DP_SEC_TIMESTAMP 0x1fa9 +#define SEA_mmDP2_DP_SEC_TIMESTAMP 0x42a9 +#define SEA_mmDP3_DP_SEC_TIMESTAMP 0x45a9 +#define SEA_mmDP4_DP_SEC_TIMESTAMP 0x48a9 +#define SEA_mmDP5_DP_SEC_TIMESTAMP 0x4ba9 +#define SEA_mmDP6_DP_SEC_TIMESTAMP 0x4ea9 +#define SEA_mmDP_SEC_PACKET_CNTL 0x1caa +#define SEA_mmDP0_DP_SEC_PACKET_CNTL 0x1caa +#define SEA_mmDP1_DP_SEC_PACKET_CNTL 0x1faa +#define SEA_mmDP2_DP_SEC_PACKET_CNTL 0x42aa +#define SEA_mmDP3_DP_SEC_PACKET_CNTL 0x45aa +#define SEA_mmDP4_DP_SEC_PACKET_CNTL 0x48aa +#define SEA_mmDP5_DP_SEC_PACKET_CNTL 0x4baa +#define SEA_mmDP6_DP_SEC_PACKET_CNTL 0x4eaa +#define SEA_mmDP_MSE_RATE_CNTL 0x1ce1 +#define SEA_mmDP0_DP_MSE_RATE_CNTL 0x1ce1 +#define SEA_mmDP1_DP_MSE_RATE_CNTL 0x1fe1 +#define SEA_mmDP2_DP_MSE_RATE_CNTL 0x42e1 +#define SEA_mmDP3_DP_MSE_RATE_CNTL 0x45e1 +#define SEA_mmDP4_DP_MSE_RATE_CNTL 0x48e1 +#define SEA_mmDP5_DP_MSE_RATE_CNTL 0x4be1 +#define SEA_mmDP6_DP_MSE_RATE_CNTL 0x4ee1 +#define SEA_mmDP_MSE_RATE_UPDATE 0x1ce3 +#define SEA_mmDP0_DP_MSE_RATE_UPDATE 0x1ce3 +#define SEA_mmDP1_DP_MSE_RATE_UPDATE 0x1fe3 +#define SEA_mmDP2_DP_MSE_RATE_UPDATE 0x42e3 +#define SEA_mmDP3_DP_MSE_RATE_UPDATE 0x45e3 +#define SEA_mmDP4_DP_MSE_RATE_UPDATE 0x48e3 +#define SEA_mmDP5_DP_MSE_RATE_UPDATE 0x4be3 +#define SEA_mmDP6_DP_MSE_RATE_UPDATE 0x4ee3 +#define SEA_mmDP_MSE_SAT0 0x1ce4 +#define SEA_mmDP0_DP_MSE_SAT0 0x1ce4 +#define SEA_mmDP1_DP_MSE_SAT0 0x1fe4 +#define SEA_mmDP2_DP_MSE_SAT0 0x42e4 +#define SEA_mmDP3_DP_MSE_SAT0 0x45e4 +#define SEA_mmDP4_DP_MSE_SAT0 0x48e4 +#define SEA_mmDP5_DP_MSE_SAT0 0x4be4 +#define SEA_mmDP6_DP_MSE_SAT0 0x4ee4 +#define SEA_mmDP_MSE_SAT1 0x1ce5 +#define SEA_mmDP0_DP_MSE_SAT1 0x1ce5 +#define SEA_mmDP1_DP_MSE_SAT1 0x1fe5 +#define SEA_mmDP2_DP_MSE_SAT1 0x42e5 +#define SEA_mmDP3_DP_MSE_SAT1 0x45e5 +#define SEA_mmDP4_DP_MSE_SAT1 0x48e5 +#define SEA_mmDP5_DP_MSE_SAT1 0x4be5 +#define SEA_mmDP6_DP_MSE_SAT1 0x4ee5 +#define SEA_mmDP_MSE_SAT2 0x1ce6 +#define SEA_mmDP0_DP_MSE_SAT2 0x1ce6 +#define SEA_mmDP1_DP_MSE_SAT2 0x1fe6 +#define SEA_mmDP2_DP_MSE_SAT2 0x42e6 +#define SEA_mmDP3_DP_MSE_SAT2 0x45e6 +#define SEA_mmDP4_DP_MSE_SAT2 0x48e6 +#define SEA_mmDP5_DP_MSE_SAT2 0x4be6 +#define SEA_mmDP6_DP_MSE_SAT2 0x4ee6 +#define SEA_mmDP_MSE_SAT_UPDATE 0x1ce7 +#define SEA_mmDP0_DP_MSE_SAT_UPDATE 0x1ce7 +#define SEA_mmDP1_DP_MSE_SAT_UPDATE 0x1fe7 +#define SEA_mmDP2_DP_MSE_SAT_UPDATE 0x42e7 +#define SEA_mmDP3_DP_MSE_SAT_UPDATE 0x45e7 +#define SEA_mmDP4_DP_MSE_SAT_UPDATE 0x48e7 +#define SEA_mmDP5_DP_MSE_SAT_UPDATE 0x4be7 +#define SEA_mmDP6_DP_MSE_SAT_UPDATE 0x4ee7 +#define SEA_mmDP_MSE_LINK_TIMING 0x1ce8 +#define SEA_mmDP0_DP_MSE_LINK_TIMING 0x1ce8 +#define SEA_mmDP1_DP_MSE_LINK_TIMING 0x1fe8 +#define SEA_mmDP2_DP_MSE_LINK_TIMING 0x42e8 +#define SEA_mmDP3_DP_MSE_LINK_TIMING 0x45e8 +#define SEA_mmDP4_DP_MSE_LINK_TIMING 0x48e8 +#define SEA_mmDP5_DP_MSE_LINK_TIMING 0x4be8 +#define SEA_mmDP6_DP_MSE_LINK_TIMING 0x4ee8 +#define SEA_mmDP_MSE_MISC_CNTL 0x1cdb +#define SEA_mmDP0_DP_MSE_MISC_CNTL 0x1cdb +#define SEA_mmDP1_DP_MSE_MISC_CNTL 0x1fdb +#define SEA_mmDP2_DP_MSE_MISC_CNTL 0x42db +#define SEA_mmDP3_DP_MSE_MISC_CNTL 0x45db +#define SEA_mmDP4_DP_MSE_MISC_CNTL 0x48db +#define SEA_mmDP5_DP_MSE_MISC_CNTL 0x4bdb +#define SEA_mmDP6_DP_MSE_MISC_CNTL 0x4edb +#define SEA_mmDP_TEST_DEBUG_INDEX 0x1cfc +#define SEA_mmDP0_DP_TEST_DEBUG_INDEX 0x1cfc +#define SEA_mmDP1_DP_TEST_DEBUG_INDEX 0x1ffc +#define SEA_mmDP2_DP_TEST_DEBUG_INDEX 0x42fc +#define SEA_mmDP3_DP_TEST_DEBUG_INDEX 0x45fc +#define SEA_mmDP4_DP_TEST_DEBUG_INDEX 0x48fc +#define SEA_mmDP5_DP_TEST_DEBUG_INDEX 0x4bfc +#define SEA_mmDP6_DP_TEST_DEBUG_INDEX 0x4efc +#define SEA_mmDP_TEST_DEBUG_DATA 0x1cfd +#define SEA_mmDP0_DP_TEST_DEBUG_DATA 0x1cfd +#define SEA_mmDP1_DP_TEST_DEBUG_DATA 0x1ffd +#define SEA_mmDP2_DP_TEST_DEBUG_DATA 0x42fd +#define SEA_mmDP3_DP_TEST_DEBUG_DATA 0x45fd +#define SEA_mmDP4_DP_TEST_DEBUG_DATA 0x48fd +#define SEA_mmDP5_DP_TEST_DEBUG_DATA 0x4bfd +#define SEA_mmDP6_DP_TEST_DEBUG_DATA 0x4efd +#define SEA_mmAUX_CONTROL 0x1880 +#define SEA_mmDP_AUX0_AUX_CONTROL 0x1880 +#define SEA_mmDP_AUX1_AUX_CONTROL 0x1894 +#define SEA_mmDP_AUX2_AUX_CONTROL 0x18a8 +#define SEA_mmDP_AUX3_AUX_CONTROL 0x18c0 +#define SEA_mmDP_AUX4_AUX_CONTROL 0x18d4 +#define SEA_mmDP_AUX5_AUX_CONTROL 0x18e8 +#define SEA_mmAUX_SW_CONTROL 0x1881 +#define SEA_mmDP_AUX0_AUX_SW_CONTROL 0x1881 +#define SEA_mmDP_AUX1_AUX_SW_CONTROL 0x1895 +#define SEA_mmDP_AUX2_AUX_SW_CONTROL 0x18a9 +#define SEA_mmDP_AUX3_AUX_SW_CONTROL 0x18c1 +#define SEA_mmDP_AUX4_AUX_SW_CONTROL 0x18d5 +#define SEA_mmDP_AUX5_AUX_SW_CONTROL 0x18e9 +#define SEA_mmAUX_ARB_CONTROL 0x1882 +#define SEA_mmDP_AUX0_AUX_ARB_CONTROL 0x1882 +#define SEA_mmDP_AUX1_AUX_ARB_CONTROL 0x1896 +#define SEA_mmDP_AUX2_AUX_ARB_CONTROL 0x18aa +#define SEA_mmDP_AUX3_AUX_ARB_CONTROL 0x18c2 +#define SEA_mmDP_AUX4_AUX_ARB_CONTROL 0x18d6 +#define SEA_mmDP_AUX5_AUX_ARB_CONTROL 0x18ea +#define SEA_mmAUX_INTERRUPT_CONTROL 0x1883 +#define SEA_mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 +#define SEA_mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 +#define SEA_mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18ab +#define SEA_mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18c3 +#define SEA_mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18d7 +#define SEA_mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18eb +#define SEA_mmAUX_SW_STATUS 0x1884 +#define SEA_mmDP_AUX0_AUX_SW_STATUS 0x1884 +#define SEA_mmDP_AUX1_AUX_SW_STATUS 0x1898 +#define SEA_mmDP_AUX2_AUX_SW_STATUS 0x18ac +#define SEA_mmDP_AUX3_AUX_SW_STATUS 0x18c4 +#define SEA_mmDP_AUX4_AUX_SW_STATUS 0x18d8 +#define SEA_mmDP_AUX5_AUX_SW_STATUS 0x18ec +#define SEA_mmAUX_LS_STATUS 0x1885 +#define SEA_mmDP_AUX0_AUX_LS_STATUS 0x1885 +#define SEA_mmDP_AUX1_AUX_LS_STATUS 0x1899 +#define SEA_mmDP_AUX2_AUX_LS_STATUS 0x18ad +#define SEA_mmDP_AUX3_AUX_LS_STATUS 0x18c5 +#define SEA_mmDP_AUX4_AUX_LS_STATUS 0x18d9 +#define SEA_mmDP_AUX5_AUX_LS_STATUS 0x18ed +#define SEA_mmAUX_SW_DATA 0x1886 +#define SEA_mmDP_AUX0_AUX_SW_DATA 0x1886 +#define SEA_mmDP_AUX1_AUX_SW_DATA 0x189a +#define SEA_mmDP_AUX2_AUX_SW_DATA 0x18ae +#define SEA_mmDP_AUX3_AUX_SW_DATA 0x18c6 +#define SEA_mmDP_AUX4_AUX_SW_DATA 0x18da +#define SEA_mmDP_AUX5_AUX_SW_DATA 0x18ee +#define SEA_mmAUX_LS_DATA 0x1887 +#define SEA_mmDP_AUX0_AUX_LS_DATA 0x1887 +#define SEA_mmDP_AUX1_AUX_LS_DATA 0x189b +#define SEA_mmDP_AUX2_AUX_LS_DATA 0x18af +#define SEA_mmDP_AUX3_AUX_LS_DATA 0x18c7 +#define SEA_mmDP_AUX4_AUX_LS_DATA 0x18db +#define SEA_mmDP_AUX5_AUX_LS_DATA 0x18ef +#define SEA_mmAUX_DPHY_TX_REF_CONTROL 0x1888 +#define SEA_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 +#define SEA_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189c +#define SEA_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18b0 +#define SEA_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18c8 +#define SEA_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18dc +#define SEA_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18f0 +#define SEA_mmAUX_DPHY_TX_CONTROL 0x1889 +#define SEA_mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 +#define SEA_mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189d +#define SEA_mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18b1 +#define SEA_mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18c9 +#define SEA_mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18dd +#define SEA_mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18f1 +#define SEA_mmAUX_DPHY_RX_CONTROL0 0x188a +#define SEA_mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188a +#define SEA_mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189e +#define SEA_mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18b2 +#define SEA_mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18ca +#define SEA_mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18de +#define SEA_mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18f2 +#define SEA_mmAUX_DPHY_RX_CONTROL1 0x188b +#define SEA_mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188b +#define SEA_mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189f +#define SEA_mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18b3 +#define SEA_mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18cb +#define SEA_mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18df +#define SEA_mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18f3 +#define SEA_mmAUX_DPHY_TX_STATUS 0x188c +#define SEA_mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188c +#define SEA_mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18a0 +#define SEA_mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18b4 +#define SEA_mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18cc +#define SEA_mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18e0 +#define SEA_mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18f4 +#define SEA_mmAUX_DPHY_RX_STATUS 0x188d +#define SEA_mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188d +#define SEA_mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18a1 +#define SEA_mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18b5 +#define SEA_mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18cd +#define SEA_mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18e1 +#define SEA_mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18f5 +#define SEA_mmAUX_GTC_SYNC_CONTROL 0x188e +#define SEA_mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188e +#define SEA_mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18a2 +#define SEA_mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18b6 +#define SEA_mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18ce +#define SEA_mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18e2 +#define SEA_mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18f6 +#define SEA_mmAUX_GTC_SYNC_ERROR_CONTROL 0x188f +#define SEA_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x188f +#define SEA_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x18a3 +#define SEA_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x18b7 +#define SEA_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x18cf +#define SEA_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x18e3 +#define SEA_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x18f7 +#define SEA_mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 +#define SEA_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 +#define SEA_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18a4 +#define SEA_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18b8 +#define SEA_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18d0 +#define SEA_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18e4 +#define SEA_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18f8 +#define SEA_mmAUX_GTC_SYNC_STATUS 0x1891 +#define SEA_mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1891 +#define SEA_mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x18a5 +#define SEA_mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x18b9 +#define SEA_mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x18d1 +#define SEA_mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x18e5 +#define SEA_mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x18f9 +#define SEA_mmAUX_GTC_SYNC_DATA 0x1892 +#define SEA_mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1892 +#define SEA_mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18a6 +#define SEA_mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18ba +#define SEA_mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18d2 +#define SEA_mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18e6 +#define SEA_mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18fa +#define SEA_mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 +#define SEA_mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 +#define SEA_mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18a7 +#define SEA_mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18bb +#define SEA_mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18d3 +#define SEA_mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18e7 +#define SEA_mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18fb +#define SEA_mmDVO_ENABLE 0x1858 +#define SEA_mmDVO_SOURCE_SELECT 0x1859 +#define SEA_mmDVO_OUTPUT 0x185a +#define SEA_mmDVO_CONTROL 0x185b +#define SEA_mmDVO_CRC_EN 0x185c +#define SEA_mmDVO_CRC2_SIG_MASK 0x185d +#define SEA_mmDVO_CRC2_SIG_RESULT 0x185e +#define SEA_mmDVO_FIFO_ERROR_STATUS 0x185f +#define SEA_mmFBC_CNTL 0x16d0 +#define SEA_mmFBC_IDLE_MASK 0x16d1 +#define SEA_mmFBC_IDLE_FORCE_CLEAR_MASK 0x16d2 +#define SEA_mmFBC_START_STOP_DELAY 0x16d3 +#define SEA_mmFBC_COMP_CNTL 0x16d4 +#define SEA_mmFBC_COMP_MODE 0x16d5 +#define SEA_mmFBC_DEBUG0 0x16d6 +#define SEA_mmFBC_DEBUG1 0x16d7 +#define SEA_mmFBC_DEBUG2 0x16d8 +#define SEA_mmFBC_IND_LUT0 0x16d9 +#define SEA_mmFBC_IND_LUT1 0x16da +#define SEA_mmFBC_IND_LUT2 0x16db +#define SEA_mmFBC_IND_LUT3 0x16dc +#define SEA_mmFBC_IND_LUT4 0x16dd +#define SEA_mmFBC_IND_LUT5 0x16de +#define SEA_mmFBC_IND_LUT6 0x16df +#define SEA_mmFBC_IND_LUT7 0x16e0 +#define SEA_mmFBC_IND_LUT8 0x16e1 +#define SEA_mmFBC_IND_LUT9 0x16e2 +#define SEA_mmFBC_IND_LUT10 0x16e3 +#define SEA_mmFBC_IND_LUT11 0x16e4 +#define SEA_mmFBC_IND_LUT12 0x16e5 +#define SEA_mmFBC_IND_LUT13 0x16e6 +#define SEA_mmFBC_IND_LUT14 0x16e7 +#define SEA_mmFBC_IND_LUT15 0x16e8 +#define SEA_mmFBC_CSM_REGION_OFFSET_01 0x16e9 +#define SEA_mmFBC_CSM_REGION_OFFSET_23 0x16ea +#define SEA_mmFBC_CLIENT_REGION_MASK 0x16eb +#define SEA_mmFBC_DEBUG_COMP 0x16ec +#define SEA_mmFBC_DEBUG_CSR 0x16ed +#define SEA_mmFBC_DEBUG_CSR_RDATA 0x16ee +#define SEA_mmFBC_DEBUG_CSR_WDATA 0x16ef +#define SEA_mmFBC_DEBUG_CSR_RDATA_HI 0x16f6 +#define SEA_mmFBC_DEBUG_CSR_WDATA_HI 0x16f7 +#define SEA_mmFBC_MISC 0x16f0 +#define SEA_mmFBC_STATUS 0x16f1 +#define SEA_mmFBC_TEST_DEBUG_INDEX 0x16f4 +#define SEA_mmFBC_TEST_DEBUG_DATA 0x16f5 +#define SEA_mmFMT_CLAMP_COMPONENT_R 0x1be8 +#define SEA_mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 +#define SEA_mmFMT1_FMT_CLAMP_COMPONENT_R 0x1ee8 +#define SEA_mmFMT2_FMT_CLAMP_COMPONENT_R 0x41e8 +#define SEA_mmFMT3_FMT_CLAMP_COMPONENT_R 0x44e8 +#define SEA_mmFMT4_FMT_CLAMP_COMPONENT_R 0x47e8 +#define SEA_mmFMT5_FMT_CLAMP_COMPONENT_R 0x4ae8 +#define SEA_mmFMT_CLAMP_COMPONENT_G 0x1be9 +#define SEA_mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 +#define SEA_mmFMT1_FMT_CLAMP_COMPONENT_G 0x1ee9 +#define SEA_mmFMT2_FMT_CLAMP_COMPONENT_G 0x41e9 +#define SEA_mmFMT3_FMT_CLAMP_COMPONENT_G 0x44e9 +#define SEA_mmFMT4_FMT_CLAMP_COMPONENT_G 0x47e9 +#define SEA_mmFMT5_FMT_CLAMP_COMPONENT_G 0x4ae9 +#define SEA_mmFMT_CLAMP_COMPONENT_B 0x1bea +#define SEA_mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea +#define SEA_mmFMT1_FMT_CLAMP_COMPONENT_B 0x1eea +#define SEA_mmFMT2_FMT_CLAMP_COMPONENT_B 0x41ea +#define SEA_mmFMT3_FMT_CLAMP_COMPONENT_B 0x44ea +#define SEA_mmFMT4_FMT_CLAMP_COMPONENT_B 0x47ea +#define SEA_mmFMT5_FMT_CLAMP_COMPONENT_B 0x4aea +#define SEA_mmFMT_DYNAMIC_EXP_CNTL 0x1bed +#define SEA_mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed +#define SEA_mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1eed +#define SEA_mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ed +#define SEA_mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ed +#define SEA_mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ed +#define SEA_mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4aed +#define SEA_mmFMT_CONTROL 0x1bee +#define SEA_mmFMT0_FMT_CONTROL 0x1bee +#define SEA_mmFMT1_FMT_CONTROL 0x1eee +#define SEA_mmFMT2_FMT_CONTROL 0x41ee +#define SEA_mmFMT3_FMT_CONTROL 0x44ee +#define SEA_mmFMT4_FMT_CONTROL 0x47ee +#define SEA_mmFMT5_FMT_CONTROL 0x4aee +#define SEA_mmFMT_FORCE_OUTPUT_CNTL 0x1bef +#define SEA_mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef +#define SEA_mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1eef +#define SEA_mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41ef +#define SEA_mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44ef +#define SEA_mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47ef +#define SEA_mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4aef +#define SEA_mmFMT_FORCE_DATA_0_1 0x1bf0 +#define SEA_mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0 +#define SEA_mmFMT1_FMT_FORCE_DATA_0_1 0x1ef0 +#define SEA_mmFMT2_FMT_FORCE_DATA_0_1 0x41f0 +#define SEA_mmFMT3_FMT_FORCE_DATA_0_1 0x44f0 +#define SEA_mmFMT4_FMT_FORCE_DATA_0_1 0x47f0 +#define SEA_mmFMT5_FMT_FORCE_DATA_0_1 0x4af0 +#define SEA_mmFMT_FORCE_DATA_2_3 0x1bf1 +#define SEA_mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1 +#define SEA_mmFMT1_FMT_FORCE_DATA_2_3 0x1ef1 +#define SEA_mmFMT2_FMT_FORCE_DATA_2_3 0x41f1 +#define SEA_mmFMT3_FMT_FORCE_DATA_2_3 0x44f1 +#define SEA_mmFMT4_FMT_FORCE_DATA_2_3 0x47f1 +#define SEA_mmFMT5_FMT_FORCE_DATA_2_3 0x4af1 +#define SEA_mmFMT_BIT_DEPTH_CONTROL 0x1bf2 +#define SEA_mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 +#define SEA_mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1ef2 +#define SEA_mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41f2 +#define SEA_mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44f2 +#define SEA_mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47f2 +#define SEA_mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4af2 +#define SEA_mmFMT_DITHER_RAND_R_SEED 0x1bf3 +#define SEA_mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 +#define SEA_mmFMT1_FMT_DITHER_RAND_R_SEED 0x1ef3 +#define SEA_mmFMT2_FMT_DITHER_RAND_R_SEED 0x41f3 +#define SEA_mmFMT3_FMT_DITHER_RAND_R_SEED 0x44f3 +#define SEA_mmFMT4_FMT_DITHER_RAND_R_SEED 0x47f3 +#define SEA_mmFMT5_FMT_DITHER_RAND_R_SEED 0x4af3 +#define SEA_mmFMT_DITHER_RAND_G_SEED 0x1bf4 +#define SEA_mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 +#define SEA_mmFMT1_FMT_DITHER_RAND_G_SEED 0x1ef4 +#define SEA_mmFMT2_FMT_DITHER_RAND_G_SEED 0x41f4 +#define SEA_mmFMT3_FMT_DITHER_RAND_G_SEED 0x44f4 +#define SEA_mmFMT4_FMT_DITHER_RAND_G_SEED 0x47f4 +#define SEA_mmFMT5_FMT_DITHER_RAND_G_SEED 0x4af4 +#define SEA_mmFMT_DITHER_RAND_B_SEED 0x1bf5 +#define SEA_mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 +#define SEA_mmFMT1_FMT_DITHER_RAND_B_SEED 0x1ef5 +#define SEA_mmFMT2_FMT_DITHER_RAND_B_SEED 0x41f5 +#define SEA_mmFMT3_FMT_DITHER_RAND_B_SEED 0x44f5 +#define SEA_mmFMT4_FMT_DITHER_RAND_B_SEED 0x47f5 +#define SEA_mmFMT5_FMT_DITHER_RAND_B_SEED 0x4af5 +#define SEA_mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define SEA_mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define SEA_mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ef6 +#define SEA_mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 +#define SEA_mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44f6 +#define SEA_mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47f6 +#define SEA_mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4af6 +#define SEA_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define SEA_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define SEA_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ef7 +#define SEA_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 +#define SEA_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44f7 +#define SEA_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47f7 +#define SEA_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4af7 +#define SEA_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define SEA_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define SEA_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ef8 +#define SEA_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 +#define SEA_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44f8 +#define SEA_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47f8 +#define SEA_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4af8 +#define SEA_mmFMT_CLAMP_CNTL 0x1bf9 +#define SEA_mmFMT0_FMT_CLAMP_CNTL 0x1bf9 +#define SEA_mmFMT1_FMT_CLAMP_CNTL 0x1ef9 +#define SEA_mmFMT2_FMT_CLAMP_CNTL 0x41f9 +#define SEA_mmFMT3_FMT_CLAMP_CNTL 0x44f9 +#define SEA_mmFMT4_FMT_CLAMP_CNTL 0x47f9 +#define SEA_mmFMT5_FMT_CLAMP_CNTL 0x4af9 +#define SEA_mmFMT_CRC_CNTL 0x1bfa +#define SEA_mmFMT0_FMT_CRC_CNTL 0x1bfa +#define SEA_mmFMT1_FMT_CRC_CNTL 0x1efa +#define SEA_mmFMT2_FMT_CRC_CNTL 0x41fa +#define SEA_mmFMT3_FMT_CRC_CNTL 0x44fa +#define SEA_mmFMT4_FMT_CRC_CNTL 0x47fa +#define SEA_mmFMT5_FMT_CRC_CNTL 0x4afa +#define SEA_mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define SEA_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define SEA_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1efb +#define SEA_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb +#define SEA_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44fb +#define SEA_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47fb +#define SEA_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4afb +#define SEA_mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define SEA_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define SEA_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1efc +#define SEA_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc +#define SEA_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44fc +#define SEA_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47fc +#define SEA_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4afc +#define SEA_mmFMT_CRC_SIG_RED_GREEN 0x1bfd +#define SEA_mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd +#define SEA_mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1efd +#define SEA_mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41fd +#define SEA_mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44fd +#define SEA_mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47fd +#define SEA_mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4afd +#define SEA_mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define SEA_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define SEA_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1efe +#define SEA_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41fe +#define SEA_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44fe +#define SEA_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47fe +#define SEA_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4afe +#define SEA_mmFMT_DEBUG_CNTL 0x1bff +#define SEA_mmFMT0_FMT_DEBUG_CNTL 0x1bff +#define SEA_mmFMT1_FMT_DEBUG_CNTL 0x1eff +#define SEA_mmFMT2_FMT_DEBUG_CNTL 0x41ff +#define SEA_mmFMT3_FMT_DEBUG_CNTL 0x44ff +#define SEA_mmFMT4_FMT_DEBUG_CNTL 0x47ff +#define SEA_mmFMT5_FMT_DEBUG_CNTL 0x4aff +#define SEA_mmFMT_TEST_DEBUG_INDEX 0x1beb +#define SEA_mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb +#define SEA_mmFMT1_FMT_TEST_DEBUG_INDEX 0x1eeb +#define SEA_mmFMT2_FMT_TEST_DEBUG_INDEX 0x41eb +#define SEA_mmFMT3_FMT_TEST_DEBUG_INDEX 0x44eb +#define SEA_mmFMT4_FMT_TEST_DEBUG_INDEX 0x47eb +#define SEA_mmFMT5_FMT_TEST_DEBUG_INDEX 0x4aeb +#define SEA_mmFMT_TEST_DEBUG_DATA 0x1bec +#define SEA_mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec +#define SEA_mmFMT1_FMT_TEST_DEBUG_DATA 0x1eec +#define SEA_mmFMT2_FMT_TEST_DEBUG_DATA 0x41ec +#define SEA_mmFMT3_FMT_TEST_DEBUG_DATA 0x44ec +#define SEA_mmFMT4_FMT_TEST_DEBUG_DATA 0x47ec +#define SEA_mmFMT5_FMT_TEST_DEBUG_DATA 0x4aec +#define SEA_ixFMT_DEBUG0 0x1 +#define SEA_ixFMT_DEBUG1 0x2 +#define SEA_ixFMT_DEBUG2 0x3 +#define SEA_ixFMT_DEBUG_ID 0x0 +#define SEA_mmLB_DATA_FORMAT 0x1ac0 +#define SEA_mmLB0_LB_DATA_FORMAT 0x1ac0 +#define SEA_mmLB1_LB_DATA_FORMAT 0x1dc0 +#define SEA_mmLB2_LB_DATA_FORMAT 0x40c0 +#define SEA_mmLB3_LB_DATA_FORMAT 0x43c0 +#define SEA_mmLB4_LB_DATA_FORMAT 0x46c0 +#define SEA_mmLB5_LB_DATA_FORMAT 0x49c0 +#define SEA_mmLB_MEMORY_CTRL 0x1ac1 +#define SEA_mmLB0_LB_MEMORY_CTRL 0x1ac1 +#define SEA_mmLB1_LB_MEMORY_CTRL 0x1dc1 +#define SEA_mmLB2_LB_MEMORY_CTRL 0x40c1 +#define SEA_mmLB3_LB_MEMORY_CTRL 0x43c1 +#define SEA_mmLB4_LB_MEMORY_CTRL 0x46c1 +#define SEA_mmLB5_LB_MEMORY_CTRL 0x49c1 +#define SEA_mmLB_MEMORY_SIZE_STATUS 0x1ac2 +#define SEA_mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 +#define SEA_mmLB1_LB_MEMORY_SIZE_STATUS 0x1dc2 +#define SEA_mmLB2_LB_MEMORY_SIZE_STATUS 0x40c2 +#define SEA_mmLB3_LB_MEMORY_SIZE_STATUS 0x43c2 +#define SEA_mmLB4_LB_MEMORY_SIZE_STATUS 0x46c2 +#define SEA_mmLB5_LB_MEMORY_SIZE_STATUS 0x49c2 +#define SEA_mmLB_DESKTOP_HEIGHT 0x1ac3 +#define SEA_mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 +#define SEA_mmLB1_LB_DESKTOP_HEIGHT 0x1dc3 +#define SEA_mmLB2_LB_DESKTOP_HEIGHT 0x40c3 +#define SEA_mmLB3_LB_DESKTOP_HEIGHT 0x43c3 +#define SEA_mmLB4_LB_DESKTOP_HEIGHT 0x46c3 +#define SEA_mmLB5_LB_DESKTOP_HEIGHT 0x49c3 +#define SEA_mmLB_VLINE_START_END 0x1ac4 +#define SEA_mmLB0_LB_VLINE_START_END 0x1ac4 +#define SEA_mmLB1_LB_VLINE_START_END 0x1dc4 +#define SEA_mmLB2_LB_VLINE_START_END 0x40c4 +#define SEA_mmLB3_LB_VLINE_START_END 0x43c4 +#define SEA_mmLB4_LB_VLINE_START_END 0x46c4 +#define SEA_mmLB5_LB_VLINE_START_END 0x49c4 +#define SEA_mmLB_VLINE2_START_END 0x1ac5 +#define SEA_mmLB0_LB_VLINE2_START_END 0x1ac5 +#define SEA_mmLB1_LB_VLINE2_START_END 0x1dc5 +#define SEA_mmLB2_LB_VLINE2_START_END 0x40c5 +#define SEA_mmLB3_LB_VLINE2_START_END 0x43c5 +#define SEA_mmLB4_LB_VLINE2_START_END 0x46c5 +#define SEA_mmLB5_LB_VLINE2_START_END 0x49c5 +#define SEA_mmLB_V_COUNTER 0x1ac6 +#define SEA_mmLB0_LB_V_COUNTER 0x1ac6 +#define SEA_mmLB1_LB_V_COUNTER 0x1dc6 +#define SEA_mmLB2_LB_V_COUNTER 0x40c6 +#define SEA_mmLB3_LB_V_COUNTER 0x43c6 +#define SEA_mmLB4_LB_V_COUNTER 0x46c6 +#define SEA_mmLB5_LB_V_COUNTER 0x49c6 +#define SEA_mmLB_SNAPSHOT_V_COUNTER 0x1ac7 +#define SEA_mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 +#define SEA_mmLB1_LB_SNAPSHOT_V_COUNTER 0x1dc7 +#define SEA_mmLB2_LB_SNAPSHOT_V_COUNTER 0x40c7 +#define SEA_mmLB3_LB_SNAPSHOT_V_COUNTER 0x43c7 +#define SEA_mmLB4_LB_SNAPSHOT_V_COUNTER 0x46c7 +#define SEA_mmLB5_LB_SNAPSHOT_V_COUNTER 0x49c7 +#define SEA_mmLB_INTERRUPT_MASK 0x1ac8 +#define SEA_mmLB0_LB_INTERRUPT_MASK 0x1ac8 +#define SEA_mmLB1_LB_INTERRUPT_MASK 0x1dc8 +#define SEA_mmLB2_LB_INTERRUPT_MASK 0x40c8 +#define SEA_mmLB3_LB_INTERRUPT_MASK 0x43c8 +#define SEA_mmLB4_LB_INTERRUPT_MASK 0x46c8 +#define SEA_mmLB5_LB_INTERRUPT_MASK 0x49c8 +#define SEA_mmLB_VLINE_STATUS 0x1ac9 +#define SEA_mmLB0_LB_VLINE_STATUS 0x1ac9 +#define SEA_mmLB1_LB_VLINE_STATUS 0x1dc9 +#define SEA_mmLB2_LB_VLINE_STATUS 0x40c9 +#define SEA_mmLB3_LB_VLINE_STATUS 0x43c9 +#define SEA_mmLB4_LB_VLINE_STATUS 0x46c9 +#define SEA_mmLB5_LB_VLINE_STATUS 0x49c9 +#define SEA_mmLB_VLINE2_STATUS 0x1aca +#define SEA_mmLB0_LB_VLINE2_STATUS 0x1aca +#define SEA_mmLB1_LB_VLINE2_STATUS 0x1dca +#define SEA_mmLB2_LB_VLINE2_STATUS 0x40ca +#define SEA_mmLB3_LB_VLINE2_STATUS 0x43ca +#define SEA_mmLB4_LB_VLINE2_STATUS 0x46ca +#define SEA_mmLB5_LB_VLINE2_STATUS 0x49ca +#define SEA_mmLB_VBLANK_STATUS 0x1acb +#define SEA_mmLB0_LB_VBLANK_STATUS 0x1acb +#define SEA_mmLB1_LB_VBLANK_STATUS 0x1dcb +#define SEA_mmLB2_LB_VBLANK_STATUS 0x40cb +#define SEA_mmLB3_LB_VBLANK_STATUS 0x43cb +#define SEA_mmLB4_LB_VBLANK_STATUS 0x46cb +#define SEA_mmLB5_LB_VBLANK_STATUS 0x49cb +#define SEA_mmLB_SYNC_RESET_SEL 0x1acc +#define SEA_mmLB0_LB_SYNC_RESET_SEL 0x1acc +#define SEA_mmLB1_LB_SYNC_RESET_SEL 0x1dcc +#define SEA_mmLB2_LB_SYNC_RESET_SEL 0x40cc +#define SEA_mmLB3_LB_SYNC_RESET_SEL 0x43cc +#define SEA_mmLB4_LB_SYNC_RESET_SEL 0x46cc +#define SEA_mmLB5_LB_SYNC_RESET_SEL 0x49cc +#define SEA_mmLB_BLACK_KEYER_R_CR 0x1acd +#define SEA_mmLB0_LB_BLACK_KEYER_R_CR 0x1acd +#define SEA_mmLB1_LB_BLACK_KEYER_R_CR 0x1dcd +#define SEA_mmLB2_LB_BLACK_KEYER_R_CR 0x40cd +#define SEA_mmLB3_LB_BLACK_KEYER_R_CR 0x43cd +#define SEA_mmLB4_LB_BLACK_KEYER_R_CR 0x46cd +#define SEA_mmLB5_LB_BLACK_KEYER_R_CR 0x49cd +#define SEA_mmLB_BLACK_KEYER_G_Y 0x1ace +#define SEA_mmLB0_LB_BLACK_KEYER_G_Y 0x1ace +#define SEA_mmLB1_LB_BLACK_KEYER_G_Y 0x1dce +#define SEA_mmLB2_LB_BLACK_KEYER_G_Y 0x40ce +#define SEA_mmLB3_LB_BLACK_KEYER_G_Y 0x43ce +#define SEA_mmLB4_LB_BLACK_KEYER_G_Y 0x46ce +#define SEA_mmLB5_LB_BLACK_KEYER_G_Y 0x49ce +#define SEA_mmLB_BLACK_KEYER_B_CB 0x1acf +#define SEA_mmLB0_LB_BLACK_KEYER_B_CB 0x1acf +#define SEA_mmLB1_LB_BLACK_KEYER_B_CB 0x1dcf +#define SEA_mmLB2_LB_BLACK_KEYER_B_CB 0x40cf +#define SEA_mmLB3_LB_BLACK_KEYER_B_CB 0x43cf +#define SEA_mmLB4_LB_BLACK_KEYER_B_CB 0x46cf +#define SEA_mmLB5_LB_BLACK_KEYER_B_CB 0x49cf +#define SEA_mmLB_KEYER_COLOR_CTRL 0x1ad0 +#define SEA_mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 +#define SEA_mmLB1_LB_KEYER_COLOR_CTRL 0x1dd0 +#define SEA_mmLB2_LB_KEYER_COLOR_CTRL 0x40d0 +#define SEA_mmLB3_LB_KEYER_COLOR_CTRL 0x43d0 +#define SEA_mmLB4_LB_KEYER_COLOR_CTRL 0x46d0 +#define SEA_mmLB5_LB_KEYER_COLOR_CTRL 0x49d0 +#define SEA_mmLB_KEYER_COLOR_R_CR 0x1ad1 +#define SEA_mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 +#define SEA_mmLB1_LB_KEYER_COLOR_R_CR 0x1dd1 +#define SEA_mmLB2_LB_KEYER_COLOR_R_CR 0x40d1 +#define SEA_mmLB3_LB_KEYER_COLOR_R_CR 0x43d1 +#define SEA_mmLB4_LB_KEYER_COLOR_R_CR 0x46d1 +#define SEA_mmLB5_LB_KEYER_COLOR_R_CR 0x49d1 +#define SEA_mmLB_KEYER_COLOR_G_Y 0x1ad2 +#define SEA_mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 +#define SEA_mmLB1_LB_KEYER_COLOR_G_Y 0x1dd2 +#define SEA_mmLB2_LB_KEYER_COLOR_G_Y 0x40d2 +#define SEA_mmLB3_LB_KEYER_COLOR_G_Y 0x43d2 +#define SEA_mmLB4_LB_KEYER_COLOR_G_Y 0x46d2 +#define SEA_mmLB5_LB_KEYER_COLOR_G_Y 0x49d2 +#define SEA_mmLB_KEYER_COLOR_B_CB 0x1ad3 +#define SEA_mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 +#define SEA_mmLB1_LB_KEYER_COLOR_B_CB 0x1dd3 +#define SEA_mmLB2_LB_KEYER_COLOR_B_CB 0x40d3 +#define SEA_mmLB3_LB_KEYER_COLOR_B_CB 0x43d3 +#define SEA_mmLB4_LB_KEYER_COLOR_B_CB 0x46d3 +#define SEA_mmLB5_LB_KEYER_COLOR_B_CB 0x49d3 +#define SEA_mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define SEA_mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define SEA_mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1dd4 +#define SEA_mmLB2_LB_KEYER_COLOR_REP_R_CR 0x40d4 +#define SEA_mmLB3_LB_KEYER_COLOR_REP_R_CR 0x43d4 +#define SEA_mmLB4_LB_KEYER_COLOR_REP_R_CR 0x46d4 +#define SEA_mmLB5_LB_KEYER_COLOR_REP_R_CR 0x49d4 +#define SEA_mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define SEA_mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define SEA_mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1dd5 +#define SEA_mmLB2_LB_KEYER_COLOR_REP_G_Y 0x40d5 +#define SEA_mmLB3_LB_KEYER_COLOR_REP_G_Y 0x43d5 +#define SEA_mmLB4_LB_KEYER_COLOR_REP_G_Y 0x46d5 +#define SEA_mmLB5_LB_KEYER_COLOR_REP_G_Y 0x49d5 +#define SEA_mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define SEA_mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define SEA_mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1dd6 +#define SEA_mmLB2_LB_KEYER_COLOR_REP_B_CB 0x40d6 +#define SEA_mmLB3_LB_KEYER_COLOR_REP_B_CB 0x43d6 +#define SEA_mmLB4_LB_KEYER_COLOR_REP_B_CB 0x46d6 +#define SEA_mmLB5_LB_KEYER_COLOR_REP_B_CB 0x49d6 +#define SEA_mmLB_BUFFER_LEVEL_STATUS 0x1ad7 +#define SEA_mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 +#define SEA_mmLB1_LB_BUFFER_LEVEL_STATUS 0x1dd7 +#define SEA_mmLB2_LB_BUFFER_LEVEL_STATUS 0x40d7 +#define SEA_mmLB3_LB_BUFFER_LEVEL_STATUS 0x43d7 +#define SEA_mmLB4_LB_BUFFER_LEVEL_STATUS 0x46d7 +#define SEA_mmLB5_LB_BUFFER_LEVEL_STATUS 0x49d7 +#define SEA_mmLB_BUFFER_URGENCY_CTRL 0x1ad8 +#define SEA_mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 +#define SEA_mmLB1_LB_BUFFER_URGENCY_CTRL 0x1dd8 +#define SEA_mmLB2_LB_BUFFER_URGENCY_CTRL 0x40d8 +#define SEA_mmLB3_LB_BUFFER_URGENCY_CTRL 0x43d8 +#define SEA_mmLB4_LB_BUFFER_URGENCY_CTRL 0x46d8 +#define SEA_mmLB5_LB_BUFFER_URGENCY_CTRL 0x49d8 +#define SEA_mmLB_BUFFER_URGENCY_STATUS 0x1ad9 +#define SEA_mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 +#define SEA_mmLB1_LB_BUFFER_URGENCY_STATUS 0x1dd9 +#define SEA_mmLB2_LB_BUFFER_URGENCY_STATUS 0x40d9 +#define SEA_mmLB3_LB_BUFFER_URGENCY_STATUS 0x43d9 +#define SEA_mmLB4_LB_BUFFER_URGENCY_STATUS 0x46d9 +#define SEA_mmLB5_LB_BUFFER_URGENCY_STATUS 0x49d9 +#define SEA_mmLB_BUFFER_STATUS 0x1ada +#define SEA_mmLB0_LB_BUFFER_STATUS 0x1ada +#define SEA_mmLB1_LB_BUFFER_STATUS 0x1dda +#define SEA_mmLB2_LB_BUFFER_STATUS 0x40da +#define SEA_mmLB3_LB_BUFFER_STATUS 0x43da +#define SEA_mmLB4_LB_BUFFER_STATUS 0x46da +#define SEA_mmLB5_LB_BUFFER_STATUS 0x49da +#define SEA_mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define SEA_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define SEA_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1ddc +#define SEA_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc +#define SEA_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43dc +#define SEA_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46dc +#define SEA_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49dc +#define SEA_mmMVP_AFR_FLIP_MODE 0x1ae0 +#define SEA_mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 +#define SEA_mmLB1_MVP_AFR_FLIP_MODE 0x1de0 +#define SEA_mmLB2_MVP_AFR_FLIP_MODE 0x40e0 +#define SEA_mmLB3_MVP_AFR_FLIP_MODE 0x43e0 +#define SEA_mmLB4_MVP_AFR_FLIP_MODE 0x46e0 +#define SEA_mmLB5_MVP_AFR_FLIP_MODE 0x49e0 +#define SEA_mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define SEA_mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define SEA_mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1de1 +#define SEA_mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 +#define SEA_mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43e1 +#define SEA_mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46e1 +#define SEA_mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49e1 +#define SEA_mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define SEA_mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define SEA_mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1de2 +#define SEA_mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40e2 +#define SEA_mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43e2 +#define SEA_mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46e2 +#define SEA_mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49e2 +#define SEA_mmDC_MVP_LB_CONTROL 0x1ae3 +#define SEA_mmLB0_DC_MVP_LB_CONTROL 0x1ae3 +#define SEA_mmLB1_DC_MVP_LB_CONTROL 0x1de3 +#define SEA_mmLB2_DC_MVP_LB_CONTROL 0x40e3 +#define SEA_mmLB3_DC_MVP_LB_CONTROL 0x43e3 +#define SEA_mmLB4_DC_MVP_LB_CONTROL 0x46e3 +#define SEA_mmLB5_DC_MVP_LB_CONTROL 0x49e3 +#define SEA_mmLB_DEBUG 0x1ae4 +#define SEA_mmLB0_LB_DEBUG 0x1ae4 +#define SEA_mmLB1_LB_DEBUG 0x1de4 +#define SEA_mmLB2_LB_DEBUG 0x40e4 +#define SEA_mmLB3_LB_DEBUG 0x43e4 +#define SEA_mmLB4_LB_DEBUG 0x46e4 +#define SEA_mmLB5_LB_DEBUG 0x49e4 +#define SEA_mmLB_DEBUG2 0x1ae5 +#define SEA_mmLB0_LB_DEBUG2 0x1ae5 +#define SEA_mmLB1_LB_DEBUG2 0x1de5 +#define SEA_mmLB2_LB_DEBUG2 0x40e5 +#define SEA_mmLB3_LB_DEBUG2 0x43e5 +#define SEA_mmLB4_LB_DEBUG2 0x46e5 +#define SEA_mmLB5_LB_DEBUG2 0x49e5 +#define SEA_mmLB_DEBUG3 0x1ae6 +#define SEA_mmLB0_LB_DEBUG3 0x1ae6 +#define SEA_mmLB1_LB_DEBUG3 0x1de6 +#define SEA_mmLB2_LB_DEBUG3 0x40e6 +#define SEA_mmLB3_LB_DEBUG3 0x43e6 +#define SEA_mmLB4_LB_DEBUG3 0x46e6 +#define SEA_mmLB5_LB_DEBUG3 0x49e6 +#define SEA_mmLB_TEST_DEBUG_INDEX 0x1afe +#define SEA_mmLB0_LB_TEST_DEBUG_INDEX 0x1afe +#define SEA_mmLB1_LB_TEST_DEBUG_INDEX 0x1dfe +#define SEA_mmLB2_LB_TEST_DEBUG_INDEX 0x40fe +#define SEA_mmLB3_LB_TEST_DEBUG_INDEX 0x43fe +#define SEA_mmLB4_LB_TEST_DEBUG_INDEX 0x46fe +#define SEA_mmLB5_LB_TEST_DEBUG_INDEX 0x49fe +#define SEA_mmLB_TEST_DEBUG_DATA 0x1aff +#define SEA_mmLB0_LB_TEST_DEBUG_DATA 0x1aff +#define SEA_mmLB1_LB_TEST_DEBUG_DATA 0x1dff +#define SEA_mmLB2_LB_TEST_DEBUG_DATA 0x40ff +#define SEA_mmLB3_LB_TEST_DEBUG_DATA 0x43ff +#define SEA_mmLB4_LB_TEST_DEBUG_DATA 0x46ff +#define SEA_mmLB5_LB_TEST_DEBUG_DATA 0x49ff +#define SEA_mmMVP_CONTROL1 0x1680 +#define SEA_mmMVP_CONTROL2 0x1681 +#define SEA_mmMVP_FIFO_CONTROL 0x1682 +#define SEA_mmMVP_FIFO_STATUS 0x1683 +#define SEA_mmMVP_SLAVE_STATUS 0x1684 +#define SEA_mmMVP_INBAND_CNTL_CAP 0x1685 +#define SEA_mmMVP_BLACK_KEYER 0x1686 +#define SEA_mmMVP_CRC_CNTL 0x1687 +#define SEA_mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 +#define SEA_mmMVP_CRC_RESULT_RED 0x1689 +#define SEA_mmMVP_CONTROL3 0x168a +#define SEA_mmMVP_RECEIVE_CNT_CNTL1 0x168b +#define SEA_mmMVP_RECEIVE_CNT_CNTL2 0x168c +#define SEA_mmMVP_DEBUG 0x168f +#define SEA_mmMVP_TEST_DEBUG_INDEX 0x168d +#define SEA_mmMVP_TEST_DEBUG_DATA 0x168e +#define SEA_ixMVP_DEBUG_12 0xc +#define SEA_ixMVP_DEBUG_13 0xd +#define SEA_ixMVP_DEBUG_14 0xe +#define SEA_ixMVP_DEBUG_15 0xf +#define SEA_ixMVP_DEBUG_16 0x10 +#define SEA_ixMVP_DEBUG_17 0x11 +#define SEA_mmSCL_COEF_RAM_SELECT 0x1b40 +#define SEA_mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 +#define SEA_mmSCL1_SCL_COEF_RAM_SELECT 0x1e40 +#define SEA_mmSCL2_SCL_COEF_RAM_SELECT 0x4140 +#define SEA_mmSCL3_SCL_COEF_RAM_SELECT 0x4440 +#define SEA_mmSCL4_SCL_COEF_RAM_SELECT 0x4740 +#define SEA_mmSCL5_SCL_COEF_RAM_SELECT 0x4a40 +#define SEA_mmSCL_COEF_RAM_TAP_DATA 0x1b41 +#define SEA_mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 +#define SEA_mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1e41 +#define SEA_mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 +#define SEA_mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 +#define SEA_mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 +#define SEA_mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4a41 +#define SEA_mmSCL_MODE 0x1b42 +#define SEA_mmSCL0_SCL_MODE 0x1b42 +#define SEA_mmSCL1_SCL_MODE 0x1e42 +#define SEA_mmSCL2_SCL_MODE 0x4142 +#define SEA_mmSCL3_SCL_MODE 0x4442 +#define SEA_mmSCL4_SCL_MODE 0x4742 +#define SEA_mmSCL5_SCL_MODE 0x4a42 +#define SEA_mmSCL_TAP_CONTROL 0x1b43 +#define SEA_mmSCL0_SCL_TAP_CONTROL 0x1b43 +#define SEA_mmSCL1_SCL_TAP_CONTROL 0x1e43 +#define SEA_mmSCL2_SCL_TAP_CONTROL 0x4143 +#define SEA_mmSCL3_SCL_TAP_CONTROL 0x4443 +#define SEA_mmSCL4_SCL_TAP_CONTROL 0x4743 +#define SEA_mmSCL5_SCL_TAP_CONTROL 0x4a43 +#define SEA_mmSCL_CONTROL 0x1b44 +#define SEA_mmSCL0_SCL_CONTROL 0x1b44 +#define SEA_mmSCL1_SCL_CONTROL 0x1e44 +#define SEA_mmSCL2_SCL_CONTROL 0x4144 +#define SEA_mmSCL3_SCL_CONTROL 0x4444 +#define SEA_mmSCL4_SCL_CONTROL 0x4744 +#define SEA_mmSCL5_SCL_CONTROL 0x4a44 +#define SEA_mmSCL_BYPASS_CONTROL 0x1b45 +#define SEA_mmSCL0_SCL_BYPASS_CONTROL 0x1b45 +#define SEA_mmSCL1_SCL_BYPASS_CONTROL 0x1e45 +#define SEA_mmSCL2_SCL_BYPASS_CONTROL 0x4145 +#define SEA_mmSCL3_SCL_BYPASS_CONTROL 0x4445 +#define SEA_mmSCL4_SCL_BYPASS_CONTROL 0x4745 +#define SEA_mmSCL5_SCL_BYPASS_CONTROL 0x4a45 +#define SEA_mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define SEA_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define SEA_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1e46 +#define SEA_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define SEA_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 +#define SEA_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 +#define SEA_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4a46 +#define SEA_mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define SEA_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define SEA_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1e47 +#define SEA_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define SEA_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 +#define SEA_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 +#define SEA_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4a47 +#define SEA_mmSCL_HORZ_FILTER_CONTROL 0x1b48 +#define SEA_mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 +#define SEA_mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1e48 +#define SEA_mmSCL2_SCL_HORZ_FILTER_CONTROL 0x4148 +#define SEA_mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4448 +#define SEA_mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4748 +#define SEA_mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4a48 +#define SEA_mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define SEA_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define SEA_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1e49 +#define SEA_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 +#define SEA_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4449 +#define SEA_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4749 +#define SEA_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4a49 +#define SEA_mmSCL_HORZ_FILTER_INIT 0x1b4a +#define SEA_mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a +#define SEA_mmSCL1_SCL_HORZ_FILTER_INIT 0x1e4a +#define SEA_mmSCL2_SCL_HORZ_FILTER_INIT 0x414a +#define SEA_mmSCL3_SCL_HORZ_FILTER_INIT 0x444a +#define SEA_mmSCL4_SCL_HORZ_FILTER_INIT 0x474a +#define SEA_mmSCL5_SCL_HORZ_FILTER_INIT 0x4a4a +#define SEA_mmSCL_VERT_FILTER_CONTROL 0x1b4b +#define SEA_mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b +#define SEA_mmSCL1_SCL_VERT_FILTER_CONTROL 0x1e4b +#define SEA_mmSCL2_SCL_VERT_FILTER_CONTROL 0x414b +#define SEA_mmSCL3_SCL_VERT_FILTER_CONTROL 0x444b +#define SEA_mmSCL4_SCL_VERT_FILTER_CONTROL 0x474b +#define SEA_mmSCL5_SCL_VERT_FILTER_CONTROL 0x4a4b +#define SEA_mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define SEA_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define SEA_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1e4c +#define SEA_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414c +#define SEA_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444c +#define SEA_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474c +#define SEA_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4a4c +#define SEA_mmSCL_VERT_FILTER_INIT 0x1b4d +#define SEA_mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d +#define SEA_mmSCL1_SCL_VERT_FILTER_INIT 0x1e4d +#define SEA_mmSCL2_SCL_VERT_FILTER_INIT 0x414d +#define SEA_mmSCL3_SCL_VERT_FILTER_INIT 0x444d +#define SEA_mmSCL4_SCL_VERT_FILTER_INIT 0x474d +#define SEA_mmSCL5_SCL_VERT_FILTER_INIT 0x4a4d +#define SEA_mmSCL_VERT_FILTER_INIT_BOT 0x1b4e +#define SEA_mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e +#define SEA_mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1e4e +#define SEA_mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x414e +#define SEA_mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x444e +#define SEA_mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x474e +#define SEA_mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4a4e +#define SEA_mmSCL_ROUND_OFFSET 0x1b4f +#define SEA_mmSCL0_SCL_ROUND_OFFSET 0x1b4f +#define SEA_mmSCL1_SCL_ROUND_OFFSET 0x1e4f +#define SEA_mmSCL2_SCL_ROUND_OFFSET 0x414f +#define SEA_mmSCL3_SCL_ROUND_OFFSET 0x444f +#define SEA_mmSCL4_SCL_ROUND_OFFSET 0x474f +#define SEA_mmSCL5_SCL_ROUND_OFFSET 0x4a4f +#define SEA_mmSCL_UPDATE 0x1b51 +#define SEA_mmSCL0_SCL_UPDATE 0x1b51 +#define SEA_mmSCL1_SCL_UPDATE 0x1e51 +#define SEA_mmSCL2_SCL_UPDATE 0x4151 +#define SEA_mmSCL3_SCL_UPDATE 0x4451 +#define SEA_mmSCL4_SCL_UPDATE 0x4751 +#define SEA_mmSCL5_SCL_UPDATE 0x4a51 +#define SEA_mmSCL_F_SHARP_CONTROL 0x1b53 +#define SEA_mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 +#define SEA_mmSCL1_SCL_F_SHARP_CONTROL 0x1e53 +#define SEA_mmSCL2_SCL_F_SHARP_CONTROL 0x4153 +#define SEA_mmSCL3_SCL_F_SHARP_CONTROL 0x4453 +#define SEA_mmSCL4_SCL_F_SHARP_CONTROL 0x4753 +#define SEA_mmSCL5_SCL_F_SHARP_CONTROL 0x4a53 +#define SEA_mmSCL_ALU_CONTROL 0x1b54 +#define SEA_mmSCL0_SCL_ALU_CONTROL 0x1b54 +#define SEA_mmSCL1_SCL_ALU_CONTROL 0x1e54 +#define SEA_mmSCL2_SCL_ALU_CONTROL 0x4154 +#define SEA_mmSCL3_SCL_ALU_CONTROL 0x4454 +#define SEA_mmSCL4_SCL_ALU_CONTROL 0x4754 +#define SEA_mmSCL5_SCL_ALU_CONTROL 0x4a54 +#define SEA_mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define SEA_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define SEA_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1e55 +#define SEA_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define SEA_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 +#define SEA_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 +#define SEA_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4a55 +#define SEA_mmVIEWPORT_START 0x1b5c +#define SEA_mmSCL0_VIEWPORT_START 0x1b5c +#define SEA_mmSCL1_VIEWPORT_START 0x1e5c +#define SEA_mmSCL2_VIEWPORT_START 0x415c +#define SEA_mmSCL3_VIEWPORT_START 0x445c +#define SEA_mmSCL4_VIEWPORT_START 0x475c +#define SEA_mmSCL5_VIEWPORT_START 0x4a5c +#define SEA_mmVIEWPORT_SIZE 0x1b5d +#define SEA_mmSCL0_VIEWPORT_SIZE 0x1b5d +#define SEA_mmSCL1_VIEWPORT_SIZE 0x1e5d +#define SEA_mmSCL2_VIEWPORT_SIZE 0x415d +#define SEA_mmSCL3_VIEWPORT_SIZE 0x445d +#define SEA_mmSCL4_VIEWPORT_SIZE 0x475d +#define SEA_mmSCL5_VIEWPORT_SIZE 0x4a5d +#define SEA_mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define SEA_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define SEA_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1e5e +#define SEA_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415e +#define SEA_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445e +#define SEA_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475e +#define SEA_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4a5e +#define SEA_mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define SEA_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define SEA_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1e5f +#define SEA_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415f +#define SEA_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445f +#define SEA_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475f +#define SEA_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4a5f +#define SEA_mmSCL_MODE_CHANGE_DET1 0x1b60 +#define SEA_mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 +#define SEA_mmSCL1_SCL_MODE_CHANGE_DET1 0x1e60 +#define SEA_mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 +#define SEA_mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 +#define SEA_mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 +#define SEA_mmSCL5_SCL_MODE_CHANGE_DET1 0x4a60 +#define SEA_mmSCL_MODE_CHANGE_DET2 0x1b61 +#define SEA_mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 +#define SEA_mmSCL1_SCL_MODE_CHANGE_DET2 0x1e61 +#define SEA_mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 +#define SEA_mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 +#define SEA_mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 +#define SEA_mmSCL5_SCL_MODE_CHANGE_DET2 0x4a61 +#define SEA_mmSCL_MODE_CHANGE_DET3 0x1b62 +#define SEA_mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 +#define SEA_mmSCL1_SCL_MODE_CHANGE_DET3 0x1e62 +#define SEA_mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 +#define SEA_mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 +#define SEA_mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 +#define SEA_mmSCL5_SCL_MODE_CHANGE_DET3 0x4a62 +#define SEA_mmSCL_MODE_CHANGE_MASK 0x1b63 +#define SEA_mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 +#define SEA_mmSCL1_SCL_MODE_CHANGE_MASK 0x1e63 +#define SEA_mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 +#define SEA_mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 +#define SEA_mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 +#define SEA_mmSCL5_SCL_MODE_CHANGE_MASK 0x4a63 +#define SEA_mmSCL_DEBUG2 0x1b69 +#define SEA_mmSCL0_SCL_DEBUG2 0x1b69 +#define SEA_mmSCL1_SCL_DEBUG2 0x1e69 +#define SEA_mmSCL2_SCL_DEBUG2 0x4169 +#define SEA_mmSCL3_SCL_DEBUG2 0x4469 +#define SEA_mmSCL4_SCL_DEBUG2 0x4769 +#define SEA_mmSCL5_SCL_DEBUG2 0x4a69 +#define SEA_mmSCL_DEBUG 0x1b6a +#define SEA_mmSCL0_SCL_DEBUG 0x1b6a +#define SEA_mmSCL1_SCL_DEBUG 0x1e6a +#define SEA_mmSCL2_SCL_DEBUG 0x416a +#define SEA_mmSCL3_SCL_DEBUG 0x446a +#define SEA_mmSCL4_SCL_DEBUG 0x476a +#define SEA_mmSCL5_SCL_DEBUG 0x4a6a +#define SEA_mmSCL_TEST_DEBUG_INDEX 0x1b6b +#define SEA_mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b +#define SEA_mmSCL1_SCL_TEST_DEBUG_INDEX 0x1e6b +#define SEA_mmSCL2_SCL_TEST_DEBUG_INDEX 0x416b +#define SEA_mmSCL3_SCL_TEST_DEBUG_INDEX 0x446b +#define SEA_mmSCL4_SCL_TEST_DEBUG_INDEX 0x476b +#define SEA_mmSCL5_SCL_TEST_DEBUG_INDEX 0x4a6b +#define SEA_mmSCL_TEST_DEBUG_DATA 0x1b6c +#define SEA_mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c +#define SEA_mmSCL1_SCL_TEST_DEBUG_DATA 0x1e6c +#define SEA_mmSCL2_SCL_TEST_DEBUG_DATA 0x416c +#define SEA_mmSCL3_SCL_TEST_DEBUG_DATA 0x446c +#define SEA_mmSCL4_SCL_TEST_DEBUG_DATA 0x476c +#define SEA_mmSCL5_SCL_TEST_DEBUG_DATA 0x4a6c +#define SEA_mmGENMO_WT 0xf0 +#define SEA_mmGENMO_RD 0xf3 +#define SEA_mmGENENB 0xf0 +#define SEA_mmGENFC_WT 0xee +#define SEA_mmVGA0_GENFC_WT 0xee +#define SEA_mmVGA1_GENFC_WT 0xf6 +#define SEA_mmGENFC_RD 0xf2 +#define SEA_mmGENS0 0xf0 +#define SEA_mmGENS1 0xee +#define SEA_mmVGA0_GENS1 0xee +#define SEA_mmVGA1_GENS1 0xf6 +#define SEA_mmDAC_DATA 0xf2 +#define SEA_mmDAC_MASK 0xf1 +#define SEA_mmDAC_R_INDEX 0xf1 +#define SEA_mmDAC_W_INDEX 0xf2 +#define SEA_mmSEQ8_IDX 0xf1 +#define SEA_mmSEQ8_DATA 0xf1 +#define SEA_ixSEQ00 0x0 +#define SEA_ixSEQ01 0x1 +#define SEA_ixSEQ02 0x2 +#define SEA_ixSEQ03 0x3 +#define SEA_ixSEQ04 0x4 +#define SEA_mmCRTC8_IDX 0xed +#define SEA_mmVGA0_CRTC8_IDX 0xed +#define SEA_mmVGA1_CRTC8_IDX 0xf5 +#define SEA_mmCRTC8_DATA 0xed +#define SEA_mmVGA0_CRTC8_DATA 0xed +#define SEA_mmVGA1_CRTC8_DATA 0xf5 +#define SEA_ixCRT00 0x0 +#define SEA_ixCRT01 0x1 +#define SEA_ixCRT02 0x2 +#define SEA_ixCRT03 0x3 +#define SEA_ixCRT04 0x4 +#define SEA_ixCRT05 0x5 +#define SEA_ixCRT06 0x6 +#define SEA_ixCRT07 0x7 +#define SEA_ixCRT08 0x8 +#define SEA_ixCRT09 0x9 +#define SEA_ixCRT0A 0xa +#define SEA_ixCRT0B 0xb +#define SEA_ixCRT0C 0xc +#define SEA_ixCRT0D 0xd +#define SEA_ixCRT0E 0xe +#define SEA_ixCRT0F 0xf +#define SEA_ixCRT10 0x10 +#define SEA_ixCRT11 0x11 +#define SEA_ixCRT12 0x12 +#define SEA_ixCRT13 0x13 +#define SEA_ixCRT14 0x14 +#define SEA_ixCRT15 0x15 +#define SEA_ixCRT16 0x16 +#define SEA_ixCRT17 0x17 +#define SEA_ixCRT18 0x18 +#define SEA_ixCRT1E 0x1e +#define SEA_ixCRT1F 0x1f +#define SEA_ixCRT22 0x22 +#define SEA_mmGRPH8_IDX 0xf3 +#define SEA_mmGRPH8_DATA 0xf3 +#define SEA_ixGRA00 0x0 +#define SEA_ixGRA01 0x1 +#define SEA_ixGRA02 0x2 +#define SEA_ixGRA03 0x3 +#define SEA_ixGRA04 0x4 +#define SEA_ixGRA05 0x5 +#define SEA_ixGRA06 0x6 +#define SEA_ixGRA07 0x7 +#define SEA_ixGRA08 0x8 +#define SEA_mmATTRX 0xf0 +#define SEA_mmATTRDW 0xf0 +#define SEA_mmATTRDR 0xf0 +#define SEA_ixATTR00 0x0 +#define SEA_ixATTR01 0x1 +#define SEA_ixATTR02 0x2 +#define SEA_ixATTR03 0x3 +#define SEA_ixATTR04 0x4 +#define SEA_ixATTR05 0x5 +#define SEA_ixATTR06 0x6 +#define SEA_ixATTR07 0x7 +#define SEA_ixATTR08 0x8 +#define SEA_ixATTR09 0x9 +#define SEA_ixATTR0A 0xa +#define SEA_ixATTR0B 0xb +#define SEA_ixATTR0C 0xc +#define SEA_ixATTR0D 0xd +#define SEA_ixATTR0E 0xe +#define SEA_ixATTR0F 0xf +#define SEA_ixATTR10 0x10 +#define SEA_ixATTR11 0x11 +#define SEA_ixATTR12 0x12 +#define SEA_ixATTR13 0x13 +#define SEA_ixATTR14 0x14 +#define SEA_mmVGA_RENDER_CONTROL 0xc0 +#define SEA_mmVGA_SOURCE_SELECT 0xfc +#define SEA_mmVGA_SEQUENCER_RESET_CONTROL 0xc1 +#define SEA_mmVGA_MODE_CONTROL 0xc2 +#define SEA_mmVGA_SURFACE_PITCH_SELECT 0xc3 +#define SEA_mmVGA_MEMORY_BASE_ADDRESS 0xc4 +#define SEA_mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 +#define SEA_mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 +#define SEA_mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 +#define SEA_mmVGA_HDP_CONTROL 0xca +#define SEA_mmVGA_CACHE_CONTROL 0xcb +#define SEA_mmD1VGA_CONTROL 0xcc +#define SEA_mmD2VGA_CONTROL 0xce +#define SEA_mmD3VGA_CONTROL 0xf8 +#define SEA_mmD4VGA_CONTROL 0xf9 +#define SEA_mmD5VGA_CONTROL 0xfa +#define SEA_mmD6VGA_CONTROL 0xfb +#define SEA_mmVGA_HW_DEBUG 0xcf +#define SEA_mmVGA_STATUS 0xd0 +#define SEA_mmVGA_INTERRUPT_CONTROL 0xd1 +#define SEA_mmVGA_STATUS_CLEAR 0xd2 +#define SEA_mmVGA_INTERRUPT_STATUS 0xd3 +#define SEA_mmVGA_MAIN_CONTROL 0xd4 +#define SEA_mmVGA_TEST_CONTROL 0xd5 +#define SEA_mmVGA_DEBUG_READBACK_INDEX 0xd6 +#define SEA_mmVGA_DEBUG_READBACK_DATA 0xd7 +#define SEA_mmVGA_MEM_WRITE_PAGE_ADDR 0x12 +#define SEA_mmVGA_MEM_READ_PAGE_ADDR 0x13 +#define SEA_mmVGA_TEST_DEBUG_INDEX 0xc5 +#define SEA_mmVGA_TEST_DEBUG_DATA 0xc7 +#define SEA_ixVGADCC_DBG_DCCIF_C 0x7e +#define SEA_mmBPHYC_DAC_MACRO_CNTL 0x19fd +#define SEA_mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19fe +#define SEA_mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define SEA_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define SEA_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1e30 +#define SEA_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define SEA_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 +#define SEA_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 +#define SEA_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4a30 +#define SEA_mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define SEA_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define SEA_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1e31 +#define SEA_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define SEA_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 +#define SEA_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 +#define SEA_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4a31 +#define SEA_mmDPG_WATERMARK_MASK_CONTROL 0x1b32 +#define SEA_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 +#define SEA_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1e32 +#define SEA_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x4132 +#define SEA_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4432 +#define SEA_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4732 +#define SEA_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4a32 +#define SEA_mmDPG_PIPE_URGENCY_CONTROL 0x1b33 +#define SEA_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 +#define SEA_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1e33 +#define SEA_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define SEA_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 +#define SEA_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 +#define SEA_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4a33 +#define SEA_mmDPG_PIPE_DPM_CONTROL 0x1b34 +#define SEA_mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 +#define SEA_mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1e34 +#define SEA_mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 +#define SEA_mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 +#define SEA_mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 +#define SEA_mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4a34 +#define SEA_mmDPG_PIPE_STUTTER_CONTROL 0x1b35 +#define SEA_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 +#define SEA_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1e35 +#define SEA_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define SEA_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 +#define SEA_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 +#define SEA_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4a35 +#define SEA_mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define SEA_mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define SEA_mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1e36 +#define SEA_mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define SEA_mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 +#define SEA_mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define SEA_mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4a36 +#define SEA_mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define SEA_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define SEA_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1e37 +#define SEA_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define SEA_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 +#define SEA_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define SEA_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4a37 +#define SEA_mmDPG_REPEATER_PROGRAM 0x1b3a +#define SEA_mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a +#define SEA_mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1e3a +#define SEA_mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x413a +#define SEA_mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x443a +#define SEA_mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x473a +#define SEA_mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x4a3a +#define SEA_mmDPG_HW_DEBUG_A 0x1b3b +#define SEA_mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b +#define SEA_mmDMIF_PG1_DPG_HW_DEBUG_A 0x1e3b +#define SEA_mmDMIF_PG2_DPG_HW_DEBUG_A 0x413b +#define SEA_mmDMIF_PG3_DPG_HW_DEBUG_A 0x443b +#define SEA_mmDMIF_PG4_DPG_HW_DEBUG_A 0x473b +#define SEA_mmDMIF_PG5_DPG_HW_DEBUG_A 0x4a3b +#define SEA_mmDPG_HW_DEBUG_B 0x1b3c +#define SEA_mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c +#define SEA_mmDMIF_PG1_DPG_HW_DEBUG_B 0x1e3c +#define SEA_mmDMIF_PG2_DPG_HW_DEBUG_B 0x413c +#define SEA_mmDMIF_PG3_DPG_HW_DEBUG_B 0x443c +#define SEA_mmDMIF_PG4_DPG_HW_DEBUG_B 0x473c +#define SEA_mmDMIF_PG5_DPG_HW_DEBUG_B 0x4a3c +#define SEA_mmDPG_TEST_DEBUG_INDEX 0x1b38 +#define SEA_mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 +#define SEA_mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1e38 +#define SEA_mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 +#define SEA_mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 +#define SEA_mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 +#define SEA_mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4a38 +#define SEA_mmDPG_TEST_DEBUG_DATA 0x1b39 +#define SEA_mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 +#define SEA_mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1e39 +#define SEA_mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 +#define SEA_mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 +#define SEA_mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 +#define SEA_mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4a39 +#define SEA_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define SEA_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define SEA_ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 +#define SEA_ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 +#define SEA_ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define SEA_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17d2 +#define SEA_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17d3 +#define SEA_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17d5 +#define SEA_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17d6 +#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17d7 +#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17d8 +#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17d9 +#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17da +#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17db +#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17dc +#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17dd +#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17de +#define SEA_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17d4 +#define SEA_mmAZALIA_F0_CODEC_DEBUG 0x17df +#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET0 0x17e1 +#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET1 0x17e2 +#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET2 0x17e3 +#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET3 0x17e4 +#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET4 0x17e5 +#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET5 0x17e6 +#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET6 0x17e7 +#define SEA_mmGLOBAL_CAPABILITIES 0x0 +#define SEA_mmMINOR_VERSION 0x0 +#define SEA_mmMAJOR_VERSION 0x0 +#define SEA_mmOUTPUT_PAYLOAD_CAPABILITY 0x1 +#define SEA_mmINPUT_PAYLOAD_CAPABILITY 0x1 +#define SEA_mmGLOBAL_CONTROL 0x2 +#define SEA_mmWAKE_ENABLE 0x3 +#define SEA_mmSTATE_CHANGE_STATUS 0x3 +#define SEA_mmGLOBAL_STATUS 0x4 +#define SEA_mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define SEA_mmINTERRUPT_CONTROL 0x8 +#define SEA_mmINTERRUPT_STATUS 0x9 +#define SEA_mmWALL_CLOCK_COUNTER 0xc +#define SEA_mmSTREAM_SYNCHRONIZATION 0xe +#define SEA_mmCORB_LOWER_BASE_ADDRESS 0x10 +#define SEA_mmCORB_UPPER_BASE_ADDRESS 0x11 +#define SEA_mmCORB_WRITE_POINTER 0x12 +#define SEA_mmCORB_READ_POINTER 0x12 +#define SEA_mmCORB_CONTROL 0x13 +#define SEA_mmCORB_STATUS 0x13 +#define SEA_mmCORB_SIZE 0x13 +#define SEA_mmRIRB_LOWER_BASE_ADDRESS 0x14 +#define SEA_mmRIRB_UPPER_BASE_ADDRESS 0x15 +#define SEA_mmRIRB_WRITE_POINTER 0x16 +#define SEA_mmRESPONSE_INTERRUPT_COUNT 0x16 +#define SEA_mmRIRB_CONTROL 0x17 +#define SEA_mmRIRB_STATUS 0x17 +#define SEA_mmRIRB_SIZE 0x17 +#define SEA_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 +#define SEA_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define SEA_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define SEA_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 +#define SEA_mmIMMEDIATE_COMMAND_STATUS 0x1a +#define SEA_mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c +#define SEA_mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d +#define SEA_mmWALL_CLOCK_COUNTER_ALIAS 0x80c +#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 +#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 +#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 +#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 +#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 +#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 +#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 +#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 +#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 +#define SEA_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define SEA_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define SEA_ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define SEA_ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define SEA_ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define SEA_ixAUDIO_DESCRIPTOR0 0x1 +#define SEA_ixAUDIO_DESCRIPTOR1 0x2 +#define SEA_ixAUDIO_DESCRIPTOR2 0x3 +#define SEA_ixAUDIO_DESCRIPTOR3 0x4 +#define SEA_ixAUDIO_DESCRIPTOR4 0x5 +#define SEA_ixAUDIO_DESCRIPTOR5 0x6 +#define SEA_ixAUDIO_DESCRIPTOR6 0x7 +#define SEA_ixAUDIO_DESCRIPTOR7 0x8 +#define SEA_ixAUDIO_DESCRIPTOR8 0x9 +#define SEA_ixAUDIO_DESCRIPTOR9 0xa +#define SEA_ixAUDIO_DESCRIPTOR10 0xb +#define SEA_ixAUDIO_DESCRIPTOR11 0xc +#define SEA_ixAUDIO_DESCRIPTOR12 0xd +#define SEA_ixAUDIO_DESCRIPTOR13 0xe +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 +#define SEA_ixSINK_DESCRIPTION0 0x5 +#define SEA_ixSINK_DESCRIPTION1 0x6 +#define SEA_ixSINK_DESCRIPTION2 0x7 +#define SEA_ixSINK_DESCRIPTION3 0x8 +#define SEA_ixSINK_DESCRIPTION4 0x9 +#define SEA_ixSINK_DESCRIPTION5 0xa +#define SEA_ixSINK_DESCRIPTION6 0xb +#define SEA_ixSINK_DESCRIPTION7 0xc +#define SEA_ixSINK_DESCRIPTION8 0xd +#define SEA_ixSINK_DESCRIPTION9 0xe +#define SEA_ixSINK_DESCRIPTION10 0xf +#define SEA_ixSINK_DESCRIPTION11 0x10 +#define SEA_ixSINK_DESCRIPTION12 0x11 +#define SEA_ixSINK_DESCRIPTION13 0x12 +#define SEA_ixSINK_DESCRIPTION14 0x13 +#define SEA_ixSINK_DESCRIPTION15 0x14 +#define SEA_ixSINK_DESCRIPTION16 0x15 +#define SEA_ixSINK_DESCRIPTION17 0x16 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define SEA_ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define SEA_mmAZALIA_CONTROLLER_CLOCK_GATING 0x17b9 +#define SEA_mmAZALIA_AUDIO_DTO 0x17ba +#define SEA_mmAZALIA_AUDIO_DTO_CONTROL 0x17bb +#define SEA_mmAZALIA_SCLK_CONTROL 0x17bc +#define SEA_mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17bd +#define SEA_mmAZALIA_DATA_DMA_CONTROL 0x17be +#define SEA_mmAZALIA_BDL_DMA_CONTROL 0x17bf +#define SEA_mmAZALIA_RIRB_AND_DP_CONTROL 0x17c0 +#define SEA_mmAZALIA_CORB_DMA_CONTROL 0x17c1 +#define SEA_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17c9 +#define SEA_mmAZALIA_CYCLIC_BUFFER_SYNC 0x17ca +#define SEA_mmAZALIA_GLOBAL_CAPABILITIES 0x17cb +#define SEA_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17cc +#define SEA_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17cd +#define SEA_mmAZALIA_CONTROLLER_DEBUG 0x17cf +#define SEA_mmAZALIA_CRC0_CONTROL0 0x17ae +#define SEA_mmAZALIA_CRC0_CONTROL1 0x17af +#define SEA_mmAZALIA_CRC0_CONTROL2 0x17b0 +#define SEA_mmAZALIA_CRC0_CONTROL3 0x17b1 +#define SEA_mmAZALIA_CRC0_RESULT 0x17b2 +#define SEA_ixAZALIA_CRC0_CHANNEL0 0x0 +#define SEA_ixAZALIA_CRC0_CHANNEL1 0x1 +#define SEA_ixAZALIA_CRC0_CHANNEL2 0x2 +#define SEA_ixAZALIA_CRC0_CHANNEL3 0x3 +#define SEA_ixAZALIA_CRC0_CHANNEL4 0x4 +#define SEA_ixAZALIA_CRC0_CHANNEL5 0x5 +#define SEA_ixAZALIA_CRC0_CHANNEL6 0x6 +#define SEA_ixAZALIA_CRC0_CHANNEL7 0x7 +#define SEA_mmAZALIA_CRC1_CONTROL0 0x17b3 +#define SEA_mmAZALIA_CRC1_CONTROL1 0x17b4 +#define SEA_mmAZALIA_CRC1_CONTROL2 0x17b5 +#define SEA_mmAZALIA_CRC1_CONTROL3 0x17b6 +#define SEA_mmAZALIA_CRC1_RESULT 0x17b7 +#define SEA_ixAZALIA_CRC1_CHANNEL0 0x0 +#define SEA_ixAZALIA_CRC1_CHANNEL1 0x1 +#define SEA_ixAZALIA_CRC1_CHANNEL2 0x2 +#define SEA_ixAZALIA_CRC1_CHANNEL3 0x3 +#define SEA_ixAZALIA_CRC1_CHANNEL4 0x4 +#define SEA_ixAZALIA_CRC1_CHANNEL5 0x5 +#define SEA_ixAZALIA_CRC1_CHANNEL6 0x6 +#define SEA_ixAZALIA_CRC1_CHANNEL7 0x7 +#define SEA_mmAZ_TEST_DEBUG_INDEX 0x17d0 +#define SEA_mmAZ_TEST_DEBUG_DATA 0x17d1 +#define SEA_mmAZALIA_STREAM_INDEX 0x17e8 +#define SEA_mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17e8 +#define SEA_mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17ec +#define SEA_mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17f0 +#define SEA_mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17f4 +#define SEA_mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17f8 +#define SEA_mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17fc +#define SEA_mmAZALIA_STREAM_DATA 0x17e9 +#define SEA_mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17e9 +#define SEA_mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ed +#define SEA_mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17f1 +#define SEA_mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17f5 +#define SEA_mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17f9 +#define SEA_mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17fd +#define SEA_ixAZALIA_FIFO_SIZE_CONTROL 0x0 +#define SEA_ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 +#define SEA_ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 +#define SEA_ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 +#define SEA_ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 +#define SEA_ixAZALIA_STREAM_DEBUG 0x5 +#define SEA_mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define SEA_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define SEA_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 +#define SEA_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178c +#define SEA_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 +#define SEA_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 +#define SEA_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179e +#define SEA_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a4 +#define SEA_mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define SEA_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define SEA_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 +#define SEA_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178d +#define SEA_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 +#define SEA_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 +#define SEA_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179f +#define SEA_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a5 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd +#define SEA_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe +#define SEA_ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define SEA_ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 +#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a +#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b +#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c +#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d +#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e +#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f +#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 +#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 +#define SEA_ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 +#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 +#define SEA_mmBLND_CONTROL 0x1b6d +#define SEA_mmBLND0_BLND_CONTROL 0x1b6d +#define SEA_mmBLND1_BLND_CONTROL 0x1e6d +#define SEA_mmBLND2_BLND_CONTROL 0x416d +#define SEA_mmBLND3_BLND_CONTROL 0x446d +#define SEA_mmBLND4_BLND_CONTROL 0x476d +#define SEA_mmBLND5_BLND_CONTROL 0x4a6d +#define SEA_mmSM_CONTROL2 0x1b6e +#define SEA_mmBLND0_SM_CONTROL2 0x1b6e +#define SEA_mmBLND1_SM_CONTROL2 0x1e6e +#define SEA_mmBLND2_SM_CONTROL2 0x416e +#define SEA_mmBLND3_SM_CONTROL2 0x446e +#define SEA_mmBLND4_SM_CONTROL2 0x476e +#define SEA_mmBLND5_SM_CONTROL2 0x4a6e +#define SEA_mmPTI_CONTROL 0x1b6f +#define SEA_mmBLND0_PTI_CONTROL 0x1b6f +#define SEA_mmBLND1_PTI_CONTROL 0x1e6f +#define SEA_mmBLND2_PTI_CONTROL 0x416f +#define SEA_mmBLND3_PTI_CONTROL 0x446f +#define SEA_mmBLND4_PTI_CONTROL 0x476f +#define SEA_mmBLND5_PTI_CONTROL 0x4a6f +#define SEA_mmBLND_UPDATE 0x1b70 +#define SEA_mmBLND0_BLND_UPDATE 0x1b70 +#define SEA_mmBLND1_BLND_UPDATE 0x1e70 +#define SEA_mmBLND2_BLND_UPDATE 0x4170 +#define SEA_mmBLND3_BLND_UPDATE 0x4470 +#define SEA_mmBLND4_BLND_UPDATE 0x4770 +#define SEA_mmBLND5_BLND_UPDATE 0x4a70 +#define SEA_mmBLND_UNDERFLOW_INTERRUPT 0x1b71 +#define SEA_mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 +#define SEA_mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1e71 +#define SEA_mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x4171 +#define SEA_mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4471 +#define SEA_mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4771 +#define SEA_mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4a71 +#define SEA_mmBLND_V_UPDATE_LOCK 0x1b73 +#define SEA_mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 +#define SEA_mmBLND1_BLND_V_UPDATE_LOCK 0x1e73 +#define SEA_mmBLND2_BLND_V_UPDATE_LOCK 0x4173 +#define SEA_mmBLND3_BLND_V_UPDATE_LOCK 0x4473 +#define SEA_mmBLND4_BLND_V_UPDATE_LOCK 0x4773 +#define SEA_mmBLND5_BLND_V_UPDATE_LOCK 0x4a73 +#define SEA_mmBLND_REG_UPDATE_STATUS 0x1b77 +#define SEA_mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 +#define SEA_mmBLND1_BLND_REG_UPDATE_STATUS 0x1e77 +#define SEA_mmBLND2_BLND_REG_UPDATE_STATUS 0x4177 +#define SEA_mmBLND3_BLND_REG_UPDATE_STATUS 0x4477 +#define SEA_mmBLND4_BLND_REG_UPDATE_STATUS 0x4777 +#define SEA_mmBLND5_BLND_REG_UPDATE_STATUS 0x4a77 +#define SEA_mmBLND_DEBUG 0x1b74 +#define SEA_mmBLND0_BLND_DEBUG 0x1b74 +#define SEA_mmBLND1_BLND_DEBUG 0x1e74 +#define SEA_mmBLND2_BLND_DEBUG 0x4174 +#define SEA_mmBLND3_BLND_DEBUG 0x4474 +#define SEA_mmBLND4_BLND_DEBUG 0x4774 +#define SEA_mmBLND5_BLND_DEBUG 0x4a74 +#define SEA_mmBLND_TEST_DEBUG_INDEX 0x1b75 +#define SEA_mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 +#define SEA_mmBLND1_BLND_TEST_DEBUG_INDEX 0x1e75 +#define SEA_mmBLND2_BLND_TEST_DEBUG_INDEX 0x4175 +#define SEA_mmBLND3_BLND_TEST_DEBUG_INDEX 0x4475 +#define SEA_mmBLND4_BLND_TEST_DEBUG_INDEX 0x4775 +#define SEA_mmBLND5_BLND_TEST_DEBUG_INDEX 0x4a75 +#define SEA_mmBLND_TEST_DEBUG_DATA 0x1b76 +#define SEA_mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 +#define SEA_mmBLND1_BLND_TEST_DEBUG_DATA 0x1e76 +#define SEA_mmBLND2_BLND_TEST_DEBUG_DATA 0x4176 +#define SEA_mmBLND3_BLND_TEST_DEBUG_DATA 0x4476 +#define SEA_mmBLND4_BLND_TEST_DEBUG_DATA 0x4776 +#define SEA_mmBLND5_BLND_TEST_DEBUG_DATA 0x4a76 +#define SEA_mmSI_ENABLE 0x4c00 +#define SEA_mmSI_EC_CONFIG 0x4c01 +#define SEA_mmCNV_MODE 0x4c02 +#define SEA_mmCNV_WINDOW_START 0x4c03 +#define SEA_mmCNV_WINDOW_SIZE 0x4c04 +#define SEA_mmCNV_UPDATE 0x4c05 +#define SEA_mmCNV_SOURCE_SIZE 0x4c06 +#define SEA_mmCNV_CSC_CONTROL 0x4c07 +#define SEA_mmCNV_CSC_C11_C12 0x4c08 +#define SEA_mmCNV_CSC_C13_C14 0x4c09 +#define SEA_mmCNV_CSC_C21_C22 0x4c0a +#define SEA_mmCNV_CSC_C23_C24 0x4c0b +#define SEA_mmCNV_CSC_C31_C32 0x4c0c +#define SEA_mmCNV_CSC_C33_C34 0x4c0d +#define SEA_mmCNV_CSC_ROUND_OFFSET_R 0x4c0e +#define SEA_mmCNV_CSC_ROUND_OFFSET_G 0x4c0f +#define SEA_mmCNV_CSC_ROUND_OFFSET_B 0x4c10 +#define SEA_mmCNV_CSC_CLAMP_R 0x4c11 +#define SEA_mmCNV_CSC_CLAMP_G 0x4c12 +#define SEA_mmCNV_CSC_CLAMP_B 0x4c13 +#define SEA_mmCNV_TEST_CNTL 0x4c14 +#define SEA_mmCNV_TEST_CRC_RED 0x4c15 +#define SEA_mmCNV_TEST_CRC_GREEN 0x4c16 +#define SEA_mmCNV_TEST_CRC_BLUE 0x4c17 +#define SEA_mmSI_DEBUG_CTRL 0x4c18 +#define SEA_mmSI_DBG_MODE 0x4c1b +#define SEA_mmSI_HARD_DEBUG 0x4c1c +#define SEA_mmCNV_TEST_DEBUG_INDEX 0x4c19 +#define SEA_mmCNV_TEST_DEBUG_DATA 0x4c1a +#define SEA_mmSISCL_COEF_RAM_SELECT 0x4c20 +#define SEA_mmSISCL_COEF_RAM_TAP_DATA 0x4c21 +#define SEA_mmSISCL_MODE 0x4c22 +#define SEA_mmSISCL_TAP_CONTROL 0x4c23 +#define SEA_mmSISCL_DEST_SIZE 0x4c24 +#define SEA_mmSISCL_HORZ_FILTER_SCALE_RATIO 0x4c25 +#define SEA_mmSISCL_HORZ_FILTER_INIT_Y_RGB 0x4c26 +#define SEA_mmSISCL_HORZ_FILTER_INIT_CBCR 0x4c27 +#define SEA_mmSISCL_VERT_FILTER_SCALE_RATIO 0x4c28 +#define SEA_mmSISCL_VERT_FILTER_INIT_Y_RGB 0x4c29 +#define SEA_mmSISCL_VERT_FILTER_INIT_CBCR 0x4c2a +#define SEA_mmSISCL_ROUND_OFFSET 0x4c2b +#define SEA_mmSISCL_CLAMP 0x4c2c +#define SEA_mmSISCL_OVERFLOW_STATUS 0x4c2d +#define SEA_mmSISCL_COEF_RAM_CONFLICT_STATUS 0x4c2e +#define SEA_mmSISCL_OUTSIDE_PIX_STRATEGY 0x4c2f +#define SEA_mmSISCL_TEST_CNTL 0x4c30 +#define SEA_mmSISCL_TEST_CRC_RED 0x4c31 +#define SEA_mmSISCL_TEST_CRC_GREEN 0x4c32 +#define SEA_mmSISCL_TEST_CRC_BLUE 0x4c33 +#define SEA_mmSISCL_BACKPRESSURE_CNT_EN 0x4c36 +#define SEA_mmSISCL_MCIF_BACKPRESSURE_CNT 0x4c37 +#define SEA_mmSISCL_TEST_DEBUG_INDEX 0x4c34 +#define SEA_mmSISCL_TEST_DEBUG_DATA 0x4c35 +#define SEA_mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 +#define SEA_mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 +#define SEA_mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 +#define SEA_mmXDMA_INTERRUPT 0x3e3 +#define SEA_mmXDMA_CLOCK_GATING_CNTL 0x3e4 +#define SEA_mmXDMA_MEM_POWER_CNTL 0x3e6 +#define SEA_mmXDMA_IF_BIF_STATUS 0x3e7 +#define SEA_mmXDMA_PERF_MEAS_STATUS 0x3e8 +#define SEA_mmXDMA_IF_STATUS 0x3e9 +#define SEA_mmXDMA_TEST_DEBUG_INDEX 0x3ea +#define SEA_mmXDMA_TEST_DEBUG_DATA 0x3eb +#define SEA_mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 +#define SEA_mmXDMA_PG_CONTROL 0x3f9 +#define SEA_mmXDMA_PG_WDATA 0x3fa +#define SEA_mmXDMA_PG_STATUS 0x3fb +#define SEA_mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc +#define SEA_mmXDMA_AON_TEST_DEBUG_DATA 0x3fd + +#endif /* DCE_8_0_D_H */ diff --git a/headers/private/graphics/radeon_hd/vol_reg.h b/headers/private/graphics/radeon_hd/vol_reg.h new file mode 100644 index 0000000000..46e585f9d4 --- /dev/null +++ b/headers/private/graphics/radeon_hd/vol_reg.h @@ -0,0 +1,7350 @@ +/* + * DCE_10_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_10_0_D_H +#define DCE_10_0_D_H + +#define VOL_mmPIPE0_PG_CONFIG 0x2c0 +#define VOL_mmPIPE0_PG_ENABLE 0x2c1 +#define VOL_mmPIPE0_PG_STATUS 0x2c2 +#define VOL_mmPIPE1_PG_CONFIG 0x2c3 +#define VOL_mmPIPE1_PG_ENABLE 0x2c4 +#define VOL_mmPIPE1_PG_STATUS 0x2c5 +#define VOL_mmPIPE2_PG_CONFIG 0x2c6 +#define VOL_mmPIPE2_PG_ENABLE 0x2c7 +#define VOL_mmPIPE2_PG_STATUS 0x2c8 +#define VOL_mmPIPE3_PG_CONFIG 0x2c9 +#define VOL_mmPIPE3_PG_ENABLE 0x2ca +#define VOL_mmPIPE3_PG_STATUS 0x2cb +#define VOL_mmPIPE4_PG_CONFIG 0x2cc +#define VOL_mmPIPE4_PG_ENABLE 0x2cd +#define VOL_mmPIPE4_PG_STATUS 0x2ce +#define VOL_mmPIPE5_PG_CONFIG 0x2cf +#define VOL_mmPIPE5_PG_ENABLE 0x2d0 +#define VOL_mmPIPE5_PG_STATUS 0x2d1 +#define VOL_mmDC_IP_REQUEST_CNTL 0x2d2 +#define VOL_mmDC_PGFSM_CONFIG_REG 0x2d3 +#define VOL_mmDC_PGFSM_WRITE_REG 0x2d4 +#define VOL_mmDC_PGCNTL_STATUS_REG 0x2d5 +#define VOL_mmDCPG_TEST_DEBUG_INDEX 0x2d6 +#define VOL_mmDCPG_TEST_DEBUG_DATA 0x2d7 +#define VOL_mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define VOL_mmBL1_PWM_USER_LEVEL 0x1629 +#define VOL_mmBL1_PWM_TARGET_ABM_LEVEL 0x162a +#define VOL_mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b +#define VOL_mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c +#define VOL_mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d +#define VOL_mmBL1_PWM_ABM_CNTL 0x162e +#define VOL_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f +#define VOL_mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define VOL_mmDC_ABM1_CNTL 0x1638 +#define VOL_mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a +#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b +#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c +#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d +#define VOL_mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e +#define VOL_mmDC_ABM1_ACE_THRES_12 0x163f +#define VOL_mmDC_ABM1_ACE_THRES_34 0x1640 +#define VOL_mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define VOL_mmDC_ABM1_DEBUG_MISC 0x1649 +#define VOL_mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a +#define VOL_mmDC_ABM1_HG_MISC_CTRL 0x164b +#define VOL_mmDC_ABM1_LS_SUM_OF_LUMA 0x164c +#define VOL_mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d +#define VOL_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e +#define VOL_mmDC_ABM1_LS_PIXEL_COUNT 0x164f +#define VOL_mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define VOL_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define VOL_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define VOL_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define VOL_mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define VOL_mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define VOL_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define VOL_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define VOL_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define VOL_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define VOL_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a +#define VOL_mmDC_ABM1_HG_RESULT_1 0x165b +#define VOL_mmDC_ABM1_HG_RESULT_2 0x165c +#define VOL_mmDC_ABM1_HG_RESULT_3 0x165d +#define VOL_mmDC_ABM1_HG_RESULT_4 0x165e +#define VOL_mmDC_ABM1_HG_RESULT_5 0x165f +#define VOL_mmDC_ABM1_HG_RESULT_6 0x1660 +#define VOL_mmDC_ABM1_HG_RESULT_7 0x1661 +#define VOL_mmDC_ABM1_HG_RESULT_8 0x1662 +#define VOL_mmDC_ABM1_HG_RESULT_9 0x1663 +#define VOL_mmDC_ABM1_HG_RESULT_10 0x1664 +#define VOL_mmDC_ABM1_HG_RESULT_11 0x1665 +#define VOL_mmDC_ABM1_HG_RESULT_12 0x1666 +#define VOL_mmDC_ABM1_HG_RESULT_13 0x1667 +#define VOL_mmDC_ABM1_HG_RESULT_14 0x1668 +#define VOL_mmDC_ABM1_HG_RESULT_15 0x1669 +#define VOL_mmDC_ABM1_HG_RESULT_16 0x166a +#define VOL_mmDC_ABM1_HG_RESULT_17 0x166b +#define VOL_mmDC_ABM1_HG_RESULT_18 0x166c +#define VOL_mmDC_ABM1_HG_RESULT_19 0x166d +#define VOL_mmDC_ABM1_HG_RESULT_20 0x166e +#define VOL_mmDC_ABM1_HG_RESULT_21 0x166f +#define VOL_mmDC_ABM1_HG_RESULT_22 0x1670 +#define VOL_mmDC_ABM1_HG_RESULT_23 0x1671 +#define VOL_mmDC_ABM1_HG_RESULT_24 0x1672 +#define VOL_mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b +#define VOL_mmDC_ABM1_BL_MASTER_LOCK 0x169c +#define VOL_mmABM_TEST_DEBUG_INDEX 0x169e +#define VOL_mmABM_TEST_DEBUG_DATA 0x169f +#define VOL_mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c +#define VOL_mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c +#define VOL_mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1d7c +#define VOL_mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x1f7c +#define VOL_mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x417c +#define VOL_mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x437c +#define VOL_mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x457c +#define VOL_mmCRTC6_CRTC_DCFE_CLOCK_CONTROL 0x477c +#define VOL_mmCRTC_H_BLANK_EARLY_NUM 0x1b7d +#define VOL_mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d +#define VOL_mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d +#define VOL_mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d +#define VOL_mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d +#define VOL_mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d +#define VOL_mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d +#define VOL_mmCRTC6_CRTC_H_BLANK_EARLY_NUM 0x477d +#define VOL_mmDCFE_DBG_SEL 0x1b7e +#define VOL_mmCRTC0_DCFE_DBG_SEL 0x1b7e +#define VOL_mmCRTC1_DCFE_DBG_SEL 0x1d7e +#define VOL_mmCRTC2_DCFE_DBG_SEL 0x1f7e +#define VOL_mmCRTC3_DCFE_DBG_SEL 0x417e +#define VOL_mmCRTC4_DCFE_DBG_SEL 0x437e +#define VOL_mmCRTC5_DCFE_DBG_SEL 0x457e +#define VOL_mmCRTC6_DCFE_DBG_SEL 0x477e +#define VOL_mmDCFE_MEM_PWR_CTRL 0x1b7f +#define VOL_mmCRTC0_DCFE_MEM_PWR_CTRL 0x1b7f +#define VOL_mmCRTC1_DCFE_MEM_PWR_CTRL 0x1d7f +#define VOL_mmCRTC2_DCFE_MEM_PWR_CTRL 0x1f7f +#define VOL_mmCRTC3_DCFE_MEM_PWR_CTRL 0x417f +#define VOL_mmCRTC4_DCFE_MEM_PWR_CTRL 0x437f +#define VOL_mmCRTC5_DCFE_MEM_PWR_CTRL 0x457f +#define VOL_mmCRTC6_DCFE_MEM_PWR_CTRL 0x477f +#define VOL_mmDCFE_MEM_PWR_CTRL2 0x1bb8 +#define VOL_mmCRTC0_DCFE_MEM_PWR_CTRL2 0x1bb8 +#define VOL_mmCRTC1_DCFE_MEM_PWR_CTRL2 0x1db8 +#define VOL_mmCRTC2_DCFE_MEM_PWR_CTRL2 0x1fb8 +#define VOL_mmCRTC3_DCFE_MEM_PWR_CTRL2 0x41b8 +#define VOL_mmCRTC4_DCFE_MEM_PWR_CTRL2 0x43b8 +#define VOL_mmCRTC5_DCFE_MEM_PWR_CTRL2 0x45b8 +#define VOL_mmCRTC6_DCFE_MEM_PWR_CTRL2 0x47b8 +#define VOL_mmDCFE_MEM_PWR_STATUS 0x1bb9 +#define VOL_mmCRTC0_DCFE_MEM_PWR_STATUS 0x1bb9 +#define VOL_mmCRTC1_DCFE_MEM_PWR_STATUS 0x1db9 +#define VOL_mmCRTC2_DCFE_MEM_PWR_STATUS 0x1fb9 +#define VOL_mmCRTC3_DCFE_MEM_PWR_STATUS 0x41b9 +#define VOL_mmCRTC4_DCFE_MEM_PWR_STATUS 0x43b9 +#define VOL_mmCRTC5_DCFE_MEM_PWR_STATUS 0x45b9 +#define VOL_mmCRTC6_DCFE_MEM_PWR_STATUS 0x47b9 +#define VOL_mmCRTC_H_TOTAL 0x1b80 +#define VOL_mmCRTC0_CRTC_H_TOTAL 0x1b80 +#define VOL_mmCRTC1_CRTC_H_TOTAL 0x1d80 +#define VOL_mmCRTC2_CRTC_H_TOTAL 0x1f80 +#define VOL_mmCRTC3_CRTC_H_TOTAL 0x4180 +#define VOL_mmCRTC4_CRTC_H_TOTAL 0x4380 +#define VOL_mmCRTC5_CRTC_H_TOTAL 0x4580 +#define VOL_mmCRTC6_CRTC_H_TOTAL 0x4780 +#define VOL_mmCRTC_H_BLANK_START_END 0x1b81 +#define VOL_mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 +#define VOL_mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 +#define VOL_mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 +#define VOL_mmCRTC3_CRTC_H_BLANK_START_END 0x4181 +#define VOL_mmCRTC4_CRTC_H_BLANK_START_END 0x4381 +#define VOL_mmCRTC5_CRTC_H_BLANK_START_END 0x4581 +#define VOL_mmCRTC6_CRTC_H_BLANK_START_END 0x4781 +#define VOL_mmCRTC_H_SYNC_A 0x1b82 +#define VOL_mmCRTC0_CRTC_H_SYNC_A 0x1b82 +#define VOL_mmCRTC1_CRTC_H_SYNC_A 0x1d82 +#define VOL_mmCRTC2_CRTC_H_SYNC_A 0x1f82 +#define VOL_mmCRTC3_CRTC_H_SYNC_A 0x4182 +#define VOL_mmCRTC4_CRTC_H_SYNC_A 0x4382 +#define VOL_mmCRTC5_CRTC_H_SYNC_A 0x4582 +#define VOL_mmCRTC6_CRTC_H_SYNC_A 0x4782 +#define VOL_mmCRTC_H_SYNC_A_CNTL 0x1b83 +#define VOL_mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 +#define VOL_mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 +#define VOL_mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 +#define VOL_mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 +#define VOL_mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 +#define VOL_mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 +#define VOL_mmCRTC6_CRTC_H_SYNC_A_CNTL 0x4783 +#define VOL_mmCRTC_H_SYNC_B 0x1b84 +#define VOL_mmCRTC0_CRTC_H_SYNC_B 0x1b84 +#define VOL_mmCRTC1_CRTC_H_SYNC_B 0x1d84 +#define VOL_mmCRTC2_CRTC_H_SYNC_B 0x1f84 +#define VOL_mmCRTC3_CRTC_H_SYNC_B 0x4184 +#define VOL_mmCRTC4_CRTC_H_SYNC_B 0x4384 +#define VOL_mmCRTC5_CRTC_H_SYNC_B 0x4584 +#define VOL_mmCRTC6_CRTC_H_SYNC_B 0x4784 +#define VOL_mmCRTC_H_SYNC_B_CNTL 0x1b85 +#define VOL_mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 +#define VOL_mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 +#define VOL_mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 +#define VOL_mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 +#define VOL_mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 +#define VOL_mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 +#define VOL_mmCRTC6_CRTC_H_SYNC_B_CNTL 0x4785 +#define VOL_mmCRTC_VBI_END 0x1b86 +#define VOL_mmCRTC0_CRTC_VBI_END 0x1b86 +#define VOL_mmCRTC1_CRTC_VBI_END 0x1d86 +#define VOL_mmCRTC2_CRTC_VBI_END 0x1f86 +#define VOL_mmCRTC3_CRTC_VBI_END 0x4186 +#define VOL_mmCRTC4_CRTC_VBI_END 0x4386 +#define VOL_mmCRTC5_CRTC_VBI_END 0x4586 +#define VOL_mmCRTC6_CRTC_VBI_END 0x4786 +#define VOL_mmCRTC_V_TOTAL 0x1b87 +#define VOL_mmCRTC0_CRTC_V_TOTAL 0x1b87 +#define VOL_mmCRTC1_CRTC_V_TOTAL 0x1d87 +#define VOL_mmCRTC2_CRTC_V_TOTAL 0x1f87 +#define VOL_mmCRTC3_CRTC_V_TOTAL 0x4187 +#define VOL_mmCRTC4_CRTC_V_TOTAL 0x4387 +#define VOL_mmCRTC5_CRTC_V_TOTAL 0x4587 +#define VOL_mmCRTC6_CRTC_V_TOTAL 0x4787 +#define VOL_mmCRTC_V_TOTAL_MIN 0x1b88 +#define VOL_mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 +#define VOL_mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 +#define VOL_mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 +#define VOL_mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 +#define VOL_mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 +#define VOL_mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 +#define VOL_mmCRTC6_CRTC_V_TOTAL_MIN 0x4788 +#define VOL_mmCRTC_V_TOTAL_MAX 0x1b89 +#define VOL_mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 +#define VOL_mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 +#define VOL_mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 +#define VOL_mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 +#define VOL_mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 +#define VOL_mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 +#define VOL_mmCRTC6_CRTC_V_TOTAL_MAX 0x4789 +#define VOL_mmCRTC_V_TOTAL_CONTROL 0x1b8a +#define VOL_mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a +#define VOL_mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a +#define VOL_mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a +#define VOL_mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a +#define VOL_mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a +#define VOL_mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a +#define VOL_mmCRTC6_CRTC_V_TOTAL_CONTROL 0x478a +#define VOL_mmCRTC_V_TOTAL_INT_STATUS 0x1b8b +#define VOL_mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b +#define VOL_mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b +#define VOL_mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b +#define VOL_mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b +#define VOL_mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b +#define VOL_mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b +#define VOL_mmCRTC6_CRTC_V_TOTAL_INT_STATUS 0x478b +#define VOL_mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define VOL_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define VOL_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c +#define VOL_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c +#define VOL_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c +#define VOL_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c +#define VOL_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c +#define VOL_mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS 0x478c +#define VOL_mmCRTC_V_BLANK_START_END 0x1b8d +#define VOL_mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d +#define VOL_mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d +#define VOL_mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d +#define VOL_mmCRTC3_CRTC_V_BLANK_START_END 0x418d +#define VOL_mmCRTC4_CRTC_V_BLANK_START_END 0x438d +#define VOL_mmCRTC5_CRTC_V_BLANK_START_END 0x458d +#define VOL_mmCRTC6_CRTC_V_BLANK_START_END 0x478d +#define VOL_mmCRTC_V_SYNC_A 0x1b8e +#define VOL_mmCRTC0_CRTC_V_SYNC_A 0x1b8e +#define VOL_mmCRTC1_CRTC_V_SYNC_A 0x1d8e +#define VOL_mmCRTC2_CRTC_V_SYNC_A 0x1f8e +#define VOL_mmCRTC3_CRTC_V_SYNC_A 0x418e +#define VOL_mmCRTC4_CRTC_V_SYNC_A 0x438e +#define VOL_mmCRTC5_CRTC_V_SYNC_A 0x458e +#define VOL_mmCRTC6_CRTC_V_SYNC_A 0x478e +#define VOL_mmCRTC_V_SYNC_A_CNTL 0x1b8f +#define VOL_mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f +#define VOL_mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f +#define VOL_mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f +#define VOL_mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f +#define VOL_mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f +#define VOL_mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f +#define VOL_mmCRTC6_CRTC_V_SYNC_A_CNTL 0x478f +#define VOL_mmCRTC_V_SYNC_B 0x1b90 +#define VOL_mmCRTC0_CRTC_V_SYNC_B 0x1b90 +#define VOL_mmCRTC1_CRTC_V_SYNC_B 0x1d90 +#define VOL_mmCRTC2_CRTC_V_SYNC_B 0x1f90 +#define VOL_mmCRTC3_CRTC_V_SYNC_B 0x4190 +#define VOL_mmCRTC4_CRTC_V_SYNC_B 0x4390 +#define VOL_mmCRTC5_CRTC_V_SYNC_B 0x4590 +#define VOL_mmCRTC6_CRTC_V_SYNC_B 0x4790 +#define VOL_mmCRTC_V_SYNC_B_CNTL 0x1b91 +#define VOL_mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 +#define VOL_mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 +#define VOL_mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 +#define VOL_mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 +#define VOL_mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 +#define VOL_mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 +#define VOL_mmCRTC6_CRTC_V_SYNC_B_CNTL 0x4791 +#define VOL_mmCRTC_DTMTEST_CNTL 0x1b92 +#define VOL_mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 +#define VOL_mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 +#define VOL_mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 +#define VOL_mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 +#define VOL_mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 +#define VOL_mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 +#define VOL_mmCRTC6_CRTC_DTMTEST_CNTL 0x4792 +#define VOL_mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define VOL_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define VOL_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 +#define VOL_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 +#define VOL_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define VOL_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 +#define VOL_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 +#define VOL_mmCRTC6_CRTC_DTMTEST_STATUS_POSITION 0x4793 +#define VOL_mmCRTC_TRIGA_CNTL 0x1b94 +#define VOL_mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 +#define VOL_mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 +#define VOL_mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 +#define VOL_mmCRTC3_CRTC_TRIGA_CNTL 0x4194 +#define VOL_mmCRTC4_CRTC_TRIGA_CNTL 0x4394 +#define VOL_mmCRTC5_CRTC_TRIGA_CNTL 0x4594 +#define VOL_mmCRTC6_CRTC_TRIGA_CNTL 0x4794 +#define VOL_mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define VOL_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define VOL_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 +#define VOL_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 +#define VOL_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define VOL_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 +#define VOL_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 +#define VOL_mmCRTC6_CRTC_TRIGA_MANUAL_TRIG 0x4795 +#define VOL_mmCRTC_TRIGB_CNTL 0x1b96 +#define VOL_mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 +#define VOL_mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 +#define VOL_mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 +#define VOL_mmCRTC3_CRTC_TRIGB_CNTL 0x4196 +#define VOL_mmCRTC4_CRTC_TRIGB_CNTL 0x4396 +#define VOL_mmCRTC5_CRTC_TRIGB_CNTL 0x4596 +#define VOL_mmCRTC6_CRTC_TRIGB_CNTL 0x4796 +#define VOL_mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define VOL_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define VOL_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 +#define VOL_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 +#define VOL_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define VOL_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 +#define VOL_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 +#define VOL_mmCRTC6_CRTC_TRIGB_MANUAL_TRIG 0x4797 +#define VOL_mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define VOL_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define VOL_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 +#define VOL_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 +#define VOL_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define VOL_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 +#define VOL_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 +#define VOL_mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 +#define VOL_mmCRTC_FLOW_CONTROL 0x1b99 +#define VOL_mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 +#define VOL_mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 +#define VOL_mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 +#define VOL_mmCRTC3_CRTC_FLOW_CONTROL 0x4199 +#define VOL_mmCRTC4_CRTC_FLOW_CONTROL 0x4399 +#define VOL_mmCRTC5_CRTC_FLOW_CONTROL 0x4599 +#define VOL_mmCRTC6_CRTC_FLOW_CONTROL 0x4799 +#define VOL_mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define VOL_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define VOL_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a +#define VOL_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a +#define VOL_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a +#define VOL_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a +#define VOL_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a +#define VOL_mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE 0x479a +#define VOL_mmCRTC_AVSYNC_COUNTER 0x1b9b +#define VOL_mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b +#define VOL_mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b +#define VOL_mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b +#define VOL_mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b +#define VOL_mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b +#define VOL_mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b +#define VOL_mmCRTC6_CRTC_AVSYNC_COUNTER 0x479b +#define VOL_mmCRTC_CONTROL 0x1b9c +#define VOL_mmCRTC0_CRTC_CONTROL 0x1b9c +#define VOL_mmCRTC1_CRTC_CONTROL 0x1d9c +#define VOL_mmCRTC2_CRTC_CONTROL 0x1f9c +#define VOL_mmCRTC3_CRTC_CONTROL 0x419c +#define VOL_mmCRTC4_CRTC_CONTROL 0x439c +#define VOL_mmCRTC5_CRTC_CONTROL 0x459c +#define VOL_mmCRTC6_CRTC_CONTROL 0x479c +#define VOL_mmCRTC_BLANK_CONTROL 0x1b9d +#define VOL_mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d +#define VOL_mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d +#define VOL_mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d +#define VOL_mmCRTC3_CRTC_BLANK_CONTROL 0x419d +#define VOL_mmCRTC4_CRTC_BLANK_CONTROL 0x439d +#define VOL_mmCRTC5_CRTC_BLANK_CONTROL 0x459d +#define VOL_mmCRTC6_CRTC_BLANK_CONTROL 0x479d +#define VOL_mmCRTC_INTERLACE_CONTROL 0x1b9e +#define VOL_mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e +#define VOL_mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e +#define VOL_mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e +#define VOL_mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e +#define VOL_mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e +#define VOL_mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e +#define VOL_mmCRTC6_CRTC_INTERLACE_CONTROL 0x479e +#define VOL_mmCRTC_INTERLACE_STATUS 0x1b9f +#define VOL_mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f +#define VOL_mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f +#define VOL_mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f +#define VOL_mmCRTC3_CRTC_INTERLACE_STATUS 0x419f +#define VOL_mmCRTC4_CRTC_INTERLACE_STATUS 0x439f +#define VOL_mmCRTC5_CRTC_INTERLACE_STATUS 0x459f +#define VOL_mmCRTC6_CRTC_INTERLACE_STATUS 0x479f +#define VOL_mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define VOL_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define VOL_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 +#define VOL_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 +#define VOL_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 +#define VOL_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 +#define VOL_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 +#define VOL_mmCRTC6_CRTC_FIELD_INDICATION_CONTROL 0x47a0 +#define VOL_mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define VOL_mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define VOL_mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 +#define VOL_mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 +#define VOL_mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 +#define VOL_mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 +#define VOL_mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 +#define VOL_mmCRTC6_CRTC_PIXEL_DATA_READBACK0 0x47a1 +#define VOL_mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define VOL_mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define VOL_mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 +#define VOL_mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 +#define VOL_mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 +#define VOL_mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 +#define VOL_mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 +#define VOL_mmCRTC6_CRTC_PIXEL_DATA_READBACK1 0x47a2 +#define VOL_mmCRTC_STATUS 0x1ba3 +#define VOL_mmCRTC0_CRTC_STATUS 0x1ba3 +#define VOL_mmCRTC1_CRTC_STATUS 0x1da3 +#define VOL_mmCRTC2_CRTC_STATUS 0x1fa3 +#define VOL_mmCRTC3_CRTC_STATUS 0x41a3 +#define VOL_mmCRTC4_CRTC_STATUS 0x43a3 +#define VOL_mmCRTC5_CRTC_STATUS 0x45a3 +#define VOL_mmCRTC6_CRTC_STATUS 0x47a3 +#define VOL_mmCRTC_STATUS_POSITION 0x1ba4 +#define VOL_mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 +#define VOL_mmCRTC1_CRTC_STATUS_POSITION 0x1da4 +#define VOL_mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 +#define VOL_mmCRTC3_CRTC_STATUS_POSITION 0x41a4 +#define VOL_mmCRTC4_CRTC_STATUS_POSITION 0x43a4 +#define VOL_mmCRTC5_CRTC_STATUS_POSITION 0x45a4 +#define VOL_mmCRTC6_CRTC_STATUS_POSITION 0x47a4 +#define VOL_mmCRTC_NOM_VERT_POSITION 0x1ba5 +#define VOL_mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 +#define VOL_mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 +#define VOL_mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 +#define VOL_mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 +#define VOL_mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 +#define VOL_mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 +#define VOL_mmCRTC6_CRTC_NOM_VERT_POSITION 0x47a5 +#define VOL_mmCRTC_STATUS_FRAME_COUNT 0x1ba6 +#define VOL_mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 +#define VOL_mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 +#define VOL_mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 +#define VOL_mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 +#define VOL_mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 +#define VOL_mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 +#define VOL_mmCRTC6_CRTC_STATUS_FRAME_COUNT 0x47a6 +#define VOL_mmCRTC_STATUS_VF_COUNT 0x1ba7 +#define VOL_mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 +#define VOL_mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 +#define VOL_mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 +#define VOL_mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 +#define VOL_mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 +#define VOL_mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 +#define VOL_mmCRTC6_CRTC_STATUS_VF_COUNT 0x47a7 +#define VOL_mmCRTC_STATUS_HV_COUNT 0x1ba8 +#define VOL_mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 +#define VOL_mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 +#define VOL_mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 +#define VOL_mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 +#define VOL_mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 +#define VOL_mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 +#define VOL_mmCRTC6_CRTC_STATUS_HV_COUNT 0x47a8 +#define VOL_mmCRTC_COUNT_CONTROL 0x1ba9 +#define VOL_mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 +#define VOL_mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 +#define VOL_mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 +#define VOL_mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 +#define VOL_mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 +#define VOL_mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 +#define VOL_mmCRTC6_CRTC_COUNT_CONTROL 0x47a9 +#define VOL_mmCRTC_COUNT_RESET 0x1baa +#define VOL_mmCRTC0_CRTC_COUNT_RESET 0x1baa +#define VOL_mmCRTC1_CRTC_COUNT_RESET 0x1daa +#define VOL_mmCRTC2_CRTC_COUNT_RESET 0x1faa +#define VOL_mmCRTC3_CRTC_COUNT_RESET 0x41aa +#define VOL_mmCRTC4_CRTC_COUNT_RESET 0x43aa +#define VOL_mmCRTC5_CRTC_COUNT_RESET 0x45aa +#define VOL_mmCRTC6_CRTC_COUNT_RESET 0x47aa +#define VOL_mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define VOL_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define VOL_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab +#define VOL_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab +#define VOL_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab +#define VOL_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab +#define VOL_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab +#define VOL_mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab +#define VOL_mmCRTC_VERT_SYNC_CONTROL 0x1bac +#define VOL_mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac +#define VOL_mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac +#define VOL_mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac +#define VOL_mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac +#define VOL_mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac +#define VOL_mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac +#define VOL_mmCRTC6_CRTC_VERT_SYNC_CONTROL 0x47ac +#define VOL_mmCRTC_STEREO_STATUS 0x1bad +#define VOL_mmCRTC0_CRTC_STEREO_STATUS 0x1bad +#define VOL_mmCRTC1_CRTC_STEREO_STATUS 0x1dad +#define VOL_mmCRTC2_CRTC_STEREO_STATUS 0x1fad +#define VOL_mmCRTC3_CRTC_STEREO_STATUS 0x41ad +#define VOL_mmCRTC4_CRTC_STEREO_STATUS 0x43ad +#define VOL_mmCRTC5_CRTC_STEREO_STATUS 0x45ad +#define VOL_mmCRTC6_CRTC_STEREO_STATUS 0x47ad +#define VOL_mmCRTC_STEREO_CONTROL 0x1bae +#define VOL_mmCRTC0_CRTC_STEREO_CONTROL 0x1bae +#define VOL_mmCRTC1_CRTC_STEREO_CONTROL 0x1dae +#define VOL_mmCRTC2_CRTC_STEREO_CONTROL 0x1fae +#define VOL_mmCRTC3_CRTC_STEREO_CONTROL 0x41ae +#define VOL_mmCRTC4_CRTC_STEREO_CONTROL 0x43ae +#define VOL_mmCRTC5_CRTC_STEREO_CONTROL 0x45ae +#define VOL_mmCRTC6_CRTC_STEREO_CONTROL 0x47ae +#define VOL_mmCRTC_SNAPSHOT_STATUS 0x1baf +#define VOL_mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf +#define VOL_mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf +#define VOL_mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf +#define VOL_mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af +#define VOL_mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af +#define VOL_mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af +#define VOL_mmCRTC6_CRTC_SNAPSHOT_STATUS 0x47af +#define VOL_mmCRTC_SNAPSHOT_CONTROL 0x1bb0 +#define VOL_mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 +#define VOL_mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 +#define VOL_mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 +#define VOL_mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 +#define VOL_mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 +#define VOL_mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 +#define VOL_mmCRTC6_CRTC_SNAPSHOT_CONTROL 0x47b0 +#define VOL_mmCRTC_SNAPSHOT_POSITION 0x1bb1 +#define VOL_mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 +#define VOL_mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 +#define VOL_mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 +#define VOL_mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 +#define VOL_mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 +#define VOL_mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 +#define VOL_mmCRTC6_CRTC_SNAPSHOT_POSITION 0x47b1 +#define VOL_mmCRTC_SNAPSHOT_FRAME 0x1bb2 +#define VOL_mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 +#define VOL_mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 +#define VOL_mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 +#define VOL_mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 +#define VOL_mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 +#define VOL_mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 +#define VOL_mmCRTC6_CRTC_SNAPSHOT_FRAME 0x47b2 +#define VOL_mmCRTC_START_LINE_CONTROL 0x1bb3 +#define VOL_mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 +#define VOL_mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 +#define VOL_mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 +#define VOL_mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 +#define VOL_mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 +#define VOL_mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 +#define VOL_mmCRTC6_CRTC_START_LINE_CONTROL 0x47b3 +#define VOL_mmCRTC_INTERRUPT_CONTROL 0x1bb4 +#define VOL_mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 +#define VOL_mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 +#define VOL_mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 +#define VOL_mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 +#define VOL_mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 +#define VOL_mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 +#define VOL_mmCRTC6_CRTC_INTERRUPT_CONTROL 0x47b4 +#define VOL_mmCRTC_UPDATE_LOCK 0x1bb5 +#define VOL_mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 +#define VOL_mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 +#define VOL_mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 +#define VOL_mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 +#define VOL_mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 +#define VOL_mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 +#define VOL_mmCRTC6_CRTC_UPDATE_LOCK 0x47b5 +#define VOL_mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define VOL_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define VOL_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 +#define VOL_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 +#define VOL_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 +#define VOL_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 +#define VOL_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 +#define VOL_mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6 +#define VOL_mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define VOL_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define VOL_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 +#define VOL_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 +#define VOL_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 +#define VOL_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 +#define VOL_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 +#define VOL_mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7 +#define VOL_mmCRTC_TEST_PATTERN_CONTROL 0x1bba +#define VOL_mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba +#define VOL_mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba +#define VOL_mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba +#define VOL_mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba +#define VOL_mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba +#define VOL_mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba +#define VOL_mmCRTC6_CRTC_TEST_PATTERN_CONTROL 0x47ba +#define VOL_mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define VOL_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define VOL_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb +#define VOL_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb +#define VOL_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb +#define VOL_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb +#define VOL_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb +#define VOL_mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS 0x47bb +#define VOL_mmCRTC_TEST_PATTERN_COLOR 0x1bbc +#define VOL_mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc +#define VOL_mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc +#define VOL_mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc +#define VOL_mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc +#define VOL_mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc +#define VOL_mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc +#define VOL_mmCRTC6_CRTC_TEST_PATTERN_COLOR 0x47bc +#define VOL_mmMASTER_UPDATE_LOCK 0x1bbd +#define VOL_mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd +#define VOL_mmCRTC1_MASTER_UPDATE_LOCK 0x1dbd +#define VOL_mmCRTC2_MASTER_UPDATE_LOCK 0x1fbd +#define VOL_mmCRTC3_MASTER_UPDATE_LOCK 0x41bd +#define VOL_mmCRTC4_MASTER_UPDATE_LOCK 0x43bd +#define VOL_mmCRTC5_MASTER_UPDATE_LOCK 0x45bd +#define VOL_mmCRTC6_MASTER_UPDATE_LOCK 0x47bd +#define VOL_mmMASTER_UPDATE_MODE 0x1bbe +#define VOL_mmCRTC0_MASTER_UPDATE_MODE 0x1bbe +#define VOL_mmCRTC1_MASTER_UPDATE_MODE 0x1dbe +#define VOL_mmCRTC2_MASTER_UPDATE_MODE 0x1fbe +#define VOL_mmCRTC3_MASTER_UPDATE_MODE 0x41be +#define VOL_mmCRTC4_MASTER_UPDATE_MODE 0x43be +#define VOL_mmCRTC5_MASTER_UPDATE_MODE 0x45be +#define VOL_mmCRTC6_MASTER_UPDATE_MODE 0x47be +#define VOL_mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define VOL_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define VOL_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf +#define VOL_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf +#define VOL_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf +#define VOL_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf +#define VOL_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf +#define VOL_mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf +#define VOL_mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define VOL_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define VOL_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 +#define VOL_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 +#define VOL_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 +#define VOL_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 +#define VOL_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 +#define VOL_mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 +#define VOL_mmCRTC_MVP_STATUS 0x1bc1 +#define VOL_mmCRTC0_CRTC_MVP_STATUS 0x1bc1 +#define VOL_mmCRTC1_CRTC_MVP_STATUS 0x1dc1 +#define VOL_mmCRTC2_CRTC_MVP_STATUS 0x1fc1 +#define VOL_mmCRTC3_CRTC_MVP_STATUS 0x41c1 +#define VOL_mmCRTC4_CRTC_MVP_STATUS 0x43c1 +#define VOL_mmCRTC5_CRTC_MVP_STATUS 0x45c1 +#define VOL_mmCRTC6_CRTC_MVP_STATUS 0x47c1 +#define VOL_mmCRTC_MASTER_EN 0x1bc2 +#define VOL_mmCRTC0_CRTC_MASTER_EN 0x1bc2 +#define VOL_mmCRTC1_CRTC_MASTER_EN 0x1dc2 +#define VOL_mmCRTC2_CRTC_MASTER_EN 0x1fc2 +#define VOL_mmCRTC3_CRTC_MASTER_EN 0x41c2 +#define VOL_mmCRTC4_CRTC_MASTER_EN 0x43c2 +#define VOL_mmCRTC5_CRTC_MASTER_EN 0x45c2 +#define VOL_mmCRTC6_CRTC_MASTER_EN 0x47c2 +#define VOL_mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define VOL_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define VOL_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 +#define VOL_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 +#define VOL_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 +#define VOL_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 +#define VOL_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 +#define VOL_mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3 +#define VOL_mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define VOL_mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define VOL_mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 +#define VOL_mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 +#define VOL_mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 +#define VOL_mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 +#define VOL_mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 +#define VOL_mmCRTC6_CRTC_V_UPDATE_INT_STATUS 0x47c4 +#define VOL_mmCRTC_OVERSCAN_COLOR 0x1bc8 +#define VOL_mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 +#define VOL_mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 +#define VOL_mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 +#define VOL_mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 +#define VOL_mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 +#define VOL_mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 +#define VOL_mmCRTC6_CRTC_OVERSCAN_COLOR 0x47c8 +#define VOL_mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define VOL_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define VOL_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 +#define VOL_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 +#define VOL_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 +#define VOL_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 +#define VOL_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 +#define VOL_mmCRTC6_CRTC_OVERSCAN_COLOR_EXT 0x47c9 +#define VOL_mmCRTC_BLANK_DATA_COLOR 0x1bca +#define VOL_mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca +#define VOL_mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca +#define VOL_mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca +#define VOL_mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca +#define VOL_mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca +#define VOL_mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca +#define VOL_mmCRTC6_CRTC_BLANK_DATA_COLOR 0x47ca +#define VOL_mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define VOL_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define VOL_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb +#define VOL_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb +#define VOL_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb +#define VOL_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb +#define VOL_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb +#define VOL_mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT 0x47cb +#define VOL_mmCRTC_BLACK_COLOR 0x1bcc +#define VOL_mmCRTC0_CRTC_BLACK_COLOR 0x1bcc +#define VOL_mmCRTC1_CRTC_BLACK_COLOR 0x1dcc +#define VOL_mmCRTC2_CRTC_BLACK_COLOR 0x1fcc +#define VOL_mmCRTC3_CRTC_BLACK_COLOR 0x41cc +#define VOL_mmCRTC4_CRTC_BLACK_COLOR 0x43cc +#define VOL_mmCRTC5_CRTC_BLACK_COLOR 0x45cc +#define VOL_mmCRTC6_CRTC_BLACK_COLOR 0x47cc +#define VOL_mmCRTC_BLACK_COLOR_EXT 0x1bcd +#define VOL_mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd +#define VOL_mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd +#define VOL_mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd +#define VOL_mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd +#define VOL_mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd +#define VOL_mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd +#define VOL_mmCRTC6_CRTC_BLACK_COLOR_EXT 0x47cd +#define VOL_mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce +#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce +#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce +#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce +#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce +#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce +#define VOL_mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf +#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf +#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf +#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf +#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf +#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf +#define VOL_mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 +#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 +#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 +#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 +#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 +#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0 +#define VOL_mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 +#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 +#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 +#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 +#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 +#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1 +#define VOL_mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 +#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 +#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 +#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 +#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 +#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2 +#define VOL_mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define VOL_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define VOL_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 +#define VOL_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 +#define VOL_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 +#define VOL_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 +#define VOL_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 +#define VOL_mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3 +#define VOL_mmCRTC_CRC_CNTL 0x1bd4 +#define VOL_mmCRTC0_CRTC_CRC_CNTL 0x1bd4 +#define VOL_mmCRTC1_CRTC_CRC_CNTL 0x1dd4 +#define VOL_mmCRTC2_CRTC_CRC_CNTL 0x1fd4 +#define VOL_mmCRTC3_CRTC_CRC_CNTL 0x41d4 +#define VOL_mmCRTC4_CRTC_CRC_CNTL 0x43d4 +#define VOL_mmCRTC5_CRTC_CRC_CNTL 0x45d4 +#define VOL_mmCRTC6_CRTC_CRC_CNTL 0x47d4 +#define VOL_mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define VOL_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define VOL_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 +#define VOL_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 +#define VOL_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 +#define VOL_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 +#define VOL_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 +#define VOL_mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5 +#define VOL_mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define VOL_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define VOL_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 +#define VOL_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 +#define VOL_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 +#define VOL_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 +#define VOL_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 +#define VOL_mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6 +#define VOL_mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define VOL_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define VOL_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 +#define VOL_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 +#define VOL_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 +#define VOL_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 +#define VOL_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 +#define VOL_mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7 +#define VOL_mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define VOL_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define VOL_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 +#define VOL_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 +#define VOL_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 +#define VOL_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 +#define VOL_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 +#define VOL_mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8 +#define VOL_mmCRTC_CRC0_DATA_RG 0x1bd9 +#define VOL_mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 +#define VOL_mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 +#define VOL_mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 +#define VOL_mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 +#define VOL_mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 +#define VOL_mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 +#define VOL_mmCRTC6_CRTC_CRC0_DATA_RG 0x47d9 +#define VOL_mmCRTC_CRC0_DATA_B 0x1bda +#define VOL_mmCRTC0_CRTC_CRC0_DATA_B 0x1bda +#define VOL_mmCRTC1_CRTC_CRC0_DATA_B 0x1dda +#define VOL_mmCRTC2_CRTC_CRC0_DATA_B 0x1fda +#define VOL_mmCRTC3_CRTC_CRC0_DATA_B 0x41da +#define VOL_mmCRTC4_CRTC_CRC0_DATA_B 0x43da +#define VOL_mmCRTC5_CRTC_CRC0_DATA_B 0x45da +#define VOL_mmCRTC6_CRTC_CRC0_DATA_B 0x47da +#define VOL_mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define VOL_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define VOL_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb +#define VOL_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb +#define VOL_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db +#define VOL_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db +#define VOL_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db +#define VOL_mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db +#define VOL_mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define VOL_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define VOL_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc +#define VOL_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc +#define VOL_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc +#define VOL_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc +#define VOL_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc +#define VOL_mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc +#define VOL_mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define VOL_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define VOL_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd +#define VOL_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd +#define VOL_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd +#define VOL_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd +#define VOL_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd +#define VOL_mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd +#define VOL_mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define VOL_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define VOL_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde +#define VOL_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde +#define VOL_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de +#define VOL_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de +#define VOL_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de +#define VOL_mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de +#define VOL_mmCRTC_CRC1_DATA_RG 0x1bdf +#define VOL_mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf +#define VOL_mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf +#define VOL_mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf +#define VOL_mmCRTC3_CRTC_CRC1_DATA_RG 0x41df +#define VOL_mmCRTC4_CRTC_CRC1_DATA_RG 0x43df +#define VOL_mmCRTC5_CRTC_CRC1_DATA_RG 0x45df +#define VOL_mmCRTC6_CRTC_CRC1_DATA_RG 0x47df +#define VOL_mmCRTC_CRC1_DATA_B 0x1be0 +#define VOL_mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 +#define VOL_mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 +#define VOL_mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 +#define VOL_mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 +#define VOL_mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 +#define VOL_mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 +#define VOL_mmCRTC6_CRTC_CRC1_DATA_B 0x47e0 +#define VOL_mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1de1 +#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x1fe1 +#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 +#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x43e1 +#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x45e1 +#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1 +#define VOL_mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1de2 +#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1fe2 +#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 +#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x43e2 +#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x45e2 +#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2 +#define VOL_mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1de3 +#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1fe3 +#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 +#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x43e3 +#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x45e3 +#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3 +#define VOL_mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1de4 +#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1fe4 +#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 +#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x43e4 +#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x45e4 +#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4 +#define VOL_mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1de5 +#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1fe5 +#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 +#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x43e5 +#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x45e5 +#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5 +#define VOL_mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define VOL_mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define VOL_mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1de6 +#define VOL_mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1fe6 +#define VOL_mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 +#define VOL_mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x43e6 +#define VOL_mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x45e6 +#define VOL_mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6 +#define VOL_mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define VOL_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define VOL_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 +#define VOL_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 +#define VOL_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 +#define VOL_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 +#define VOL_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 +#define VOL_mmCRTC6_CRTC_STATIC_SCREEN_CONTROL 0x47e7 +#define VOL_mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define VOL_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define VOL_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 +#define VOL_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 +#define VOL_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define VOL_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 +#define VOL_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 +#define VOL_mmCRTC6_CRTC_3D_STRUCTURE_CONTROL 0x4778 +#define VOL_mmCRTC_GSL_VSYNC_GAP 0x1b79 +#define VOL_mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 +#define VOL_mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 +#define VOL_mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 +#define VOL_mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 +#define VOL_mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 +#define VOL_mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 +#define VOL_mmCRTC6_CRTC_GSL_VSYNC_GAP 0x4779 +#define VOL_mmCRTC_GSL_WINDOW 0x1b7a +#define VOL_mmCRTC0_CRTC_GSL_WINDOW 0x1b7a +#define VOL_mmCRTC1_CRTC_GSL_WINDOW 0x1d7a +#define VOL_mmCRTC2_CRTC_GSL_WINDOW 0x1f7a +#define VOL_mmCRTC3_CRTC_GSL_WINDOW 0x417a +#define VOL_mmCRTC4_CRTC_GSL_WINDOW 0x437a +#define VOL_mmCRTC5_CRTC_GSL_WINDOW 0x457a +#define VOL_mmCRTC6_CRTC_GSL_WINDOW 0x477a +#define VOL_mmCRTC_GSL_CONTROL 0x1b7b +#define VOL_mmCRTC0_CRTC_GSL_CONTROL 0x1b7b +#define VOL_mmCRTC1_CRTC_GSL_CONTROL 0x1d7b +#define VOL_mmCRTC2_CRTC_GSL_CONTROL 0x1f7b +#define VOL_mmCRTC3_CRTC_GSL_CONTROL 0x417b +#define VOL_mmCRTC4_CRTC_GSL_CONTROL 0x437b +#define VOL_mmCRTC5_CRTC_GSL_CONTROL 0x457b +#define VOL_mmCRTC6_CRTC_GSL_CONTROL 0x477b +#define VOL_mmCRTC_TEST_DEBUG_INDEX 0x1bc6 +#define VOL_mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 +#define VOL_mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 +#define VOL_mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 +#define VOL_mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 +#define VOL_mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 +#define VOL_mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 +#define VOL_mmCRTC6_CRTC_TEST_DEBUG_INDEX 0x47c6 +#define VOL_mmCRTC_TEST_DEBUG_DATA 0x1bc7 +#define VOL_mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 +#define VOL_mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 +#define VOL_mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 +#define VOL_mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 +#define VOL_mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 +#define VOL_mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 +#define VOL_mmCRTC6_CRTC_TEST_DEBUG_DATA 0x47c7 +#define VOL_mmDAC_ENABLE 0x16aa +#define VOL_mmDAC_SOURCE_SELECT 0x16ab +#define VOL_mmDAC_CRC_EN 0x16ac +#define VOL_mmDAC_CRC_CONTROL 0x16ad +#define VOL_mmDAC_CRC_SIG_RGB_MASK 0x16ae +#define VOL_mmDAC_CRC_SIG_CONTROL_MASK 0x16af +#define VOL_mmDAC_CRC_SIG_RGB 0x16b0 +#define VOL_mmDAC_CRC_SIG_CONTROL 0x16b1 +#define VOL_mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 +#define VOL_mmDAC_STEREOSYNC_SELECT 0x16b3 +#define VOL_mmDAC_AUTODETECT_CONTROL 0x16b4 +#define VOL_mmDAC_AUTODETECT_CONTROL2 0x16b5 +#define VOL_mmDAC_AUTODETECT_CONTROL3 0x16b6 +#define VOL_mmDAC_AUTODETECT_STATUS 0x16b7 +#define VOL_mmDAC_AUTODETECT_INT_CONTROL 0x16b8 +#define VOL_mmDAC_FORCE_OUTPUT_CNTL 0x16b9 +#define VOL_mmDAC_FORCE_DATA 0x16ba +#define VOL_mmDAC_POWERDOWN 0x16bb +#define VOL_mmDAC_CONTROL 0x16bc +#define VOL_mmDAC_COMPARATOR_ENABLE 0x16bd +#define VOL_mmDAC_COMPARATOR_OUTPUT 0x16be +#define VOL_mmDAC_PWR_CNTL 0x16bf +#define VOL_mmDAC_DFT_CONFIG 0x16c0 +#define VOL_mmDAC_FIFO_STATUS 0x16c1 +#define VOL_mmDAC_TEST_DEBUG_INDEX 0x16c2 +#define VOL_mmDAC_TEST_DEBUG_DATA 0x16c3 +#define VOL_mmPERFCOUNTER_CNTL 0x170 +#define VOL_mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 +#define VOL_mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364 +#define VOL_mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8 +#define VOL_mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24 +#define VOL_mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24 +#define VOL_mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24 +#define VOL_mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124 +#define VOL_mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324 +#define VOL_mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524 +#define VOL_mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724 +#define VOL_mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0 +#define VOL_mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68 +#define VOL_mmPERFCOUNTER_STATE 0x171 +#define VOL_mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 +#define VOL_mmDC_PERFMON1_PERFCOUNTER_STATE 0x365 +#define VOL_mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9 +#define VOL_mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25 +#define VOL_mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25 +#define VOL_mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25 +#define VOL_mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125 +#define VOL_mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325 +#define VOL_mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525 +#define VOL_mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725 +#define VOL_mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1 +#define VOL_mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69 +#define VOL_mmPERFMON_CNTL 0x173 +#define VOL_mmDC_PERFMON0_PERFMON_CNTL 0x173 +#define VOL_mmDC_PERFMON1_PERFMON_CNTL 0x367 +#define VOL_mmDC_PERFMON2_PERFMON_CNTL 0x18cb +#define VOL_mmDC_PERFMON3_PERFMON_CNTL 0x1b27 +#define VOL_mmDC_PERFMON4_PERFMON_CNTL 0x1d27 +#define VOL_mmDC_PERFMON5_PERFMON_CNTL 0x1f27 +#define VOL_mmDC_PERFMON6_PERFMON_CNTL 0x4127 +#define VOL_mmDC_PERFMON7_PERFMON_CNTL 0x4327 +#define VOL_mmDC_PERFMON8_PERFMON_CNTL 0x4527 +#define VOL_mmDC_PERFMON9_PERFMON_CNTL 0x4727 +#define VOL_mmDC_PERFMON10_PERFMON_CNTL 0x59a3 +#define VOL_mmDC_PERFMON11_PERFMON_CNTL 0x5f6b +#define VOL_mmPERFMON_CNTL2 0x17a +#define VOL_mmDC_PERFMON0_PERFMON_CNTL2 0x17a +#define VOL_mmDC_PERFMON1_PERFMON_CNTL2 0x36e +#define VOL_mmDC_PERFMON2_PERFMON_CNTL2 0x18d2 +#define VOL_mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e +#define VOL_mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e +#define VOL_mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e +#define VOL_mmDC_PERFMON6_PERFMON_CNTL2 0x412e +#define VOL_mmDC_PERFMON7_PERFMON_CNTL2 0x432e +#define VOL_mmDC_PERFMON8_PERFMON_CNTL2 0x452e +#define VOL_mmDC_PERFMON9_PERFMON_CNTL2 0x472e +#define VOL_mmDC_PERFMON10_PERFMON_CNTL2 0x59aa +#define VOL_mmDC_PERFMON11_PERFMON_CNTL2 0x5f72 +#define VOL_mmPERFMON_CVALUE_INT_MISC 0x172 +#define VOL_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 +#define VOL_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366 +#define VOL_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca +#define VOL_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26 +#define VOL_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26 +#define VOL_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26 +#define VOL_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126 +#define VOL_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326 +#define VOL_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526 +#define VOL_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726 +#define VOL_mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2 +#define VOL_mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a +#define VOL_mmPERFMON_CVALUE_LOW 0x174 +#define VOL_mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 +#define VOL_mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368 +#define VOL_mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc +#define VOL_mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28 +#define VOL_mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28 +#define VOL_mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28 +#define VOL_mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128 +#define VOL_mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328 +#define VOL_mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528 +#define VOL_mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728 +#define VOL_mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4 +#define VOL_mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c +#define VOL_mmPERFMON_HI 0x175 +#define VOL_mmDC_PERFMON0_PERFMON_HI 0x175 +#define VOL_mmDC_PERFMON1_PERFMON_HI 0x369 +#define VOL_mmDC_PERFMON2_PERFMON_HI 0x18cd +#define VOL_mmDC_PERFMON3_PERFMON_HI 0x1b29 +#define VOL_mmDC_PERFMON4_PERFMON_HI 0x1d29 +#define VOL_mmDC_PERFMON5_PERFMON_HI 0x1f29 +#define VOL_mmDC_PERFMON6_PERFMON_HI 0x4129 +#define VOL_mmDC_PERFMON7_PERFMON_HI 0x4329 +#define VOL_mmDC_PERFMON8_PERFMON_HI 0x4529 +#define VOL_mmDC_PERFMON9_PERFMON_HI 0x4729 +#define VOL_mmDC_PERFMON10_PERFMON_HI 0x59a5 +#define VOL_mmDC_PERFMON11_PERFMON_HI 0x5f6d +#define VOL_mmPERFMON_LOW 0x176 +#define VOL_mmDC_PERFMON0_PERFMON_LOW 0x176 +#define VOL_mmDC_PERFMON1_PERFMON_LOW 0x36a +#define VOL_mmDC_PERFMON2_PERFMON_LOW 0x18ce +#define VOL_mmDC_PERFMON3_PERFMON_LOW 0x1b2a +#define VOL_mmDC_PERFMON4_PERFMON_LOW 0x1d2a +#define VOL_mmDC_PERFMON5_PERFMON_LOW 0x1f2a +#define VOL_mmDC_PERFMON6_PERFMON_LOW 0x412a +#define VOL_mmDC_PERFMON7_PERFMON_LOW 0x432a +#define VOL_mmDC_PERFMON8_PERFMON_LOW 0x452a +#define VOL_mmDC_PERFMON9_PERFMON_LOW 0x472a +#define VOL_mmDC_PERFMON10_PERFMON_LOW 0x59a6 +#define VOL_mmDC_PERFMON11_PERFMON_LOW 0x5f6e +#define VOL_mmPERFMON_TEST_DEBUG_INDEX 0x177 +#define VOL_mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 +#define VOL_mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b +#define VOL_mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf +#define VOL_mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b +#define VOL_mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b +#define VOL_mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b +#define VOL_mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b +#define VOL_mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b +#define VOL_mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b +#define VOL_mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b +#define VOL_mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7 +#define VOL_mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f +#define VOL_mmPERFMON_TEST_DEBUG_DATA 0x178 +#define VOL_mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 +#define VOL_mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c +#define VOL_mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0 +#define VOL_mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c +#define VOL_mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c +#define VOL_mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c +#define VOL_mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c +#define VOL_mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c +#define VOL_mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c +#define VOL_mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c +#define VOL_mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8 +#define VOL_mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70 +#define VOL_mmREFCLK_CNTL 0x109 +#define VOL_mmDCCG_CBUS_WRCMD_DELAY 0x110 +#define VOL_mmDPREFCLK_CNTL 0x118 +#define VOL_mmAVSYNC_COUNTER_WRITE 0x12a +#define VOL_mmAVSYNC_COUNTER_CONTROL 0x12b +#define VOL_mmAVSYNC_COUNTER_READ 0x12f +#define VOL_mmDCCG_GTC_CNTL 0x120 +#define VOL_mmDCCG_GTC_DTO_INCR 0x121 +#define VOL_mmDCCG_GTC_DTO_MODULO 0x122 +#define VOL_mmDCCG_GTC_CURRENT 0x123 +#define VOL_mmDCCG_DS_DTO_INCR 0x113 +#define VOL_mmDCCG_DS_DTO_MODULO 0x114 +#define VOL_mmDCCG_DS_CNTL 0x115 +#define VOL_mmDCCG_DS_HW_CAL_INTERVAL 0x116 +#define VOL_mmDCCG_DS_DEBUG_CNTL 0x112 +#define VOL_mmDMCU_SMU_INTERRUPT_CNTL 0x12c +#define VOL_mmSMU_CONTROL 0x12d +#define VOL_mmSMU_INTERRUPT_CONTROL 0x12e +#define VOL_mmDAC_CLK_ENABLE 0x128 +#define VOL_mmDVO_CLK_ENABLE 0x129 +#define VOL_mmDCCG_GATE_DISABLE_CNTL 0x134 +#define VOL_mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 +#define VOL_mmSCLK_CGTT_BLK_CTRL_REG 0x136 +#define VOL_mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 +#define VOL_mmREFCLK_CGTT_BLK_CTRL_REG 0x10b +#define VOL_mmDCCG_CAC_STATUS 0x137 +#define VOL_mmPIXCLK1_RESYNC_CNTL 0x138 +#define VOL_mmPIXCLK2_RESYNC_CNTL 0x139 +#define VOL_mmPIXCLK0_RESYNC_CNTL 0x13a +#define VOL_mmMICROSECOND_TIME_BASE_DIV 0x13b +#define VOL_mmDCCG_DISP_CNTL_REG 0x13f +#define VOL_mmMILLISECOND_TIME_BASE_DIV 0x130 +#define VOL_mmDISPCLK_FREQ_CHANGE_CNTL 0x131 +#define VOL_mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 +#define VOL_mmDCCG_PERFMON_CNTL 0x133 +#define VOL_mmDCCG_PERFMON_CNTL2 0x10e +#define VOL_mmCRTC0_PIXEL_RATE_CNTL 0x140 +#define VOL_mmDP_DTO0_PHASE 0x141 +#define VOL_mmDP_DTO0_MODULO 0x142 +#define VOL_mmCRTC1_PIXEL_RATE_CNTL 0x144 +#define VOL_mmDP_DTO1_PHASE 0x145 +#define VOL_mmDP_DTO1_MODULO 0x146 +#define VOL_mmCRTC2_PIXEL_RATE_CNTL 0x148 +#define VOL_mmDP_DTO2_PHASE 0x149 +#define VOL_mmDP_DTO2_MODULO 0x14a +#define VOL_mmCRTC3_PIXEL_RATE_CNTL 0x14c +#define VOL_mmDP_DTO3_PHASE 0x14d +#define VOL_mmDP_DTO3_MODULO 0x14e +#define VOL_mmCRTC4_PIXEL_RATE_CNTL 0x150 +#define VOL_mmDP_DTO4_PHASE 0x151 +#define VOL_mmDP_DTO4_MODULO 0x152 +#define VOL_mmCRTC5_PIXEL_RATE_CNTL 0x154 +#define VOL_mmDP_DTO5_PHASE 0x155 +#define VOL_mmDP_DTO5_MODULO 0x156 +#define VOL_mmDCCG_SOFT_RESET 0x15f +#define VOL_mmSYMCLKA_CLOCK_ENABLE 0x160 +#define VOL_mmSYMCLKB_CLOCK_ENABLE 0x161 +#define VOL_mmSYMCLKC_CLOCK_ENABLE 0x162 +#define VOL_mmSYMCLKD_CLOCK_ENABLE 0x163 +#define VOL_mmSYMCLKE_CLOCK_ENABLE 0x164 +#define VOL_mmSYMCLKF_CLOCK_ENABLE 0x165 +#define VOL_mmDPDBG_CLK_FORCE_CONTROL 0x10d +#define VOL_mmDVOACLKD_CNTL 0x168 +#define VOL_mmDVOACLKC_MVP_CNTL 0x169 +#define VOL_mmDVOACLKC_CNTL 0x16a +#define VOL_mmDCCG_AUDIO_DTO_SOURCE 0x16b +#define VOL_mmDCCG_AUDIO_DTO0_PHASE 0x16c +#define VOL_mmDCCG_AUDIO_DTO0_MODULE 0x16d +#define VOL_mmDCCG_AUDIO_DTO1_PHASE 0x16e +#define VOL_mmDCCG_AUDIO_DTO1_MODULE 0x16f +#define VOL_mmDCCG_TEST_DEBUG_INDEX 0x17c +#define VOL_mmDCCG_TEST_DEBUG_DATA 0x17d +#define VOL_mmDCCG_TEST_CLK_SEL 0x17e +#define VOL_mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 +#define VOL_mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 +#define VOL_mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 +#define VOL_mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 +#define VOL_mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 +#define VOL_mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 +#define VOL_mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa +#define VOL_mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb +#define VOL_mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc +#define VOL_mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd +#define VOL_mmCPLL_MACRO_CNTL_RESERVED10 0x5fda +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe +#define VOL_mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define VOL_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define VOL_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 +#define VOL_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 +#define VOL_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff +#define VOL_mmPLL_MACRO_CNTL_RESERVED0 0x1700 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 +#define VOL_mmPLL_MACRO_CNTL_RESERVED1 0x1701 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 +#define VOL_mmPLL_MACRO_CNTL_RESERVED2 0x1702 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 +#define VOL_mmPLL_MACRO_CNTL_RESERVED3 0x1703 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 +#define VOL_mmPLL_MACRO_CNTL_RESERVED4 0x1704 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 +#define VOL_mmPLL_MACRO_CNTL_RESERVED5 0x1705 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 +#define VOL_mmPLL_MACRO_CNTL_RESERVED6 0x1706 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a +#define VOL_mmPLL_MACRO_CNTL_RESERVED7 0x1707 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b +#define VOL_mmPLL_MACRO_CNTL_RESERVED8 0x1708 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c +#define VOL_mmPLL_MACRO_CNTL_RESERVED9 0x1709 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d +#define VOL_mmPLL_MACRO_CNTL_RESERVED10 0x170a +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e +#define VOL_mmPLL_MACRO_CNTL_RESERVED11 0x170b +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f +#define VOL_mmPLL_MACRO_CNTL_RESERVED12 0x170c +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 +#define VOL_mmPLL_MACRO_CNTL_RESERVED13 0x170d +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 +#define VOL_mmPLL_MACRO_CNTL_RESERVED14 0x170e +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 +#define VOL_mmPLL_MACRO_CNTL_RESERVED15 0x170f +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 +#define VOL_mmPLL_MACRO_CNTL_RESERVED16 0x1710 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 +#define VOL_mmPLL_MACRO_CNTL_RESERVED17 0x1711 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 +#define VOL_mmPLL_MACRO_CNTL_RESERVED18 0x1712 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 +#define VOL_mmPLL_MACRO_CNTL_RESERVED19 0x1713 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 +#define VOL_mmPLL_MACRO_CNTL_RESERVED20 0x1714 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 +#define VOL_mmPLL_MACRO_CNTL_RESERVED21 0x1715 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 +#define VOL_mmPLL_MACRO_CNTL_RESERVED22 0x1716 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a +#define VOL_mmPLL_MACRO_CNTL_RESERVED23 0x1717 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b +#define VOL_mmPLL_MACRO_CNTL_RESERVED24 0x1718 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c +#define VOL_mmPLL_MACRO_CNTL_RESERVED25 0x1719 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d +#define VOL_mmPLL_MACRO_CNTL_RESERVED26 0x171a +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e +#define VOL_mmPLL_MACRO_CNTL_RESERVED27 0x171b +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f +#define VOL_mmPLL_MACRO_CNTL_RESERVED28 0x171c +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 +#define VOL_mmPLL_MACRO_CNTL_RESERVED29 0x171d +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 +#define VOL_mmPLL_MACRO_CNTL_RESERVED30 0x171e +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 +#define VOL_mmPLL_MACRO_CNTL_RESERVED31 0x171f +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 +#define VOL_mmPLL_MACRO_CNTL_RESERVED32 0x1720 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 +#define VOL_mmPLL_MACRO_CNTL_RESERVED33 0x1721 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 +#define VOL_mmPLL_MACRO_CNTL_RESERVED34 0x1722 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 +#define VOL_mmPLL_MACRO_CNTL_RESERVED35 0x1723 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 +#define VOL_mmPLL_MACRO_CNTL_RESERVED36 0x1724 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 +#define VOL_mmPLL_MACRO_CNTL_RESERVED37 0x1725 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 +#define VOL_mmPLL_MACRO_CNTL_RESERVED38 0x1726 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a +#define VOL_mmPLL_MACRO_CNTL_RESERVED39 0x1727 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b +#define VOL_mmPLL_MACRO_CNTL_RESERVED40 0x1728 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c +#define VOL_mmPLL_MACRO_CNTL_RESERVED41 0x1729 +#define VOL_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 +#define VOL_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 +#define VOL_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d +#define VOL_mmDENTIST_DISPCLK_CNTL 0x124 +#define VOL_mmDCDEBUG_BUS_CLK1_SEL 0x16c4 +#define VOL_mmDCDEBUG_BUS_CLK2_SEL 0x16c5 +#define VOL_mmDCDEBUG_BUS_CLK3_SEL 0x16c6 +#define VOL_mmDCDEBUG_BUS_CLK4_SEL 0x16c7 +#define VOL_mmDCDEBUG_BUS_CLK5_SEL 0x16c8 +#define VOL_mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 +#define VOL_mmDCDEBUG_OUT_CNTL 0x16ca +#define VOL_mmDCDEBUG_OUT_DATA 0x16cb +#define VOL_mmDMIF_ADDR_CONFIG 0x2f5 +#define VOL_mmDMIF_CONTROL 0x2f6 +#define VOL_mmDMIF_STATUS 0x2f7 +#define VOL_mmDMIF_HW_DEBUG 0x2f8 +#define VOL_mmDMIF_ARBITRATION_CONTROL 0x2f9 +#define VOL_mmPIPE0_ARBITRATION_CONTROL3 0x2fa +#define VOL_mmPIPE1_ARBITRATION_CONTROL3 0x2fb +#define VOL_mmPIPE2_ARBITRATION_CONTROL3 0x2fc +#define VOL_mmPIPE3_ARBITRATION_CONTROL3 0x2fd +#define VOL_mmPIPE4_ARBITRATION_CONTROL3 0x2fe +#define VOL_mmPIPE5_ARBITRATION_CONTROL3 0x2ff +#define VOL_mmPIPE6_ARBITRATION_CONTROL3 0x32a +#define VOL_mmPIPE7_ARBITRATION_CONTROL3 0x32b +#define VOL_mmDMIF_P_VMID 0x300 +#define VOL_mmDMIF_URG_OVERRIDE 0x329 +#define VOL_mmDMIF_TEST_DEBUG_INDEX 0x301 +#define VOL_mmDMIF_TEST_DEBUG_DATA 0x302 +#define VOL_ixDMIF_DEBUG02_CORE0 0x2 +#define VOL_ixDMIF_DEBUG02_CORE1 0xa +#define VOL_mmDMIF_ADDR_CALC 0x303 +#define VOL_mmDMIF_STATUS2 0x304 +#define VOL_mmPIPE0_MAX_REQUESTS 0x305 +#define VOL_mmPIPE1_MAX_REQUESTS 0x306 +#define VOL_mmPIPE2_MAX_REQUESTS 0x307 +#define VOL_mmPIPE3_MAX_REQUESTS 0x308 +#define VOL_mmPIPE4_MAX_REQUESTS 0x309 +#define VOL_mmPIPE5_MAX_REQUESTS 0x30a +#define VOL_mmPIPE6_MAX_REQUESTS 0x32c +#define VOL_mmPIPE7_MAX_REQUESTS 0x32d +#define VOL_mmLOW_POWER_TILING_CONTROL 0x30b +#define VOL_mmMCIF_CONTROL 0x30c +#define VOL_mmMCIF_WRITE_COMBINE_CONTROL 0x30d +#define VOL_mmMCIF_TEST_DEBUG_INDEX 0x30e +#define VOL_mmMCIF_TEST_DEBUG_DATA 0x30f +#define VOL_ixIDDCCIF02_DBG_DCCIF_C 0x9 +#define VOL_ixIDDCCIF04_DBG_DCCIF_E 0xb +#define VOL_ixIDDCCIF05_DBG_DCCIF_F 0xc +#define VOL_mmMCIF_VMID 0x310 +#define VOL_mmMCIF_MEM_CONTROL 0x311 +#define VOL_mmCC_DC_PIPE_DIS 0x312 +#define VOL_mmMC_DC_INTERFACE_NACK_STATUS 0x313 +#define VOL_mmRBBMIF_TIMEOUT 0x314 +#define VOL_mmRBBMIF_STATUS 0x315 +#define VOL_mmRBBMIF_TIMEOUT_DIS 0x316 +#define VOL_mmRBBMIF_STATUS_FLAG 0x327 +#define VOL_mmDCI_MEM_PWR_STATUS 0x317 +#define VOL_mmDCI_MEM_PWR_STATUS2 0x318 +#define VOL_mmDCI_CLK_CNTL 0x319 +#define VOL_mmDCI_MEM_PWR_CNTL 0x31b +#define VOL_mmDCI_MEM_PWR_CNTL2 0x31c +#define VOL_mmDCI_MEM_PWR_CNTL3 0x31d +#define VOL_mmDCI_SOFT_RESET 0x328 +#define VOL_mmDCI_TEST_DEBUG_INDEX 0x31e +#define VOL_mmDCI_TEST_DEBUG_DATA 0x31f +#define VOL_mmDCI_DEBUG_CONFIG 0x320 +#define VOL_mmPIPE0_DMIF_BUFFER_CONTROL 0x321 +#define VOL_mmPIPE1_DMIF_BUFFER_CONTROL 0x322 +#define VOL_mmPIPE2_DMIF_BUFFER_CONTROL 0x323 +#define VOL_mmPIPE3_DMIF_BUFFER_CONTROL 0x324 +#define VOL_mmPIPE4_DMIF_BUFFER_CONTROL 0x325 +#define VOL_mmPIPE5_DMIF_BUFFER_CONTROL 0x326 +#define VOL_mmDC_GENERICA 0x4800 +#define VOL_mmDC_GENERICB 0x4801 +#define VOL_mmDC_PAD_EXTERN_SIG 0x4802 +#define VOL_mmDC_REF_CLK_CNTL 0x4803 +#define VOL_mmDC_GPIO_DEBUG 0x4804 +#define VOL_mmUNIPHYA_LINK_CNTL 0x4805 +#define VOL_mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 +#define VOL_mmUNIPHYB_LINK_CNTL 0x4807 +#define VOL_mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 +#define VOL_mmUNIPHYC_LINK_CNTL 0x4809 +#define VOL_mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a +#define VOL_mmUNIPHYD_LINK_CNTL 0x480b +#define VOL_mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c +#define VOL_mmUNIPHYE_LINK_CNTL 0x480d +#define VOL_mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e +#define VOL_mmUNIPHYF_LINK_CNTL 0x480f +#define VOL_mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 +#define VOL_mmUNIPHYG_LINK_CNTL 0x4811 +#define VOL_mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 +#define VOL_mmUNIPHY_IMPCAL_LINKA 0x4838 +#define VOL_mmUNIPHY_IMPCAL_LINKB 0x4839 +#define VOL_mmUNIPHY_IMPCAL_LINKC 0x483f +#define VOL_mmUNIPHY_IMPCAL_LINKD 0x4840 +#define VOL_mmUNIPHY_IMPCAL_LINKE 0x4843 +#define VOL_mmUNIPHY_IMPCAL_LINKF 0x4844 +#define VOL_mmUNIPHY_IMPCAL_PERIOD 0x483a +#define VOL_mmAUXP_IMPCAL 0x483b +#define VOL_mmAUXN_IMPCAL 0x483c +#define VOL_mmDCIO_IMPCAL_CNTL 0x483d +#define VOL_mmUNIPHY_IMPCAL_PSW_AB 0x483e +#define VOL_mmDCIO_IMPCAL_CNTL_CD 0x4841 +#define VOL_mmUNIPHY_IMPCAL_PSW_CD 0x4842 +#define VOL_mmDCIO_IMPCAL_CNTL_EF 0x4845 +#define VOL_mmUNIPHY_IMPCAL_PSW_EF 0x4846 +#define VOL_mmDCIO_WRCMD_DELAY 0x4816 +#define VOL_mmDC_PINSTRAPS 0x4818 +#define VOL_mmDC_DVODATA_CONFIG 0x481a +#define VOL_mmLVTMA_PWRSEQ_CNTL 0x481b +#define VOL_mmLVTMA_PWRSEQ_STATE 0x481c +#define VOL_mmLVTMA_PWRSEQ_REF_DIV 0x481d +#define VOL_mmLVTMA_PWRSEQ_DELAY1 0x481e +#define VOL_mmLVTMA_PWRSEQ_DELAY2 0x481f +#define VOL_mmBL_PWM_CNTL 0x4820 +#define VOL_mmBL_PWM_CNTL2 0x4821 +#define VOL_mmBL_PWM_PERIOD_CNTL 0x4822 +#define VOL_mmBL_PWM_GRP1_REG_LOCK 0x4823 +#define VOL_mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 +#define VOL_mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 +#define VOL_mmDCIO_GSL0_CNTL 0x4826 +#define VOL_mmDCIO_GSL1_CNTL 0x4827 +#define VOL_mmDCIO_GSL2_CNTL 0x4828 +#define VOL_mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 +#define VOL_mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a +#define VOL_mmDC_GPU_TIMER_READ 0x482b +#define VOL_mmDC_GPU_TIMER_READ_CNTL 0x482c +#define VOL_mmDCIO_CLOCK_CNTL 0x482d +#define VOL_mmDCIO_DEBUG 0x482f +#define VOL_mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 +#define VOL_mmDBG_OUT_CNTL 0x4834 +#define VOL_mmDCIO_DEBUG_CONFIG 0x4835 +#define VOL_mmDCIO_SOFT_RESET 0x4836 +#define VOL_mmDCIO_DPHY_SEL 0x4837 +#define VOL_mmDCIO_TEST_DEBUG_INDEX 0x4831 +#define VOL_mmDCIO_TEST_DEBUG_DATA 0x4832 +#define VOL_ixDCIO_DEBUG1 0x1 +#define VOL_ixDCIO_DEBUG2 0x2 +#define VOL_ixDCIO_DEBUG3 0x3 +#define VOL_ixDCIO_DEBUG4 0x4 +#define VOL_ixDCIO_DEBUG5 0x5 +#define VOL_ixDCIO_DEBUG6 0x6 +#define VOL_ixDCIO_DEBUG7 0x7 +#define VOL_ixDCIO_DEBUG8 0x8 +#define VOL_ixDCIO_DEBUG9 0x9 +#define VOL_ixDCIO_DEBUGA 0xa +#define VOL_ixDCIO_DEBUGB 0xb +#define VOL_ixDCIO_DEBUGC 0xc +#define VOL_ixDCIO_DEBUGD 0xd +#define VOL_ixDCIO_DEBUGE 0xe +#define VOL_ixDCIO_DEBUGF 0xf +#define VOL_ixDCIO_DEBUG10 0x10 +#define VOL_ixDCIO_DEBUG11 0x11 +#define VOL_ixDCIO_DEBUG12 0x12 +#define VOL_ixDCIO_DEBUG13 0x13 +#define VOL_ixDCIO_DEBUG14 0x14 +#define VOL_ixDCIO_DEBUG15 0x15 +#define VOL_ixDCIO_DEBUG16 0x16 +#define VOL_ixDCIO_DEBUG_ID 0x0 +#define VOL_mmDC_GPIO_GENERIC_MASK 0x4860 +#define VOL_mmDC_GPIO_GENERIC_A 0x4861 +#define VOL_mmDC_GPIO_GENERIC_EN 0x4862 +#define VOL_mmDC_GPIO_GENERIC_Y 0x4863 +#define VOL_mmDC_GPIO_DVODATA_MASK 0x4864 +#define VOL_mmDC_GPIO_DVODATA_A 0x4865 +#define VOL_mmDC_GPIO_DVODATA_EN 0x4866 +#define VOL_mmDC_GPIO_DVODATA_Y 0x4867 +#define VOL_mmDC_GPIO_DDC1_MASK 0x4868 +#define VOL_mmDC_GPIO_DDC1_A 0x4869 +#define VOL_mmDC_GPIO_DDC1_EN 0x486a +#define VOL_mmDC_GPIO_DDC1_Y 0x486b +#define VOL_mmDC_GPIO_DDC2_MASK 0x486c +#define VOL_mmDC_GPIO_DDC2_A 0x486d +#define VOL_mmDC_GPIO_DDC2_EN 0x486e +#define VOL_mmDC_GPIO_DDC2_Y 0x486f +#define VOL_mmDC_GPIO_DDC3_MASK 0x4870 +#define VOL_mmDC_GPIO_DDC3_A 0x4871 +#define VOL_mmDC_GPIO_DDC3_EN 0x4872 +#define VOL_mmDC_GPIO_DDC3_Y 0x4873 +#define VOL_mmDC_GPIO_DDC4_MASK 0x4874 +#define VOL_mmDC_GPIO_DDC4_A 0x4875 +#define VOL_mmDC_GPIO_DDC4_EN 0x4876 +#define VOL_mmDC_GPIO_DDC4_Y 0x4877 +#define VOL_mmDC_GPIO_DDC5_MASK 0x4878 +#define VOL_mmDC_GPIO_DDC5_A 0x4879 +#define VOL_mmDC_GPIO_DDC5_EN 0x487a +#define VOL_mmDC_GPIO_DDC5_Y 0x487b +#define VOL_mmDC_GPIO_DDC6_MASK 0x487c +#define VOL_mmDC_GPIO_DDC6_A 0x487d +#define VOL_mmDC_GPIO_DDC6_EN 0x487e +#define VOL_mmDC_GPIO_DDC6_Y 0x487f +#define VOL_mmDC_GPIO_DDCVGA_MASK 0x4880 +#define VOL_mmDC_GPIO_DDCVGA_A 0x4881 +#define VOL_mmDC_GPIO_DDCVGA_EN 0x4882 +#define VOL_mmDC_GPIO_DDCVGA_Y 0x4883 +#define VOL_mmDC_GPIO_SYNCA_MASK 0x4884 +#define VOL_mmDC_GPIO_SYNCA_A 0x4885 +#define VOL_mmDC_GPIO_SYNCA_EN 0x4886 +#define VOL_mmDC_GPIO_SYNCA_Y 0x4887 +#define VOL_mmDC_GPIO_GENLK_MASK 0x4888 +#define VOL_mmDC_GPIO_GENLK_A 0x4889 +#define VOL_mmDC_GPIO_GENLK_EN 0x488a +#define VOL_mmDC_GPIO_GENLK_Y 0x488b +#define VOL_mmDC_GPIO_HPD_MASK 0x488c +#define VOL_mmDC_GPIO_HPD_A 0x488d +#define VOL_mmDC_GPIO_HPD_EN 0x488e +#define VOL_mmDC_GPIO_HPD_Y 0x488f +#define VOL_mmDC_GPIO_PWRSEQ_MASK 0x4890 +#define VOL_mmDC_GPIO_PWRSEQ_A 0x4891 +#define VOL_mmDC_GPIO_PWRSEQ_EN 0x4892 +#define VOL_mmDC_GPIO_PWRSEQ_Y 0x4893 +#define VOL_mmDC_GPIO_PAD_STRENGTH_1 0x4894 +#define VOL_mmDC_GPIO_PAD_STRENGTH_2 0x4895 +#define VOL_mmPHY_AUX_CNTL 0x4897 +#define VOL_mmDC_GPIO_I2CPAD_A 0x4899 +#define VOL_mmDC_GPIO_I2CPAD_EN 0x489a +#define VOL_mmDC_GPIO_I2CPAD_Y 0x489b +#define VOL_mmDC_GPIO_I2CPAD_STRENGTH 0x489c +#define VOL_mmDVO_STRENGTH_CONTROL 0x489d +#define VOL_mmDVO_VREF_CONTROL 0x489e +#define VOL_mmDVO_SKEW_ADJUST 0x489f +#define VOL_mmDAC_MACRO_CNTL_RESERVED0 0x48b8 +#define VOL_mmDAC_MACRO_CNTL_RESERVED1 0x48b9 +#define VOL_mmDAC_MACRO_CNTL_RESERVED2 0x48ba +#define VOL_mmDAC_MACRO_CNTL_RESERVED3 0x48bb +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9 +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919 +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939 +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959 +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999 +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e +#define VOL_mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define VOL_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define VOL_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff +#define VOL_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f +#define VOL_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f +#define VOL_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f +#define VOL_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f +#define VOL_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe +#define VOL_mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff +#define VOL_mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a +#define VOL_mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b +#define VOL_mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c +#define VOL_mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d +#define VOL_mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e +#define VOL_mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f +#define VOL_mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED18 0x5daa +#define VOL_mmDPHY_MACRO_CNTL_RESERVED19 0x5dab +#define VOL_mmDPHY_MACRO_CNTL_RESERVED20 0x5dac +#define VOL_mmDPHY_MACRO_CNTL_RESERVED21 0x5dad +#define VOL_mmDPHY_MACRO_CNTL_RESERVED22 0x5dae +#define VOL_mmDPHY_MACRO_CNTL_RESERVED23 0x5daf +#define VOL_mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED34 0x5dba +#define VOL_mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb +#define VOL_mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc +#define VOL_mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd +#define VOL_mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe +#define VOL_mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf +#define VOL_mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED50 0x5dca +#define VOL_mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb +#define VOL_mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc +#define VOL_mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd +#define VOL_mmDPHY_MACRO_CNTL_RESERVED54 0x5dce +#define VOL_mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf +#define VOL_mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 +#define VOL_mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 +#define VOL_mmGRPH_ENABLE 0x1a00 +#define VOL_mmDCP0_GRPH_ENABLE 0x1a00 +#define VOL_mmDCP1_GRPH_ENABLE 0x1c00 +#define VOL_mmDCP2_GRPH_ENABLE 0x1e00 +#define VOL_mmDCP3_GRPH_ENABLE 0x4000 +#define VOL_mmDCP4_GRPH_ENABLE 0x4200 +#define VOL_mmDCP5_GRPH_ENABLE 0x4400 +#define VOL_mmGRPH_CONTROL 0x1a01 +#define VOL_mmDCP0_GRPH_CONTROL 0x1a01 +#define VOL_mmDCP1_GRPH_CONTROL 0x1c01 +#define VOL_mmDCP2_GRPH_CONTROL 0x1e01 +#define VOL_mmDCP3_GRPH_CONTROL 0x4001 +#define VOL_mmDCP4_GRPH_CONTROL 0x4201 +#define VOL_mmDCP5_GRPH_CONTROL 0x4401 +#define VOL_mmGRPH_LUT_10BIT_BYPASS 0x1a02 +#define VOL_mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 +#define VOL_mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 +#define VOL_mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 +#define VOL_mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 +#define VOL_mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 +#define VOL_mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 +#define VOL_mmGRPH_SWAP_CNTL 0x1a03 +#define VOL_mmDCP0_GRPH_SWAP_CNTL 0x1a03 +#define VOL_mmDCP1_GRPH_SWAP_CNTL 0x1c03 +#define VOL_mmDCP2_GRPH_SWAP_CNTL 0x1e03 +#define VOL_mmDCP3_GRPH_SWAP_CNTL 0x4003 +#define VOL_mmDCP4_GRPH_SWAP_CNTL 0x4203 +#define VOL_mmDCP5_GRPH_SWAP_CNTL 0x4403 +#define VOL_mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define VOL_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define VOL_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 +#define VOL_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 +#define VOL_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define VOL_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 +#define VOL_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 +#define VOL_mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define VOL_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define VOL_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 +#define VOL_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 +#define VOL_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define VOL_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 +#define VOL_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 +#define VOL_mmGRPH_PITCH 0x1a06 +#define VOL_mmDCP0_GRPH_PITCH 0x1a06 +#define VOL_mmDCP1_GRPH_PITCH 0x1c06 +#define VOL_mmDCP2_GRPH_PITCH 0x1e06 +#define VOL_mmDCP3_GRPH_PITCH 0x4006 +#define VOL_mmDCP4_GRPH_PITCH 0x4206 +#define VOL_mmDCP5_GRPH_PITCH 0x4406 +#define VOL_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define VOL_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define VOL_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 +#define VOL_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 +#define VOL_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define VOL_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 +#define VOL_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 +#define VOL_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define VOL_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define VOL_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 +#define VOL_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 +#define VOL_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define VOL_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 +#define VOL_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 +#define VOL_mmGRPH_SURFACE_OFFSET_X 0x1a09 +#define VOL_mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 +#define VOL_mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 +#define VOL_mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 +#define VOL_mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 +#define VOL_mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 +#define VOL_mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 +#define VOL_mmGRPH_SURFACE_OFFSET_Y 0x1a0a +#define VOL_mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a +#define VOL_mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a +#define VOL_mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a +#define VOL_mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a +#define VOL_mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a +#define VOL_mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a +#define VOL_mmGRPH_X_START 0x1a0b +#define VOL_mmDCP0_GRPH_X_START 0x1a0b +#define VOL_mmDCP1_GRPH_X_START 0x1c0b +#define VOL_mmDCP2_GRPH_X_START 0x1e0b +#define VOL_mmDCP3_GRPH_X_START 0x400b +#define VOL_mmDCP4_GRPH_X_START 0x420b +#define VOL_mmDCP5_GRPH_X_START 0x440b +#define VOL_mmGRPH_Y_START 0x1a0c +#define VOL_mmDCP0_GRPH_Y_START 0x1a0c +#define VOL_mmDCP1_GRPH_Y_START 0x1c0c +#define VOL_mmDCP2_GRPH_Y_START 0x1e0c +#define VOL_mmDCP3_GRPH_Y_START 0x400c +#define VOL_mmDCP4_GRPH_Y_START 0x420c +#define VOL_mmDCP5_GRPH_Y_START 0x440c +#define VOL_mmGRPH_X_END 0x1a0d +#define VOL_mmDCP0_GRPH_X_END 0x1a0d +#define VOL_mmDCP1_GRPH_X_END 0x1c0d +#define VOL_mmDCP2_GRPH_X_END 0x1e0d +#define VOL_mmDCP3_GRPH_X_END 0x400d +#define VOL_mmDCP4_GRPH_X_END 0x420d +#define VOL_mmDCP5_GRPH_X_END 0x440d +#define VOL_mmGRPH_Y_END 0x1a0e +#define VOL_mmDCP0_GRPH_Y_END 0x1a0e +#define VOL_mmDCP1_GRPH_Y_END 0x1c0e +#define VOL_mmDCP2_GRPH_Y_END 0x1e0e +#define VOL_mmDCP3_GRPH_Y_END 0x400e +#define VOL_mmDCP4_GRPH_Y_END 0x420e +#define VOL_mmDCP5_GRPH_Y_END 0x440e +#define VOL_mmINPUT_GAMMA_CONTROL 0x1a10 +#define VOL_mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 +#define VOL_mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 +#define VOL_mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 +#define VOL_mmDCP3_INPUT_GAMMA_CONTROL 0x4010 +#define VOL_mmDCP4_INPUT_GAMMA_CONTROL 0x4210 +#define VOL_mmDCP5_INPUT_GAMMA_CONTROL 0x4410 +#define VOL_mmGRPH_UPDATE 0x1a11 +#define VOL_mmDCP0_GRPH_UPDATE 0x1a11 +#define VOL_mmDCP1_GRPH_UPDATE 0x1c11 +#define VOL_mmDCP2_GRPH_UPDATE 0x1e11 +#define VOL_mmDCP3_GRPH_UPDATE 0x4011 +#define VOL_mmDCP4_GRPH_UPDATE 0x4211 +#define VOL_mmDCP5_GRPH_UPDATE 0x4411 +#define VOL_mmGRPH_FLIP_CONTROL 0x1a12 +#define VOL_mmDCP0_GRPH_FLIP_CONTROL 0x1a12 +#define VOL_mmDCP1_GRPH_FLIP_CONTROL 0x1c12 +#define VOL_mmDCP2_GRPH_FLIP_CONTROL 0x1e12 +#define VOL_mmDCP3_GRPH_FLIP_CONTROL 0x4012 +#define VOL_mmDCP4_GRPH_FLIP_CONTROL 0x4212 +#define VOL_mmDCP5_GRPH_FLIP_CONTROL 0x4412 +#define VOL_mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define VOL_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define VOL_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 +#define VOL_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 +#define VOL_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define VOL_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 +#define VOL_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 +#define VOL_mmGRPH_DFQ_CONTROL 0x1a14 +#define VOL_mmDCP0_GRPH_DFQ_CONTROL 0x1a14 +#define VOL_mmDCP1_GRPH_DFQ_CONTROL 0x1c14 +#define VOL_mmDCP2_GRPH_DFQ_CONTROL 0x1e14 +#define VOL_mmDCP3_GRPH_DFQ_CONTROL 0x4014 +#define VOL_mmDCP4_GRPH_DFQ_CONTROL 0x4214 +#define VOL_mmDCP5_GRPH_DFQ_CONTROL 0x4414 +#define VOL_mmGRPH_DFQ_STATUS 0x1a15 +#define VOL_mmDCP0_GRPH_DFQ_STATUS 0x1a15 +#define VOL_mmDCP1_GRPH_DFQ_STATUS 0x1c15 +#define VOL_mmDCP2_GRPH_DFQ_STATUS 0x1e15 +#define VOL_mmDCP3_GRPH_DFQ_STATUS 0x4015 +#define VOL_mmDCP4_GRPH_DFQ_STATUS 0x4215 +#define VOL_mmDCP5_GRPH_DFQ_STATUS 0x4415 +#define VOL_mmGRPH_INTERRUPT_STATUS 0x1a16 +#define VOL_mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 +#define VOL_mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 +#define VOL_mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 +#define VOL_mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 +#define VOL_mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 +#define VOL_mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 +#define VOL_mmGRPH_INTERRUPT_CONTROL 0x1a17 +#define VOL_mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 +#define VOL_mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 +#define VOL_mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 +#define VOL_mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 +#define VOL_mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 +#define VOL_mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 +#define VOL_mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define VOL_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define VOL_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 +#define VOL_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 +#define VOL_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define VOL_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 +#define VOL_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 +#define VOL_mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define VOL_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define VOL_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 +#define VOL_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 +#define VOL_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define VOL_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 +#define VOL_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 +#define VOL_mmGRPH_COMPRESS_PITCH 0x1a1a +#define VOL_mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a +#define VOL_mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a +#define VOL_mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a +#define VOL_mmDCP3_GRPH_COMPRESS_PITCH 0x401a +#define VOL_mmDCP4_GRPH_COMPRESS_PITCH 0x421a +#define VOL_mmDCP5_GRPH_COMPRESS_PITCH 0x441a +#define VOL_mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define VOL_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define VOL_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b +#define VOL_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b +#define VOL_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b +#define VOL_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b +#define VOL_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b +#define VOL_mmOVL_ENABLE 0x1a1c +#define VOL_mmDCP0_OVL_ENABLE 0x1a1c +#define VOL_mmDCP1_OVL_ENABLE 0x1c1c +#define VOL_mmDCP2_OVL_ENABLE 0x1e1c +#define VOL_mmDCP3_OVL_ENABLE 0x401c +#define VOL_mmDCP4_OVL_ENABLE 0x421c +#define VOL_mmDCP5_OVL_ENABLE 0x441c +#define VOL_mmOVL_CONTROL1 0x1a1d +#define VOL_mmDCP0_OVL_CONTROL1 0x1a1d +#define VOL_mmDCP1_OVL_CONTROL1 0x1c1d +#define VOL_mmDCP2_OVL_CONTROL1 0x1e1d +#define VOL_mmDCP3_OVL_CONTROL1 0x401d +#define VOL_mmDCP4_OVL_CONTROL1 0x421d +#define VOL_mmDCP5_OVL_CONTROL1 0x441d +#define VOL_mmOVL_CONTROL2 0x1a1e +#define VOL_mmDCP0_OVL_CONTROL2 0x1a1e +#define VOL_mmDCP1_OVL_CONTROL2 0x1c1e +#define VOL_mmDCP2_OVL_CONTROL2 0x1e1e +#define VOL_mmDCP3_OVL_CONTROL2 0x401e +#define VOL_mmDCP4_OVL_CONTROL2 0x421e +#define VOL_mmDCP5_OVL_CONTROL2 0x441e +#define VOL_mmOVL_SWAP_CNTL 0x1a1f +#define VOL_mmDCP0_OVL_SWAP_CNTL 0x1a1f +#define VOL_mmDCP1_OVL_SWAP_CNTL 0x1c1f +#define VOL_mmDCP2_OVL_SWAP_CNTL 0x1e1f +#define VOL_mmDCP3_OVL_SWAP_CNTL 0x401f +#define VOL_mmDCP4_OVL_SWAP_CNTL 0x421f +#define VOL_mmDCP5_OVL_SWAP_CNTL 0x441f +#define VOL_mmOVL_SURFACE_ADDRESS 0x1a20 +#define VOL_mmDCP0_OVL_SURFACE_ADDRESS 0x1a20 +#define VOL_mmDCP1_OVL_SURFACE_ADDRESS 0x1c20 +#define VOL_mmDCP2_OVL_SURFACE_ADDRESS 0x1e20 +#define VOL_mmDCP3_OVL_SURFACE_ADDRESS 0x4020 +#define VOL_mmDCP4_OVL_SURFACE_ADDRESS 0x4220 +#define VOL_mmDCP5_OVL_SURFACE_ADDRESS 0x4420 +#define VOL_mmOVL_PITCH 0x1a21 +#define VOL_mmDCP0_OVL_PITCH 0x1a21 +#define VOL_mmDCP1_OVL_PITCH 0x1c21 +#define VOL_mmDCP2_OVL_PITCH 0x1e21 +#define VOL_mmDCP3_OVL_PITCH 0x4021 +#define VOL_mmDCP4_OVL_PITCH 0x4221 +#define VOL_mmDCP5_OVL_PITCH 0x4421 +#define VOL_mmOVL_SURFACE_ADDRESS_HIGH 0x1a22 +#define VOL_mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22 +#define VOL_mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1c22 +#define VOL_mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x1e22 +#define VOL_mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4022 +#define VOL_mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4222 +#define VOL_mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4422 +#define VOL_mmOVL_SURFACE_OFFSET_X 0x1a23 +#define VOL_mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23 +#define VOL_mmDCP1_OVL_SURFACE_OFFSET_X 0x1c23 +#define VOL_mmDCP2_OVL_SURFACE_OFFSET_X 0x1e23 +#define VOL_mmDCP3_OVL_SURFACE_OFFSET_X 0x4023 +#define VOL_mmDCP4_OVL_SURFACE_OFFSET_X 0x4223 +#define VOL_mmDCP5_OVL_SURFACE_OFFSET_X 0x4423 +#define VOL_mmOVL_SURFACE_OFFSET_Y 0x1a24 +#define VOL_mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24 +#define VOL_mmDCP1_OVL_SURFACE_OFFSET_Y 0x1c24 +#define VOL_mmDCP2_OVL_SURFACE_OFFSET_Y 0x1e24 +#define VOL_mmDCP3_OVL_SURFACE_OFFSET_Y 0x4024 +#define VOL_mmDCP4_OVL_SURFACE_OFFSET_Y 0x4224 +#define VOL_mmDCP5_OVL_SURFACE_OFFSET_Y 0x4424 +#define VOL_mmOVL_START 0x1a25 +#define VOL_mmDCP0_OVL_START 0x1a25 +#define VOL_mmDCP1_OVL_START 0x1c25 +#define VOL_mmDCP2_OVL_START 0x1e25 +#define VOL_mmDCP3_OVL_START 0x4025 +#define VOL_mmDCP4_OVL_START 0x4225 +#define VOL_mmDCP5_OVL_START 0x4425 +#define VOL_mmOVL_END 0x1a26 +#define VOL_mmDCP0_OVL_END 0x1a26 +#define VOL_mmDCP1_OVL_END 0x1c26 +#define VOL_mmDCP2_OVL_END 0x1e26 +#define VOL_mmDCP3_OVL_END 0x4026 +#define VOL_mmDCP4_OVL_END 0x4226 +#define VOL_mmDCP5_OVL_END 0x4426 +#define VOL_mmOVL_UPDATE 0x1a27 +#define VOL_mmDCP0_OVL_UPDATE 0x1a27 +#define VOL_mmDCP1_OVL_UPDATE 0x1c27 +#define VOL_mmDCP2_OVL_UPDATE 0x1e27 +#define VOL_mmDCP3_OVL_UPDATE 0x4027 +#define VOL_mmDCP4_OVL_UPDATE 0x4227 +#define VOL_mmDCP5_OVL_UPDATE 0x4427 +#define VOL_mmOVL_SURFACE_ADDRESS_INUSE 0x1a28 +#define VOL_mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28 +#define VOL_mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1c28 +#define VOL_mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x1e28 +#define VOL_mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4028 +#define VOL_mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4228 +#define VOL_mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4428 +#define VOL_mmOVL_DFQ_CONTROL 0x1a29 +#define VOL_mmDCP0_OVL_DFQ_CONTROL 0x1a29 +#define VOL_mmDCP1_OVL_DFQ_CONTROL 0x1c29 +#define VOL_mmDCP2_OVL_DFQ_CONTROL 0x1e29 +#define VOL_mmDCP3_OVL_DFQ_CONTROL 0x4029 +#define VOL_mmDCP4_OVL_DFQ_CONTROL 0x4229 +#define VOL_mmDCP5_OVL_DFQ_CONTROL 0x4429 +#define VOL_mmOVL_DFQ_STATUS 0x1a2a +#define VOL_mmDCP0_OVL_DFQ_STATUS 0x1a2a +#define VOL_mmDCP1_OVL_DFQ_STATUS 0x1c2a +#define VOL_mmDCP2_OVL_DFQ_STATUS 0x1e2a +#define VOL_mmDCP3_OVL_DFQ_STATUS 0x402a +#define VOL_mmDCP4_OVL_DFQ_STATUS 0x422a +#define VOL_mmDCP5_OVL_DFQ_STATUS 0x442a +#define VOL_mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b +#define VOL_mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b +#define VOL_mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1c2b +#define VOL_mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1e2b +#define VOL_mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b +#define VOL_mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x422b +#define VOL_mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x442b +#define VOL_mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c +#define VOL_mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c +#define VOL_mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1c2c +#define VOL_mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x1e2c +#define VOL_mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x402c +#define VOL_mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x422c +#define VOL_mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x442c +#define VOL_mmPRESCALE_GRPH_CONTROL 0x1a2d +#define VOL_mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d +#define VOL_mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d +#define VOL_mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d +#define VOL_mmDCP3_PRESCALE_GRPH_CONTROL 0x402d +#define VOL_mmDCP4_PRESCALE_GRPH_CONTROL 0x422d +#define VOL_mmDCP5_PRESCALE_GRPH_CONTROL 0x442d +#define VOL_mmPRESCALE_VALUES_GRPH_R 0x1a2e +#define VOL_mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e +#define VOL_mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e +#define VOL_mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e +#define VOL_mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e +#define VOL_mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e +#define VOL_mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e +#define VOL_mmPRESCALE_VALUES_GRPH_G 0x1a2f +#define VOL_mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f +#define VOL_mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f +#define VOL_mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f +#define VOL_mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f +#define VOL_mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f +#define VOL_mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f +#define VOL_mmPRESCALE_VALUES_GRPH_B 0x1a30 +#define VOL_mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 +#define VOL_mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 +#define VOL_mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 +#define VOL_mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 +#define VOL_mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 +#define VOL_mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 +#define VOL_mmPRESCALE_OVL_CONTROL 0x1a31 +#define VOL_mmDCP0_PRESCALE_OVL_CONTROL 0x1a31 +#define VOL_mmDCP1_PRESCALE_OVL_CONTROL 0x1c31 +#define VOL_mmDCP2_PRESCALE_OVL_CONTROL 0x1e31 +#define VOL_mmDCP3_PRESCALE_OVL_CONTROL 0x4031 +#define VOL_mmDCP4_PRESCALE_OVL_CONTROL 0x4231 +#define VOL_mmDCP5_PRESCALE_OVL_CONTROL 0x4431 +#define VOL_mmPRESCALE_VALUES_OVL_CB 0x1a32 +#define VOL_mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32 +#define VOL_mmDCP1_PRESCALE_VALUES_OVL_CB 0x1c32 +#define VOL_mmDCP2_PRESCALE_VALUES_OVL_CB 0x1e32 +#define VOL_mmDCP3_PRESCALE_VALUES_OVL_CB 0x4032 +#define VOL_mmDCP4_PRESCALE_VALUES_OVL_CB 0x4232 +#define VOL_mmDCP5_PRESCALE_VALUES_OVL_CB 0x4432 +#define VOL_mmPRESCALE_VALUES_OVL_Y 0x1a33 +#define VOL_mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33 +#define VOL_mmDCP1_PRESCALE_VALUES_OVL_Y 0x1c33 +#define VOL_mmDCP2_PRESCALE_VALUES_OVL_Y 0x1e33 +#define VOL_mmDCP3_PRESCALE_VALUES_OVL_Y 0x4033 +#define VOL_mmDCP4_PRESCALE_VALUES_OVL_Y 0x4233 +#define VOL_mmDCP5_PRESCALE_VALUES_OVL_Y 0x4433 +#define VOL_mmPRESCALE_VALUES_OVL_CR 0x1a34 +#define VOL_mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34 +#define VOL_mmDCP1_PRESCALE_VALUES_OVL_CR 0x1c34 +#define VOL_mmDCP2_PRESCALE_VALUES_OVL_CR 0x1e34 +#define VOL_mmDCP3_PRESCALE_VALUES_OVL_CR 0x4034 +#define VOL_mmDCP4_PRESCALE_VALUES_OVL_CR 0x4234 +#define VOL_mmDCP5_PRESCALE_VALUES_OVL_CR 0x4434 +#define VOL_mmINPUT_CSC_CONTROL 0x1a35 +#define VOL_mmDCP0_INPUT_CSC_CONTROL 0x1a35 +#define VOL_mmDCP1_INPUT_CSC_CONTROL 0x1c35 +#define VOL_mmDCP2_INPUT_CSC_CONTROL 0x1e35 +#define VOL_mmDCP3_INPUT_CSC_CONTROL 0x4035 +#define VOL_mmDCP4_INPUT_CSC_CONTROL 0x4235 +#define VOL_mmDCP5_INPUT_CSC_CONTROL 0x4435 +#define VOL_mmINPUT_CSC_C11_C12 0x1a36 +#define VOL_mmDCP0_INPUT_CSC_C11_C12 0x1a36 +#define VOL_mmDCP1_INPUT_CSC_C11_C12 0x1c36 +#define VOL_mmDCP2_INPUT_CSC_C11_C12 0x1e36 +#define VOL_mmDCP3_INPUT_CSC_C11_C12 0x4036 +#define VOL_mmDCP4_INPUT_CSC_C11_C12 0x4236 +#define VOL_mmDCP5_INPUT_CSC_C11_C12 0x4436 +#define VOL_mmINPUT_CSC_C13_C14 0x1a37 +#define VOL_mmDCP0_INPUT_CSC_C13_C14 0x1a37 +#define VOL_mmDCP1_INPUT_CSC_C13_C14 0x1c37 +#define VOL_mmDCP2_INPUT_CSC_C13_C14 0x1e37 +#define VOL_mmDCP3_INPUT_CSC_C13_C14 0x4037 +#define VOL_mmDCP4_INPUT_CSC_C13_C14 0x4237 +#define VOL_mmDCP5_INPUT_CSC_C13_C14 0x4437 +#define VOL_mmINPUT_CSC_C21_C22 0x1a38 +#define VOL_mmDCP0_INPUT_CSC_C21_C22 0x1a38 +#define VOL_mmDCP1_INPUT_CSC_C21_C22 0x1c38 +#define VOL_mmDCP2_INPUT_CSC_C21_C22 0x1e38 +#define VOL_mmDCP3_INPUT_CSC_C21_C22 0x4038 +#define VOL_mmDCP4_INPUT_CSC_C21_C22 0x4238 +#define VOL_mmDCP5_INPUT_CSC_C21_C22 0x4438 +#define VOL_mmINPUT_CSC_C23_C24 0x1a39 +#define VOL_mmDCP0_INPUT_CSC_C23_C24 0x1a39 +#define VOL_mmDCP1_INPUT_CSC_C23_C24 0x1c39 +#define VOL_mmDCP2_INPUT_CSC_C23_C24 0x1e39 +#define VOL_mmDCP3_INPUT_CSC_C23_C24 0x4039 +#define VOL_mmDCP4_INPUT_CSC_C23_C24 0x4239 +#define VOL_mmDCP5_INPUT_CSC_C23_C24 0x4439 +#define VOL_mmINPUT_CSC_C31_C32 0x1a3a +#define VOL_mmDCP0_INPUT_CSC_C31_C32 0x1a3a +#define VOL_mmDCP1_INPUT_CSC_C31_C32 0x1c3a +#define VOL_mmDCP2_INPUT_CSC_C31_C32 0x1e3a +#define VOL_mmDCP3_INPUT_CSC_C31_C32 0x403a +#define VOL_mmDCP4_INPUT_CSC_C31_C32 0x423a +#define VOL_mmDCP5_INPUT_CSC_C31_C32 0x443a +#define VOL_mmINPUT_CSC_C33_C34 0x1a3b +#define VOL_mmDCP0_INPUT_CSC_C33_C34 0x1a3b +#define VOL_mmDCP1_INPUT_CSC_C33_C34 0x1c3b +#define VOL_mmDCP2_INPUT_CSC_C33_C34 0x1e3b +#define VOL_mmDCP3_INPUT_CSC_C33_C34 0x403b +#define VOL_mmDCP4_INPUT_CSC_C33_C34 0x423b +#define VOL_mmDCP5_INPUT_CSC_C33_C34 0x443b +#define VOL_mmOUTPUT_CSC_CONTROL 0x1a3c +#define VOL_mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c +#define VOL_mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c +#define VOL_mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c +#define VOL_mmDCP3_OUTPUT_CSC_CONTROL 0x403c +#define VOL_mmDCP4_OUTPUT_CSC_CONTROL 0x423c +#define VOL_mmDCP5_OUTPUT_CSC_CONTROL 0x443c +#define VOL_mmOUTPUT_CSC_C11_C12 0x1a3d +#define VOL_mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d +#define VOL_mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d +#define VOL_mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d +#define VOL_mmDCP3_OUTPUT_CSC_C11_C12 0x403d +#define VOL_mmDCP4_OUTPUT_CSC_C11_C12 0x423d +#define VOL_mmDCP5_OUTPUT_CSC_C11_C12 0x443d +#define VOL_mmOUTPUT_CSC_C13_C14 0x1a3e +#define VOL_mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e +#define VOL_mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e +#define VOL_mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e +#define VOL_mmDCP3_OUTPUT_CSC_C13_C14 0x403e +#define VOL_mmDCP4_OUTPUT_CSC_C13_C14 0x423e +#define VOL_mmDCP5_OUTPUT_CSC_C13_C14 0x443e +#define VOL_mmOUTPUT_CSC_C21_C22 0x1a3f +#define VOL_mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f +#define VOL_mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f +#define VOL_mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f +#define VOL_mmDCP3_OUTPUT_CSC_C21_C22 0x403f +#define VOL_mmDCP4_OUTPUT_CSC_C21_C22 0x423f +#define VOL_mmDCP5_OUTPUT_CSC_C21_C22 0x443f +#define VOL_mmOUTPUT_CSC_C23_C24 0x1a40 +#define VOL_mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 +#define VOL_mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 +#define VOL_mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 +#define VOL_mmDCP3_OUTPUT_CSC_C23_C24 0x4040 +#define VOL_mmDCP4_OUTPUT_CSC_C23_C24 0x4240 +#define VOL_mmDCP5_OUTPUT_CSC_C23_C24 0x4440 +#define VOL_mmOUTPUT_CSC_C31_C32 0x1a41 +#define VOL_mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 +#define VOL_mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 +#define VOL_mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 +#define VOL_mmDCP3_OUTPUT_CSC_C31_C32 0x4041 +#define VOL_mmDCP4_OUTPUT_CSC_C31_C32 0x4241 +#define VOL_mmDCP5_OUTPUT_CSC_C31_C32 0x4441 +#define VOL_mmOUTPUT_CSC_C33_C34 0x1a42 +#define VOL_mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 +#define VOL_mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 +#define VOL_mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 +#define VOL_mmDCP3_OUTPUT_CSC_C33_C34 0x4042 +#define VOL_mmDCP4_OUTPUT_CSC_C33_C34 0x4242 +#define VOL_mmDCP5_OUTPUT_CSC_C33_C34 0x4442 +#define VOL_mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 +#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 +#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 +#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 +#define VOL_mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 +#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 +#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 +#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 +#define VOL_mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 +#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 +#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 +#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 +#define VOL_mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 +#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 +#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 +#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 +#define VOL_mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 +#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 +#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 +#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 +#define VOL_mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define VOL_mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define VOL_mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 +#define VOL_mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 +#define VOL_mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define VOL_mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 +#define VOL_mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 +#define VOL_mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 +#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 +#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 +#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 +#define VOL_mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a +#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a +#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a +#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a +#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a +#define VOL_mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b +#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b +#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b +#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b +#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b +#define VOL_mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c +#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c +#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c +#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c +#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c +#define VOL_mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d +#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d +#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d +#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d +#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d +#define VOL_mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define VOL_mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define VOL_mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e +#define VOL_mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e +#define VOL_mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e +#define VOL_mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e +#define VOL_mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e +#define VOL_mmDENORM_CONTROL 0x1a50 +#define VOL_mmDCP0_DENORM_CONTROL 0x1a50 +#define VOL_mmDCP1_DENORM_CONTROL 0x1c50 +#define VOL_mmDCP2_DENORM_CONTROL 0x1e50 +#define VOL_mmDCP3_DENORM_CONTROL 0x4050 +#define VOL_mmDCP4_DENORM_CONTROL 0x4250 +#define VOL_mmDCP5_DENORM_CONTROL 0x4450 +#define VOL_mmOUT_ROUND_CONTROL 0x1a51 +#define VOL_mmDCP0_OUT_ROUND_CONTROL 0x1a51 +#define VOL_mmDCP1_OUT_ROUND_CONTROL 0x1c51 +#define VOL_mmDCP2_OUT_ROUND_CONTROL 0x1e51 +#define VOL_mmDCP3_OUT_ROUND_CONTROL 0x4051 +#define VOL_mmDCP4_OUT_ROUND_CONTROL 0x4251 +#define VOL_mmDCP5_OUT_ROUND_CONTROL 0x4451 +#define VOL_mmOUT_CLAMP_CONTROL_R_CR 0x1a52 +#define VOL_mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 +#define VOL_mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 +#define VOL_mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 +#define VOL_mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 +#define VOL_mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 +#define VOL_mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 +#define VOL_mmOUT_CLAMP_CONTROL_G_Y 0x1a9c +#define VOL_mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c +#define VOL_mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c +#define VOL_mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c +#define VOL_mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c +#define VOL_mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c +#define VOL_mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c +#define VOL_mmOUT_CLAMP_CONTROL_B_CB 0x1a9d +#define VOL_mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d +#define VOL_mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d +#define VOL_mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d +#define VOL_mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d +#define VOL_mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d +#define VOL_mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d +#define VOL_mmKEY_CONTROL 0x1a53 +#define VOL_mmDCP0_KEY_CONTROL 0x1a53 +#define VOL_mmDCP1_KEY_CONTROL 0x1c53 +#define VOL_mmDCP2_KEY_CONTROL 0x1e53 +#define VOL_mmDCP3_KEY_CONTROL 0x4053 +#define VOL_mmDCP4_KEY_CONTROL 0x4253 +#define VOL_mmDCP5_KEY_CONTROL 0x4453 +#define VOL_mmKEY_RANGE_ALPHA 0x1a54 +#define VOL_mmDCP0_KEY_RANGE_ALPHA 0x1a54 +#define VOL_mmDCP1_KEY_RANGE_ALPHA 0x1c54 +#define VOL_mmDCP2_KEY_RANGE_ALPHA 0x1e54 +#define VOL_mmDCP3_KEY_RANGE_ALPHA 0x4054 +#define VOL_mmDCP4_KEY_RANGE_ALPHA 0x4254 +#define VOL_mmDCP5_KEY_RANGE_ALPHA 0x4454 +#define VOL_mmKEY_RANGE_RED 0x1a55 +#define VOL_mmDCP0_KEY_RANGE_RED 0x1a55 +#define VOL_mmDCP1_KEY_RANGE_RED 0x1c55 +#define VOL_mmDCP2_KEY_RANGE_RED 0x1e55 +#define VOL_mmDCP3_KEY_RANGE_RED 0x4055 +#define VOL_mmDCP4_KEY_RANGE_RED 0x4255 +#define VOL_mmDCP5_KEY_RANGE_RED 0x4455 +#define VOL_mmKEY_RANGE_GREEN 0x1a56 +#define VOL_mmDCP0_KEY_RANGE_GREEN 0x1a56 +#define VOL_mmDCP1_KEY_RANGE_GREEN 0x1c56 +#define VOL_mmDCP2_KEY_RANGE_GREEN 0x1e56 +#define VOL_mmDCP3_KEY_RANGE_GREEN 0x4056 +#define VOL_mmDCP4_KEY_RANGE_GREEN 0x4256 +#define VOL_mmDCP5_KEY_RANGE_GREEN 0x4456 +#define VOL_mmKEY_RANGE_BLUE 0x1a57 +#define VOL_mmDCP0_KEY_RANGE_BLUE 0x1a57 +#define VOL_mmDCP1_KEY_RANGE_BLUE 0x1c57 +#define VOL_mmDCP2_KEY_RANGE_BLUE 0x1e57 +#define VOL_mmDCP3_KEY_RANGE_BLUE 0x4057 +#define VOL_mmDCP4_KEY_RANGE_BLUE 0x4257 +#define VOL_mmDCP5_KEY_RANGE_BLUE 0x4457 +#define VOL_mmDEGAMMA_CONTROL 0x1a58 +#define VOL_mmDCP0_DEGAMMA_CONTROL 0x1a58 +#define VOL_mmDCP1_DEGAMMA_CONTROL 0x1c58 +#define VOL_mmDCP2_DEGAMMA_CONTROL 0x1e58 +#define VOL_mmDCP3_DEGAMMA_CONTROL 0x4058 +#define VOL_mmDCP4_DEGAMMA_CONTROL 0x4258 +#define VOL_mmDCP5_DEGAMMA_CONTROL 0x4458 +#define VOL_mmGAMUT_REMAP_CONTROL 0x1a59 +#define VOL_mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 +#define VOL_mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 +#define VOL_mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 +#define VOL_mmDCP3_GAMUT_REMAP_CONTROL 0x4059 +#define VOL_mmDCP4_GAMUT_REMAP_CONTROL 0x4259 +#define VOL_mmDCP5_GAMUT_REMAP_CONTROL 0x4459 +#define VOL_mmGAMUT_REMAP_C11_C12 0x1a5a +#define VOL_mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a +#define VOL_mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a +#define VOL_mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a +#define VOL_mmDCP3_GAMUT_REMAP_C11_C12 0x405a +#define VOL_mmDCP4_GAMUT_REMAP_C11_C12 0x425a +#define VOL_mmDCP5_GAMUT_REMAP_C11_C12 0x445a +#define VOL_mmGAMUT_REMAP_C13_C14 0x1a5b +#define VOL_mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b +#define VOL_mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b +#define VOL_mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b +#define VOL_mmDCP3_GAMUT_REMAP_C13_C14 0x405b +#define VOL_mmDCP4_GAMUT_REMAP_C13_C14 0x425b +#define VOL_mmDCP5_GAMUT_REMAP_C13_C14 0x445b +#define VOL_mmGAMUT_REMAP_C21_C22 0x1a5c +#define VOL_mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c +#define VOL_mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c +#define VOL_mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c +#define VOL_mmDCP3_GAMUT_REMAP_C21_C22 0x405c +#define VOL_mmDCP4_GAMUT_REMAP_C21_C22 0x425c +#define VOL_mmDCP5_GAMUT_REMAP_C21_C22 0x445c +#define VOL_mmGAMUT_REMAP_C23_C24 0x1a5d +#define VOL_mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d +#define VOL_mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d +#define VOL_mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d +#define VOL_mmDCP3_GAMUT_REMAP_C23_C24 0x405d +#define VOL_mmDCP4_GAMUT_REMAP_C23_C24 0x425d +#define VOL_mmDCP5_GAMUT_REMAP_C23_C24 0x445d +#define VOL_mmGAMUT_REMAP_C31_C32 0x1a5e +#define VOL_mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e +#define VOL_mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e +#define VOL_mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e +#define VOL_mmDCP3_GAMUT_REMAP_C31_C32 0x405e +#define VOL_mmDCP4_GAMUT_REMAP_C31_C32 0x425e +#define VOL_mmDCP5_GAMUT_REMAP_C31_C32 0x445e +#define VOL_mmGAMUT_REMAP_C33_C34 0x1a5f +#define VOL_mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f +#define VOL_mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f +#define VOL_mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f +#define VOL_mmDCP3_GAMUT_REMAP_C33_C34 0x405f +#define VOL_mmDCP4_GAMUT_REMAP_C33_C34 0x425f +#define VOL_mmDCP5_GAMUT_REMAP_C33_C34 0x445f +#define VOL_mmDCP_SPATIAL_DITHER_CNTL 0x1a60 +#define VOL_mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 +#define VOL_mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 +#define VOL_mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 +#define VOL_mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define VOL_mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 +#define VOL_mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 +#define VOL_mmDCP_RANDOM_SEEDS 0x1a61 +#define VOL_mmDCP0_DCP_RANDOM_SEEDS 0x1a61 +#define VOL_mmDCP1_DCP_RANDOM_SEEDS 0x1c61 +#define VOL_mmDCP2_DCP_RANDOM_SEEDS 0x1e61 +#define VOL_mmDCP3_DCP_RANDOM_SEEDS 0x4061 +#define VOL_mmDCP4_DCP_RANDOM_SEEDS 0x4261 +#define VOL_mmDCP5_DCP_RANDOM_SEEDS 0x4461 +#define VOL_mmDCP_FP_CONVERTED_FIELD 0x1a65 +#define VOL_mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 +#define VOL_mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 +#define VOL_mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 +#define VOL_mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 +#define VOL_mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 +#define VOL_mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 +#define VOL_mmCUR_CONTROL 0x1a66 +#define VOL_mmDCP0_CUR_CONTROL 0x1a66 +#define VOL_mmDCP1_CUR_CONTROL 0x1c66 +#define VOL_mmDCP2_CUR_CONTROL 0x1e66 +#define VOL_mmDCP3_CUR_CONTROL 0x4066 +#define VOL_mmDCP4_CUR_CONTROL 0x4266 +#define VOL_mmDCP5_CUR_CONTROL 0x4466 +#define VOL_mmCUR_SURFACE_ADDRESS 0x1a67 +#define VOL_mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 +#define VOL_mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 +#define VOL_mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 +#define VOL_mmDCP3_CUR_SURFACE_ADDRESS 0x4067 +#define VOL_mmDCP4_CUR_SURFACE_ADDRESS 0x4267 +#define VOL_mmDCP5_CUR_SURFACE_ADDRESS 0x4467 +#define VOL_mmCUR_SIZE 0x1a68 +#define VOL_mmDCP0_CUR_SIZE 0x1a68 +#define VOL_mmDCP1_CUR_SIZE 0x1c68 +#define VOL_mmDCP2_CUR_SIZE 0x1e68 +#define VOL_mmDCP3_CUR_SIZE 0x4068 +#define VOL_mmDCP4_CUR_SIZE 0x4268 +#define VOL_mmDCP5_CUR_SIZE 0x4468 +#define VOL_mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define VOL_mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define VOL_mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 +#define VOL_mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 +#define VOL_mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define VOL_mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 +#define VOL_mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 +#define VOL_mmCUR_POSITION 0x1a6a +#define VOL_mmDCP0_CUR_POSITION 0x1a6a +#define VOL_mmDCP1_CUR_POSITION 0x1c6a +#define VOL_mmDCP2_CUR_POSITION 0x1e6a +#define VOL_mmDCP3_CUR_POSITION 0x406a +#define VOL_mmDCP4_CUR_POSITION 0x426a +#define VOL_mmDCP5_CUR_POSITION 0x446a +#define VOL_mmCUR_HOT_SPOT 0x1a6b +#define VOL_mmDCP0_CUR_HOT_SPOT 0x1a6b +#define VOL_mmDCP1_CUR_HOT_SPOT 0x1c6b +#define VOL_mmDCP2_CUR_HOT_SPOT 0x1e6b +#define VOL_mmDCP3_CUR_HOT_SPOT 0x406b +#define VOL_mmDCP4_CUR_HOT_SPOT 0x426b +#define VOL_mmDCP5_CUR_HOT_SPOT 0x446b +#define VOL_mmCUR_COLOR1 0x1a6c +#define VOL_mmDCP0_CUR_COLOR1 0x1a6c +#define VOL_mmDCP1_CUR_COLOR1 0x1c6c +#define VOL_mmDCP2_CUR_COLOR1 0x1e6c +#define VOL_mmDCP3_CUR_COLOR1 0x406c +#define VOL_mmDCP4_CUR_COLOR1 0x426c +#define VOL_mmDCP5_CUR_COLOR1 0x446c +#define VOL_mmCUR_COLOR2 0x1a6d +#define VOL_mmDCP0_CUR_COLOR2 0x1a6d +#define VOL_mmDCP1_CUR_COLOR2 0x1c6d +#define VOL_mmDCP2_CUR_COLOR2 0x1e6d +#define VOL_mmDCP3_CUR_COLOR2 0x406d +#define VOL_mmDCP4_CUR_COLOR2 0x426d +#define VOL_mmDCP5_CUR_COLOR2 0x446d +#define VOL_mmCUR_UPDATE 0x1a6e +#define VOL_mmDCP0_CUR_UPDATE 0x1a6e +#define VOL_mmDCP1_CUR_UPDATE 0x1c6e +#define VOL_mmDCP2_CUR_UPDATE 0x1e6e +#define VOL_mmDCP3_CUR_UPDATE 0x406e +#define VOL_mmDCP4_CUR_UPDATE 0x426e +#define VOL_mmDCP5_CUR_UPDATE 0x446e +#define VOL_mmCUR_REQUEST_FILTER_CNTL 0x1a99 +#define VOL_mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 +#define VOL_mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 +#define VOL_mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 +#define VOL_mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 +#define VOL_mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 +#define VOL_mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 +#define VOL_mmCUR_STEREO_CONTROL 0x1a9a +#define VOL_mmDCP0_CUR_STEREO_CONTROL 0x1a9a +#define VOL_mmDCP1_CUR_STEREO_CONTROL 0x1c9a +#define VOL_mmDCP2_CUR_STEREO_CONTROL 0x1e9a +#define VOL_mmDCP3_CUR_STEREO_CONTROL 0x409a +#define VOL_mmDCP4_CUR_STEREO_CONTROL 0x429a +#define VOL_mmDCP5_CUR_STEREO_CONTROL 0x449a +#define VOL_mmDC_LUT_RW_MODE 0x1a78 +#define VOL_mmDCP0_DC_LUT_RW_MODE 0x1a78 +#define VOL_mmDCP1_DC_LUT_RW_MODE 0x1c78 +#define VOL_mmDCP2_DC_LUT_RW_MODE 0x1e78 +#define VOL_mmDCP3_DC_LUT_RW_MODE 0x4078 +#define VOL_mmDCP4_DC_LUT_RW_MODE 0x4278 +#define VOL_mmDCP5_DC_LUT_RW_MODE 0x4478 +#define VOL_mmDC_LUT_RW_INDEX 0x1a79 +#define VOL_mmDCP0_DC_LUT_RW_INDEX 0x1a79 +#define VOL_mmDCP1_DC_LUT_RW_INDEX 0x1c79 +#define VOL_mmDCP2_DC_LUT_RW_INDEX 0x1e79 +#define VOL_mmDCP3_DC_LUT_RW_INDEX 0x4079 +#define VOL_mmDCP4_DC_LUT_RW_INDEX 0x4279 +#define VOL_mmDCP5_DC_LUT_RW_INDEX 0x4479 +#define VOL_mmDC_LUT_SEQ_COLOR 0x1a7a +#define VOL_mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a +#define VOL_mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a +#define VOL_mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a +#define VOL_mmDCP3_DC_LUT_SEQ_COLOR 0x407a +#define VOL_mmDCP4_DC_LUT_SEQ_COLOR 0x427a +#define VOL_mmDCP5_DC_LUT_SEQ_COLOR 0x447a +#define VOL_mmDC_LUT_PWL_DATA 0x1a7b +#define VOL_mmDCP0_DC_LUT_PWL_DATA 0x1a7b +#define VOL_mmDCP1_DC_LUT_PWL_DATA 0x1c7b +#define VOL_mmDCP2_DC_LUT_PWL_DATA 0x1e7b +#define VOL_mmDCP3_DC_LUT_PWL_DATA 0x407b +#define VOL_mmDCP4_DC_LUT_PWL_DATA 0x427b +#define VOL_mmDCP5_DC_LUT_PWL_DATA 0x447b +#define VOL_mmDC_LUT_30_COLOR 0x1a7c +#define VOL_mmDCP0_DC_LUT_30_COLOR 0x1a7c +#define VOL_mmDCP1_DC_LUT_30_COLOR 0x1c7c +#define VOL_mmDCP2_DC_LUT_30_COLOR 0x1e7c +#define VOL_mmDCP3_DC_LUT_30_COLOR 0x407c +#define VOL_mmDCP4_DC_LUT_30_COLOR 0x427c +#define VOL_mmDCP5_DC_LUT_30_COLOR 0x447c +#define VOL_mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define VOL_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define VOL_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d +#define VOL_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d +#define VOL_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d +#define VOL_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d +#define VOL_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d +#define VOL_mmDC_LUT_WRITE_EN_MASK 0x1a7e +#define VOL_mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e +#define VOL_mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e +#define VOL_mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e +#define VOL_mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e +#define VOL_mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e +#define VOL_mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e +#define VOL_mmDC_LUT_AUTOFILL 0x1a7f +#define VOL_mmDCP0_DC_LUT_AUTOFILL 0x1a7f +#define VOL_mmDCP1_DC_LUT_AUTOFILL 0x1c7f +#define VOL_mmDCP2_DC_LUT_AUTOFILL 0x1e7f +#define VOL_mmDCP3_DC_LUT_AUTOFILL 0x407f +#define VOL_mmDCP4_DC_LUT_AUTOFILL 0x427f +#define VOL_mmDCP5_DC_LUT_AUTOFILL 0x447f +#define VOL_mmDC_LUT_CONTROL 0x1a80 +#define VOL_mmDCP0_DC_LUT_CONTROL 0x1a80 +#define VOL_mmDCP1_DC_LUT_CONTROL 0x1c80 +#define VOL_mmDCP2_DC_LUT_CONTROL 0x1e80 +#define VOL_mmDCP3_DC_LUT_CONTROL 0x4080 +#define VOL_mmDCP4_DC_LUT_CONTROL 0x4280 +#define VOL_mmDCP5_DC_LUT_CONTROL 0x4480 +#define VOL_mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define VOL_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define VOL_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 +#define VOL_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 +#define VOL_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define VOL_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 +#define VOL_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 +#define VOL_mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define VOL_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define VOL_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 +#define VOL_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 +#define VOL_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define VOL_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 +#define VOL_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 +#define VOL_mmDC_LUT_BLACK_OFFSET_RED 0x1a83 +#define VOL_mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 +#define VOL_mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 +#define VOL_mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 +#define VOL_mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define VOL_mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 +#define VOL_mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 +#define VOL_mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define VOL_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define VOL_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 +#define VOL_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 +#define VOL_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define VOL_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 +#define VOL_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 +#define VOL_mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define VOL_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define VOL_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 +#define VOL_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 +#define VOL_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define VOL_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 +#define VOL_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 +#define VOL_mmDC_LUT_WHITE_OFFSET_RED 0x1a86 +#define VOL_mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 +#define VOL_mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 +#define VOL_mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 +#define VOL_mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define VOL_mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 +#define VOL_mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 +#define VOL_mmDCP_CRC_CONTROL 0x1a87 +#define VOL_mmDCP0_DCP_CRC_CONTROL 0x1a87 +#define VOL_mmDCP1_DCP_CRC_CONTROL 0x1c87 +#define VOL_mmDCP2_DCP_CRC_CONTROL 0x1e87 +#define VOL_mmDCP3_DCP_CRC_CONTROL 0x4087 +#define VOL_mmDCP4_DCP_CRC_CONTROL 0x4287 +#define VOL_mmDCP5_DCP_CRC_CONTROL 0x4487 +#define VOL_mmDCP_CRC_MASK 0x1a88 +#define VOL_mmDCP0_DCP_CRC_MASK 0x1a88 +#define VOL_mmDCP1_DCP_CRC_MASK 0x1c88 +#define VOL_mmDCP2_DCP_CRC_MASK 0x1e88 +#define VOL_mmDCP3_DCP_CRC_MASK 0x4088 +#define VOL_mmDCP4_DCP_CRC_MASK 0x4288 +#define VOL_mmDCP5_DCP_CRC_MASK 0x4488 +#define VOL_mmDCP_CRC_CURRENT 0x1a89 +#define VOL_mmDCP0_DCP_CRC_CURRENT 0x1a89 +#define VOL_mmDCP1_DCP_CRC_CURRENT 0x1c89 +#define VOL_mmDCP2_DCP_CRC_CURRENT 0x1e89 +#define VOL_mmDCP3_DCP_CRC_CURRENT 0x4089 +#define VOL_mmDCP4_DCP_CRC_CURRENT 0x4289 +#define VOL_mmDCP5_DCP_CRC_CURRENT 0x4489 +#define VOL_mmDCP_CRC_LAST 0x1a8b +#define VOL_mmDCP0_DCP_CRC_LAST 0x1a8b +#define VOL_mmDCP1_DCP_CRC_LAST 0x1c8b +#define VOL_mmDCP2_DCP_CRC_LAST 0x1e8b +#define VOL_mmDCP3_DCP_CRC_LAST 0x408b +#define VOL_mmDCP4_DCP_CRC_LAST 0x428b +#define VOL_mmDCP5_DCP_CRC_LAST 0x448b +#define VOL_mmDCP_DEBUG 0x1a8d +#define VOL_mmDCP0_DCP_DEBUG 0x1a8d +#define VOL_mmDCP1_DCP_DEBUG 0x1c8d +#define VOL_mmDCP2_DCP_DEBUG 0x1e8d +#define VOL_mmDCP3_DCP_DEBUG 0x408d +#define VOL_mmDCP4_DCP_DEBUG 0x428d +#define VOL_mmDCP5_DCP_DEBUG 0x448d +#define VOL_mmGRPH_FLIP_RATE_CNTL 0x1a8e +#define VOL_mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e +#define VOL_mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e +#define VOL_mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e +#define VOL_mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e +#define VOL_mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e +#define VOL_mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e +#define VOL_mmDCP_GSL_CONTROL 0x1a90 +#define VOL_mmDCP0_DCP_GSL_CONTROL 0x1a90 +#define VOL_mmDCP1_DCP_GSL_CONTROL 0x1c90 +#define VOL_mmDCP2_DCP_GSL_CONTROL 0x1e90 +#define VOL_mmDCP3_DCP_GSL_CONTROL 0x4090 +#define VOL_mmDCP4_DCP_GSL_CONTROL 0x4290 +#define VOL_mmDCP5_DCP_GSL_CONTROL 0x4490 +#define VOL_mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define VOL_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define VOL_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 +#define VOL_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 +#define VOL_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define VOL_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 +#define VOL_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 +#define VOL_mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92 +#define VOL_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92 +#define VOL_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1c92 +#define VOL_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x1e92 +#define VOL_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 +#define VOL_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4292 +#define VOL_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4492 +#define VOL_mmOVL_STEREOSYNC_FLIP 0x1a93 +#define VOL_mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93 +#define VOL_mmDCP1_OVL_STEREOSYNC_FLIP 0x1c93 +#define VOL_mmDCP2_OVL_STEREOSYNC_FLIP 0x1e93 +#define VOL_mmDCP3_OVL_STEREOSYNC_FLIP 0x4093 +#define VOL_mmDCP4_OVL_STEREOSYNC_FLIP 0x4293 +#define VOL_mmDCP5_OVL_STEREOSYNC_FLIP 0x4493 +#define VOL_mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 +#define VOL_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 +#define VOL_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c94 +#define VOL_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e94 +#define VOL_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 +#define VOL_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4294 +#define VOL_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4494 +#define VOL_mmDCP_TEST_DEBUG_INDEX 0x1a95 +#define VOL_mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 +#define VOL_mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 +#define VOL_mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 +#define VOL_mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 +#define VOL_mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 +#define VOL_mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 +#define VOL_mmDCP_TEST_DEBUG_DATA 0x1a96 +#define VOL_mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 +#define VOL_mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 +#define VOL_mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 +#define VOL_mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 +#define VOL_mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 +#define VOL_mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 +#define VOL_mmGRPH_STEREOSYNC_FLIP 0x1a97 +#define VOL_mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 +#define VOL_mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 +#define VOL_mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 +#define VOL_mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 +#define VOL_mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 +#define VOL_mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 +#define VOL_mmDCP_DEBUG2 0x1a98 +#define VOL_mmDCP0_DCP_DEBUG2 0x1a98 +#define VOL_mmDCP1_DCP_DEBUG2 0x1c98 +#define VOL_mmDCP2_DCP_DEBUG2 0x1e98 +#define VOL_mmDCP3_DCP_DEBUG2 0x4098 +#define VOL_mmDCP4_DCP_DEBUG2 0x4298 +#define VOL_mmDCP5_DCP_DEBUG2 0x4498 +#define VOL_mmHW_ROTATION 0x1a9e +#define VOL_mmDCP0_HW_ROTATION 0x1a9e +#define VOL_mmDCP1_HW_ROTATION 0x1c9e +#define VOL_mmDCP2_HW_ROTATION 0x1e9e +#define VOL_mmDCP3_HW_ROTATION 0x409e +#define VOL_mmDCP4_HW_ROTATION 0x429e +#define VOL_mmDCP5_HW_ROTATION 0x449e +#define VOL_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define VOL_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define VOL_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f +#define VOL_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f +#define VOL_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f +#define VOL_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f +#define VOL_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f +#define VOL_mmREGAMMA_CONTROL 0x1aa0 +#define VOL_mmDCP0_REGAMMA_CONTROL 0x1aa0 +#define VOL_mmDCP1_REGAMMA_CONTROL 0x1ca0 +#define VOL_mmDCP2_REGAMMA_CONTROL 0x1ea0 +#define VOL_mmDCP3_REGAMMA_CONTROL 0x40a0 +#define VOL_mmDCP4_REGAMMA_CONTROL 0x42a0 +#define VOL_mmDCP5_REGAMMA_CONTROL 0x44a0 +#define VOL_mmREGAMMA_LUT_INDEX 0x1aa1 +#define VOL_mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 +#define VOL_mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 +#define VOL_mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 +#define VOL_mmDCP3_REGAMMA_LUT_INDEX 0x40a1 +#define VOL_mmDCP4_REGAMMA_LUT_INDEX 0x42a1 +#define VOL_mmDCP5_REGAMMA_LUT_INDEX 0x44a1 +#define VOL_mmREGAMMA_LUT_DATA 0x1aa2 +#define VOL_mmDCP0_REGAMMA_LUT_DATA 0x1aa2 +#define VOL_mmDCP1_REGAMMA_LUT_DATA 0x1ca2 +#define VOL_mmDCP2_REGAMMA_LUT_DATA 0x1ea2 +#define VOL_mmDCP3_REGAMMA_LUT_DATA 0x40a2 +#define VOL_mmDCP4_REGAMMA_LUT_DATA 0x42a2 +#define VOL_mmDCP5_REGAMMA_LUT_DATA 0x44a2 +#define VOL_mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define VOL_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define VOL_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 +#define VOL_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 +#define VOL_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 +#define VOL_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 +#define VOL_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 +#define VOL_mmREGAMMA_CNTLA_START_CNTL 0x1aa4 +#define VOL_mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 +#define VOL_mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 +#define VOL_mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 +#define VOL_mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 +#define VOL_mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 +#define VOL_mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 +#define VOL_mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define VOL_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define VOL_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 +#define VOL_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 +#define VOL_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 +#define VOL_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 +#define VOL_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 +#define VOL_mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define VOL_mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define VOL_mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 +#define VOL_mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 +#define VOL_mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 +#define VOL_mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 +#define VOL_mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 +#define VOL_mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define VOL_mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define VOL_mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 +#define VOL_mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 +#define VOL_mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 +#define VOL_mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 +#define VOL_mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 +#define VOL_mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 +#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 +#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 +#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 +#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 +#define VOL_mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 +#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 +#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 +#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 +#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 +#define VOL_mmREGAMMA_CNTLA_REGION_4_5 0x1aaa +#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa +#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa +#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa +#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa +#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa +#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa +#define VOL_mmREGAMMA_CNTLA_REGION_6_7 0x1aab +#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab +#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab +#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab +#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab +#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab +#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab +#define VOL_mmREGAMMA_CNTLA_REGION_8_9 0x1aac +#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac +#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac +#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac +#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac +#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac +#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac +#define VOL_mmREGAMMA_CNTLA_REGION_10_11 0x1aad +#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad +#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad +#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead +#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad +#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad +#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad +#define VOL_mmREGAMMA_CNTLA_REGION_12_13 0x1aae +#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae +#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae +#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae +#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae +#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae +#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae +#define VOL_mmREGAMMA_CNTLA_REGION_14_15 0x1aaf +#define VOL_mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf +#define VOL_mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf +#define VOL_mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf +#define VOL_mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af +#define VOL_mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af +#define VOL_mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af +#define VOL_mmREGAMMA_CNTLB_START_CNTL 0x1ab0 +#define VOL_mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 +#define VOL_mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 +#define VOL_mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 +#define VOL_mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 +#define VOL_mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 +#define VOL_mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 +#define VOL_mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define VOL_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define VOL_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 +#define VOL_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 +#define VOL_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 +#define VOL_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 +#define VOL_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 +#define VOL_mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define VOL_mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define VOL_mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 +#define VOL_mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 +#define VOL_mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 +#define VOL_mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 +#define VOL_mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 +#define VOL_mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define VOL_mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define VOL_mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 +#define VOL_mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 +#define VOL_mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 +#define VOL_mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 +#define VOL_mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 +#define VOL_mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 +#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 +#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 +#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 +#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 +#define VOL_mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 +#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 +#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 +#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 +#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 +#define VOL_mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 +#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 +#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 +#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 +#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 +#define VOL_mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 +#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 +#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 +#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 +#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 +#define VOL_mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 +#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 +#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 +#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 +#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 +#define VOL_mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 +#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 +#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 +#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 +#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 +#define VOL_mmREGAMMA_CNTLB_REGION_12_13 0x1aba +#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba +#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba +#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba +#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba +#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba +#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba +#define VOL_mmREGAMMA_CNTLB_REGION_14_15 0x1abb +#define VOL_mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb +#define VOL_mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb +#define VOL_mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb +#define VOL_mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb +#define VOL_mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb +#define VOL_mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb +#define VOL_mmALPHA_CONTROL 0x1abc +#define VOL_mmDCP0_ALPHA_CONTROL 0x1abc +#define VOL_mmDCP1_ALPHA_CONTROL 0x1cbc +#define VOL_mmDCP2_ALPHA_CONTROL 0x1ebc +#define VOL_mmDCP3_ALPHA_CONTROL 0x40bc +#define VOL_mmDCP4_ALPHA_CONTROL 0x42bc +#define VOL_mmDCP5_ALPHA_CONTROL 0x44bc +#define VOL_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define VOL_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define VOL_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd +#define VOL_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd +#define VOL_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd +#define VOL_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd +#define VOL_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd +#define VOL_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define VOL_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define VOL_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe +#define VOL_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe +#define VOL_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be +#define VOL_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be +#define VOL_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be +#define VOL_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define VOL_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define VOL_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf +#define VOL_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf +#define VOL_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf +#define VOL_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf +#define VOL_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf +#define VOL_mmDIG_FE_CNTL 0x4a00 +#define VOL_mmDIG0_DIG_FE_CNTL 0x4a00 +#define VOL_mmDIG1_DIG_FE_CNTL 0x4b00 +#define VOL_mmDIG2_DIG_FE_CNTL 0x4c00 +#define VOL_mmDIG3_DIG_FE_CNTL 0x4d00 +#define VOL_mmDIG4_DIG_FE_CNTL 0x4e00 +#define VOL_mmDIG5_DIG_FE_CNTL 0x4f00 +#define VOL_mmDIG6_DIG_FE_CNTL 0x5400 +#define VOL_mmDIG_OUTPUT_CRC_CNTL 0x4a01 +#define VOL_mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 +#define VOL_mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 +#define VOL_mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 +#define VOL_mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 +#define VOL_mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 +#define VOL_mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 +#define VOL_mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 +#define VOL_mmDIG_OUTPUT_CRC_RESULT 0x4a02 +#define VOL_mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 +#define VOL_mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 +#define VOL_mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 +#define VOL_mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 +#define VOL_mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 +#define VOL_mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 +#define VOL_mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 +#define VOL_mmDIG_CLOCK_PATTERN 0x4a03 +#define VOL_mmDIG0_DIG_CLOCK_PATTERN 0x4a03 +#define VOL_mmDIG1_DIG_CLOCK_PATTERN 0x4b03 +#define VOL_mmDIG2_DIG_CLOCK_PATTERN 0x4c03 +#define VOL_mmDIG3_DIG_CLOCK_PATTERN 0x4d03 +#define VOL_mmDIG4_DIG_CLOCK_PATTERN 0x4e03 +#define VOL_mmDIG5_DIG_CLOCK_PATTERN 0x4f03 +#define VOL_mmDIG6_DIG_CLOCK_PATTERN 0x5403 +#define VOL_mmDIG_TEST_PATTERN 0x4a04 +#define VOL_mmDIG0_DIG_TEST_PATTERN 0x4a04 +#define VOL_mmDIG1_DIG_TEST_PATTERN 0x4b04 +#define VOL_mmDIG2_DIG_TEST_PATTERN 0x4c04 +#define VOL_mmDIG3_DIG_TEST_PATTERN 0x4d04 +#define VOL_mmDIG4_DIG_TEST_PATTERN 0x4e04 +#define VOL_mmDIG5_DIG_TEST_PATTERN 0x4f04 +#define VOL_mmDIG6_DIG_TEST_PATTERN 0x5404 +#define VOL_mmDIG_RANDOM_PATTERN_SEED 0x4a05 +#define VOL_mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 +#define VOL_mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 +#define VOL_mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 +#define VOL_mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 +#define VOL_mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 +#define VOL_mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 +#define VOL_mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 +#define VOL_mmDIG_FIFO_STATUS 0x4a06 +#define VOL_mmDIG0_DIG_FIFO_STATUS 0x4a06 +#define VOL_mmDIG1_DIG_FIFO_STATUS 0x4b06 +#define VOL_mmDIG2_DIG_FIFO_STATUS 0x4c06 +#define VOL_mmDIG3_DIG_FIFO_STATUS 0x4d06 +#define VOL_mmDIG4_DIG_FIFO_STATUS 0x4e06 +#define VOL_mmDIG5_DIG_FIFO_STATUS 0x4f06 +#define VOL_mmDIG6_DIG_FIFO_STATUS 0x5406 +#define VOL_mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define VOL_mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define VOL_mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 +#define VOL_mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 +#define VOL_mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 +#define VOL_mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 +#define VOL_mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 +#define VOL_mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 +#define VOL_mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define VOL_mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define VOL_mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 +#define VOL_mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 +#define VOL_mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 +#define VOL_mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 +#define VOL_mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 +#define VOL_mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 +#define VOL_mmHDMI_CONTROL 0x4a09 +#define VOL_mmDIG0_HDMI_CONTROL 0x4a09 +#define VOL_mmDIG1_HDMI_CONTROL 0x4b09 +#define VOL_mmDIG2_HDMI_CONTROL 0x4c09 +#define VOL_mmDIG3_HDMI_CONTROL 0x4d09 +#define VOL_mmDIG4_HDMI_CONTROL 0x4e09 +#define VOL_mmDIG5_HDMI_CONTROL 0x4f09 +#define VOL_mmDIG6_HDMI_CONTROL 0x5409 +#define VOL_mmHDMI_STATUS 0x4a0a +#define VOL_mmDIG0_HDMI_STATUS 0x4a0a +#define VOL_mmDIG1_HDMI_STATUS 0x4b0a +#define VOL_mmDIG2_HDMI_STATUS 0x4c0a +#define VOL_mmDIG3_HDMI_STATUS 0x4d0a +#define VOL_mmDIG4_HDMI_STATUS 0x4e0a +#define VOL_mmDIG5_HDMI_STATUS 0x4f0a +#define VOL_mmDIG6_HDMI_STATUS 0x540a +#define VOL_mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define VOL_mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define VOL_mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b +#define VOL_mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b +#define VOL_mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b +#define VOL_mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b +#define VOL_mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b +#define VOL_mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b +#define VOL_mmHDMI_ACR_PACKET_CONTROL 0x4a0c +#define VOL_mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c +#define VOL_mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c +#define VOL_mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c +#define VOL_mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c +#define VOL_mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c +#define VOL_mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c +#define VOL_mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c +#define VOL_mmHDMI_VBI_PACKET_CONTROL 0x4a0d +#define VOL_mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d +#define VOL_mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d +#define VOL_mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d +#define VOL_mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d +#define VOL_mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d +#define VOL_mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d +#define VOL_mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d +#define VOL_mmHDMI_INFOFRAME_CONTROL0 0x4a0e +#define VOL_mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e +#define VOL_mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e +#define VOL_mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e +#define VOL_mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e +#define VOL_mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e +#define VOL_mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e +#define VOL_mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e +#define VOL_mmHDMI_INFOFRAME_CONTROL1 0x4a0f +#define VOL_mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f +#define VOL_mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f +#define VOL_mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f +#define VOL_mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f +#define VOL_mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f +#define VOL_mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f +#define VOL_mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f +#define VOL_mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define VOL_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define VOL_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 +#define VOL_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 +#define VOL_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 +#define VOL_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 +#define VOL_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 +#define VOL_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 +#define VOL_mmAFMT_INTERRUPT_STATUS 0x4a11 +#define VOL_mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 +#define VOL_mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 +#define VOL_mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 +#define VOL_mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 +#define VOL_mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 +#define VOL_mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 +#define VOL_mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 +#define VOL_mmHDMI_GC 0x4a13 +#define VOL_mmDIG0_HDMI_GC 0x4a13 +#define VOL_mmDIG1_HDMI_GC 0x4b13 +#define VOL_mmDIG2_HDMI_GC 0x4c13 +#define VOL_mmDIG3_HDMI_GC 0x4d13 +#define VOL_mmDIG4_HDMI_GC 0x4e13 +#define VOL_mmDIG5_HDMI_GC 0x4f13 +#define VOL_mmDIG6_HDMI_GC 0x5413 +#define VOL_mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define VOL_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define VOL_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 +#define VOL_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 +#define VOL_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 +#define VOL_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 +#define VOL_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 +#define VOL_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 +#define VOL_mmAFMT_ISRC1_0 0x4a15 +#define VOL_mmDIG0_AFMT_ISRC1_0 0x4a15 +#define VOL_mmDIG1_AFMT_ISRC1_0 0x4b15 +#define VOL_mmDIG2_AFMT_ISRC1_0 0x4c15 +#define VOL_mmDIG3_AFMT_ISRC1_0 0x4d15 +#define VOL_mmDIG4_AFMT_ISRC1_0 0x4e15 +#define VOL_mmDIG5_AFMT_ISRC1_0 0x4f15 +#define VOL_mmDIG6_AFMT_ISRC1_0 0x5415 +#define VOL_mmAFMT_ISRC1_1 0x4a16 +#define VOL_mmDIG0_AFMT_ISRC1_1 0x4a16 +#define VOL_mmDIG1_AFMT_ISRC1_1 0x4b16 +#define VOL_mmDIG2_AFMT_ISRC1_1 0x4c16 +#define VOL_mmDIG3_AFMT_ISRC1_1 0x4d16 +#define VOL_mmDIG4_AFMT_ISRC1_1 0x4e16 +#define VOL_mmDIG5_AFMT_ISRC1_1 0x4f16 +#define VOL_mmDIG6_AFMT_ISRC1_1 0x5416 +#define VOL_mmAFMT_ISRC1_2 0x4a17 +#define VOL_mmDIG0_AFMT_ISRC1_2 0x4a17 +#define VOL_mmDIG1_AFMT_ISRC1_2 0x4b17 +#define VOL_mmDIG2_AFMT_ISRC1_2 0x4c17 +#define VOL_mmDIG3_AFMT_ISRC1_2 0x4d17 +#define VOL_mmDIG4_AFMT_ISRC1_2 0x4e17 +#define VOL_mmDIG5_AFMT_ISRC1_2 0x4f17 +#define VOL_mmDIG6_AFMT_ISRC1_2 0x5417 +#define VOL_mmAFMT_ISRC1_3 0x4a18 +#define VOL_mmDIG0_AFMT_ISRC1_3 0x4a18 +#define VOL_mmDIG1_AFMT_ISRC1_3 0x4b18 +#define VOL_mmDIG2_AFMT_ISRC1_3 0x4c18 +#define VOL_mmDIG3_AFMT_ISRC1_3 0x4d18 +#define VOL_mmDIG4_AFMT_ISRC1_3 0x4e18 +#define VOL_mmDIG5_AFMT_ISRC1_3 0x4f18 +#define VOL_mmDIG6_AFMT_ISRC1_3 0x5418 +#define VOL_mmAFMT_ISRC1_4 0x4a19 +#define VOL_mmDIG0_AFMT_ISRC1_4 0x4a19 +#define VOL_mmDIG1_AFMT_ISRC1_4 0x4b19 +#define VOL_mmDIG2_AFMT_ISRC1_4 0x4c19 +#define VOL_mmDIG3_AFMT_ISRC1_4 0x4d19 +#define VOL_mmDIG4_AFMT_ISRC1_4 0x4e19 +#define VOL_mmDIG5_AFMT_ISRC1_4 0x4f19 +#define VOL_mmDIG6_AFMT_ISRC1_4 0x5419 +#define VOL_mmAFMT_ISRC2_0 0x4a1a +#define VOL_mmDIG0_AFMT_ISRC2_0 0x4a1a +#define VOL_mmDIG1_AFMT_ISRC2_0 0x4b1a +#define VOL_mmDIG2_AFMT_ISRC2_0 0x4c1a +#define VOL_mmDIG3_AFMT_ISRC2_0 0x4d1a +#define VOL_mmDIG4_AFMT_ISRC2_0 0x4e1a +#define VOL_mmDIG5_AFMT_ISRC2_0 0x4f1a +#define VOL_mmDIG6_AFMT_ISRC2_0 0x541a +#define VOL_mmAFMT_ISRC2_1 0x4a1b +#define VOL_mmDIG0_AFMT_ISRC2_1 0x4a1b +#define VOL_mmDIG1_AFMT_ISRC2_1 0x4b1b +#define VOL_mmDIG2_AFMT_ISRC2_1 0x4c1b +#define VOL_mmDIG3_AFMT_ISRC2_1 0x4d1b +#define VOL_mmDIG4_AFMT_ISRC2_1 0x4e1b +#define VOL_mmDIG5_AFMT_ISRC2_1 0x4f1b +#define VOL_mmDIG6_AFMT_ISRC2_1 0x541b +#define VOL_mmAFMT_ISRC2_2 0x4a1c +#define VOL_mmDIG0_AFMT_ISRC2_2 0x4a1c +#define VOL_mmDIG1_AFMT_ISRC2_2 0x4b1c +#define VOL_mmDIG2_AFMT_ISRC2_2 0x4c1c +#define VOL_mmDIG3_AFMT_ISRC2_2 0x4d1c +#define VOL_mmDIG4_AFMT_ISRC2_2 0x4e1c +#define VOL_mmDIG5_AFMT_ISRC2_2 0x4f1c +#define VOL_mmDIG6_AFMT_ISRC2_2 0x541c +#define VOL_mmAFMT_ISRC2_3 0x4a1d +#define VOL_mmDIG0_AFMT_ISRC2_3 0x4a1d +#define VOL_mmDIG1_AFMT_ISRC2_3 0x4b1d +#define VOL_mmDIG2_AFMT_ISRC2_3 0x4c1d +#define VOL_mmDIG3_AFMT_ISRC2_3 0x4d1d +#define VOL_mmDIG4_AFMT_ISRC2_3 0x4e1d +#define VOL_mmDIG5_AFMT_ISRC2_3 0x4f1d +#define VOL_mmDIG6_AFMT_ISRC2_3 0x541d +#define VOL_mmAFMT_AVI_INFO0 0x4a1e +#define VOL_mmDIG0_AFMT_AVI_INFO0 0x4a1e +#define VOL_mmDIG1_AFMT_AVI_INFO0 0x4b1e +#define VOL_mmDIG2_AFMT_AVI_INFO0 0x4c1e +#define VOL_mmDIG3_AFMT_AVI_INFO0 0x4d1e +#define VOL_mmDIG4_AFMT_AVI_INFO0 0x4e1e +#define VOL_mmDIG5_AFMT_AVI_INFO0 0x4f1e +#define VOL_mmDIG6_AFMT_AVI_INFO0 0x541e +#define VOL_mmAFMT_AVI_INFO1 0x4a1f +#define VOL_mmDIG0_AFMT_AVI_INFO1 0x4a1f +#define VOL_mmDIG1_AFMT_AVI_INFO1 0x4b1f +#define VOL_mmDIG2_AFMT_AVI_INFO1 0x4c1f +#define VOL_mmDIG3_AFMT_AVI_INFO1 0x4d1f +#define VOL_mmDIG4_AFMT_AVI_INFO1 0x4e1f +#define VOL_mmDIG5_AFMT_AVI_INFO1 0x4f1f +#define VOL_mmDIG6_AFMT_AVI_INFO1 0x541f +#define VOL_mmAFMT_AVI_INFO2 0x4a20 +#define VOL_mmDIG0_AFMT_AVI_INFO2 0x4a20 +#define VOL_mmDIG1_AFMT_AVI_INFO2 0x4b20 +#define VOL_mmDIG2_AFMT_AVI_INFO2 0x4c20 +#define VOL_mmDIG3_AFMT_AVI_INFO2 0x4d20 +#define VOL_mmDIG4_AFMT_AVI_INFO2 0x4e20 +#define VOL_mmDIG5_AFMT_AVI_INFO2 0x4f20 +#define VOL_mmDIG6_AFMT_AVI_INFO2 0x5420 +#define VOL_mmAFMT_AVI_INFO3 0x4a21 +#define VOL_mmDIG0_AFMT_AVI_INFO3 0x4a21 +#define VOL_mmDIG1_AFMT_AVI_INFO3 0x4b21 +#define VOL_mmDIG2_AFMT_AVI_INFO3 0x4c21 +#define VOL_mmDIG3_AFMT_AVI_INFO3 0x4d21 +#define VOL_mmDIG4_AFMT_AVI_INFO3 0x4e21 +#define VOL_mmDIG5_AFMT_AVI_INFO3 0x4f21 +#define VOL_mmDIG6_AFMT_AVI_INFO3 0x5421 +#define VOL_mmAFMT_MPEG_INFO0 0x4a22 +#define VOL_mmDIG0_AFMT_MPEG_INFO0 0x4a22 +#define VOL_mmDIG1_AFMT_MPEG_INFO0 0x4b22 +#define VOL_mmDIG2_AFMT_MPEG_INFO0 0x4c22 +#define VOL_mmDIG3_AFMT_MPEG_INFO0 0x4d22 +#define VOL_mmDIG4_AFMT_MPEG_INFO0 0x4e22 +#define VOL_mmDIG5_AFMT_MPEG_INFO0 0x4f22 +#define VOL_mmDIG6_AFMT_MPEG_INFO0 0x5422 +#define VOL_mmAFMT_MPEG_INFO1 0x4a23 +#define VOL_mmDIG0_AFMT_MPEG_INFO1 0x4a23 +#define VOL_mmDIG1_AFMT_MPEG_INFO1 0x4b23 +#define VOL_mmDIG2_AFMT_MPEG_INFO1 0x4c23 +#define VOL_mmDIG3_AFMT_MPEG_INFO1 0x4d23 +#define VOL_mmDIG4_AFMT_MPEG_INFO1 0x4e23 +#define VOL_mmDIG5_AFMT_MPEG_INFO1 0x4f23 +#define VOL_mmDIG6_AFMT_MPEG_INFO1 0x5423 +#define VOL_mmAFMT_GENERIC_HDR 0x4a24 +#define VOL_mmDIG0_AFMT_GENERIC_HDR 0x4a24 +#define VOL_mmDIG1_AFMT_GENERIC_HDR 0x4b24 +#define VOL_mmDIG2_AFMT_GENERIC_HDR 0x4c24 +#define VOL_mmDIG3_AFMT_GENERIC_HDR 0x4d24 +#define VOL_mmDIG4_AFMT_GENERIC_HDR 0x4e24 +#define VOL_mmDIG5_AFMT_GENERIC_HDR 0x4f24 +#define VOL_mmDIG6_AFMT_GENERIC_HDR 0x5424 +#define VOL_mmAFMT_GENERIC_0 0x4a25 +#define VOL_mmDIG0_AFMT_GENERIC_0 0x4a25 +#define VOL_mmDIG1_AFMT_GENERIC_0 0x4b25 +#define VOL_mmDIG2_AFMT_GENERIC_0 0x4c25 +#define VOL_mmDIG3_AFMT_GENERIC_0 0x4d25 +#define VOL_mmDIG4_AFMT_GENERIC_0 0x4e25 +#define VOL_mmDIG5_AFMT_GENERIC_0 0x4f25 +#define VOL_mmDIG6_AFMT_GENERIC_0 0x5425 +#define VOL_mmAFMT_GENERIC_1 0x4a26 +#define VOL_mmDIG0_AFMT_GENERIC_1 0x4a26 +#define VOL_mmDIG1_AFMT_GENERIC_1 0x4b26 +#define VOL_mmDIG2_AFMT_GENERIC_1 0x4c26 +#define VOL_mmDIG3_AFMT_GENERIC_1 0x4d26 +#define VOL_mmDIG4_AFMT_GENERIC_1 0x4e26 +#define VOL_mmDIG5_AFMT_GENERIC_1 0x4f26 +#define VOL_mmDIG6_AFMT_GENERIC_1 0x5426 +#define VOL_mmAFMT_GENERIC_2 0x4a27 +#define VOL_mmDIG0_AFMT_GENERIC_2 0x4a27 +#define VOL_mmDIG1_AFMT_GENERIC_2 0x4b27 +#define VOL_mmDIG2_AFMT_GENERIC_2 0x4c27 +#define VOL_mmDIG3_AFMT_GENERIC_2 0x4d27 +#define VOL_mmDIG4_AFMT_GENERIC_2 0x4e27 +#define VOL_mmDIG5_AFMT_GENERIC_2 0x4f27 +#define VOL_mmDIG6_AFMT_GENERIC_2 0x5427 +#define VOL_mmAFMT_GENERIC_3 0x4a28 +#define VOL_mmDIG0_AFMT_GENERIC_3 0x4a28 +#define VOL_mmDIG1_AFMT_GENERIC_3 0x4b28 +#define VOL_mmDIG2_AFMT_GENERIC_3 0x4c28 +#define VOL_mmDIG3_AFMT_GENERIC_3 0x4d28 +#define VOL_mmDIG4_AFMT_GENERIC_3 0x4e28 +#define VOL_mmDIG5_AFMT_GENERIC_3 0x4f28 +#define VOL_mmDIG6_AFMT_GENERIC_3 0x5428 +#define VOL_mmAFMT_GENERIC_4 0x4a29 +#define VOL_mmDIG0_AFMT_GENERIC_4 0x4a29 +#define VOL_mmDIG1_AFMT_GENERIC_4 0x4b29 +#define VOL_mmDIG2_AFMT_GENERIC_4 0x4c29 +#define VOL_mmDIG3_AFMT_GENERIC_4 0x4d29 +#define VOL_mmDIG4_AFMT_GENERIC_4 0x4e29 +#define VOL_mmDIG5_AFMT_GENERIC_4 0x4f29 +#define VOL_mmDIG6_AFMT_GENERIC_4 0x5429 +#define VOL_mmAFMT_GENERIC_5 0x4a2a +#define VOL_mmDIG0_AFMT_GENERIC_5 0x4a2a +#define VOL_mmDIG1_AFMT_GENERIC_5 0x4b2a +#define VOL_mmDIG2_AFMT_GENERIC_5 0x4c2a +#define VOL_mmDIG3_AFMT_GENERIC_5 0x4d2a +#define VOL_mmDIG4_AFMT_GENERIC_5 0x4e2a +#define VOL_mmDIG5_AFMT_GENERIC_5 0x4f2a +#define VOL_mmDIG6_AFMT_GENERIC_5 0x542a +#define VOL_mmAFMT_GENERIC_6 0x4a2b +#define VOL_mmDIG0_AFMT_GENERIC_6 0x4a2b +#define VOL_mmDIG1_AFMT_GENERIC_6 0x4b2b +#define VOL_mmDIG2_AFMT_GENERIC_6 0x4c2b +#define VOL_mmDIG3_AFMT_GENERIC_6 0x4d2b +#define VOL_mmDIG4_AFMT_GENERIC_6 0x4e2b +#define VOL_mmDIG5_AFMT_GENERIC_6 0x4f2b +#define VOL_mmDIG6_AFMT_GENERIC_6 0x542b +#define VOL_mmAFMT_GENERIC_7 0x4a2c +#define VOL_mmDIG0_AFMT_GENERIC_7 0x4a2c +#define VOL_mmDIG1_AFMT_GENERIC_7 0x4b2c +#define VOL_mmDIG2_AFMT_GENERIC_7 0x4c2c +#define VOL_mmDIG3_AFMT_GENERIC_7 0x4d2c +#define VOL_mmDIG4_AFMT_GENERIC_7 0x4e2c +#define VOL_mmDIG5_AFMT_GENERIC_7 0x4f2c +#define VOL_mmDIG6_AFMT_GENERIC_7 0x542c +#define VOL_mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define VOL_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define VOL_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d +#define VOL_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d +#define VOL_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d +#define VOL_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d +#define VOL_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d +#define VOL_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d +#define VOL_mmHDMI_ACR_32_0 0x4a2e +#define VOL_mmDIG0_HDMI_ACR_32_0 0x4a2e +#define VOL_mmDIG1_HDMI_ACR_32_0 0x4b2e +#define VOL_mmDIG2_HDMI_ACR_32_0 0x4c2e +#define VOL_mmDIG3_HDMI_ACR_32_0 0x4d2e +#define VOL_mmDIG4_HDMI_ACR_32_0 0x4e2e +#define VOL_mmDIG5_HDMI_ACR_32_0 0x4f2e +#define VOL_mmDIG6_HDMI_ACR_32_0 0x542e +#define VOL_mmHDMI_ACR_32_1 0x4a2f +#define VOL_mmDIG0_HDMI_ACR_32_1 0x4a2f +#define VOL_mmDIG1_HDMI_ACR_32_1 0x4b2f +#define VOL_mmDIG2_HDMI_ACR_32_1 0x4c2f +#define VOL_mmDIG3_HDMI_ACR_32_1 0x4d2f +#define VOL_mmDIG4_HDMI_ACR_32_1 0x4e2f +#define VOL_mmDIG5_HDMI_ACR_32_1 0x4f2f +#define VOL_mmDIG6_HDMI_ACR_32_1 0x542f +#define VOL_mmHDMI_ACR_44_0 0x4a30 +#define VOL_mmDIG0_HDMI_ACR_44_0 0x4a30 +#define VOL_mmDIG1_HDMI_ACR_44_0 0x4b30 +#define VOL_mmDIG2_HDMI_ACR_44_0 0x4c30 +#define VOL_mmDIG3_HDMI_ACR_44_0 0x4d30 +#define VOL_mmDIG4_HDMI_ACR_44_0 0x4e30 +#define VOL_mmDIG5_HDMI_ACR_44_0 0x4f30 +#define VOL_mmDIG6_HDMI_ACR_44_0 0x5430 +#define VOL_mmHDMI_ACR_44_1 0x4a31 +#define VOL_mmDIG0_HDMI_ACR_44_1 0x4a31 +#define VOL_mmDIG1_HDMI_ACR_44_1 0x4b31 +#define VOL_mmDIG2_HDMI_ACR_44_1 0x4c31 +#define VOL_mmDIG3_HDMI_ACR_44_1 0x4d31 +#define VOL_mmDIG4_HDMI_ACR_44_1 0x4e31 +#define VOL_mmDIG5_HDMI_ACR_44_1 0x4f31 +#define VOL_mmDIG6_HDMI_ACR_44_1 0x5431 +#define VOL_mmHDMI_ACR_48_0 0x4a32 +#define VOL_mmDIG0_HDMI_ACR_48_0 0x4a32 +#define VOL_mmDIG1_HDMI_ACR_48_0 0x4b32 +#define VOL_mmDIG2_HDMI_ACR_48_0 0x4c32 +#define VOL_mmDIG3_HDMI_ACR_48_0 0x4d32 +#define VOL_mmDIG4_HDMI_ACR_48_0 0x4e32 +#define VOL_mmDIG5_HDMI_ACR_48_0 0x4f32 +#define VOL_mmDIG6_HDMI_ACR_48_0 0x5432 +#define VOL_mmHDMI_ACR_48_1 0x4a33 +#define VOL_mmDIG0_HDMI_ACR_48_1 0x4a33 +#define VOL_mmDIG1_HDMI_ACR_48_1 0x4b33 +#define VOL_mmDIG2_HDMI_ACR_48_1 0x4c33 +#define VOL_mmDIG3_HDMI_ACR_48_1 0x4d33 +#define VOL_mmDIG4_HDMI_ACR_48_1 0x4e33 +#define VOL_mmDIG5_HDMI_ACR_48_1 0x4f33 +#define VOL_mmDIG6_HDMI_ACR_48_1 0x5433 +#define VOL_mmHDMI_ACR_STATUS_0 0x4a34 +#define VOL_mmDIG0_HDMI_ACR_STATUS_0 0x4a34 +#define VOL_mmDIG1_HDMI_ACR_STATUS_0 0x4b34 +#define VOL_mmDIG2_HDMI_ACR_STATUS_0 0x4c34 +#define VOL_mmDIG3_HDMI_ACR_STATUS_0 0x4d34 +#define VOL_mmDIG4_HDMI_ACR_STATUS_0 0x4e34 +#define VOL_mmDIG5_HDMI_ACR_STATUS_0 0x4f34 +#define VOL_mmDIG6_HDMI_ACR_STATUS_0 0x5434 +#define VOL_mmHDMI_ACR_STATUS_1 0x4a35 +#define VOL_mmDIG0_HDMI_ACR_STATUS_1 0x4a35 +#define VOL_mmDIG1_HDMI_ACR_STATUS_1 0x4b35 +#define VOL_mmDIG2_HDMI_ACR_STATUS_1 0x4c35 +#define VOL_mmDIG3_HDMI_ACR_STATUS_1 0x4d35 +#define VOL_mmDIG4_HDMI_ACR_STATUS_1 0x4e35 +#define VOL_mmDIG5_HDMI_ACR_STATUS_1 0x4f35 +#define VOL_mmDIG6_HDMI_ACR_STATUS_1 0x5435 +#define VOL_mmAFMT_AUDIO_INFO0 0x4a36 +#define VOL_mmDIG0_AFMT_AUDIO_INFO0 0x4a36 +#define VOL_mmDIG1_AFMT_AUDIO_INFO0 0x4b36 +#define VOL_mmDIG2_AFMT_AUDIO_INFO0 0x4c36 +#define VOL_mmDIG3_AFMT_AUDIO_INFO0 0x4d36 +#define VOL_mmDIG4_AFMT_AUDIO_INFO0 0x4e36 +#define VOL_mmDIG5_AFMT_AUDIO_INFO0 0x4f36 +#define VOL_mmDIG6_AFMT_AUDIO_INFO0 0x5436 +#define VOL_mmAFMT_AUDIO_INFO1 0x4a37 +#define VOL_mmDIG0_AFMT_AUDIO_INFO1 0x4a37 +#define VOL_mmDIG1_AFMT_AUDIO_INFO1 0x4b37 +#define VOL_mmDIG2_AFMT_AUDIO_INFO1 0x4c37 +#define VOL_mmDIG3_AFMT_AUDIO_INFO1 0x4d37 +#define VOL_mmDIG4_AFMT_AUDIO_INFO1 0x4e37 +#define VOL_mmDIG5_AFMT_AUDIO_INFO1 0x4f37 +#define VOL_mmDIG6_AFMT_AUDIO_INFO1 0x5437 +#define VOL_mmAFMT_60958_0 0x4a38 +#define VOL_mmDIG0_AFMT_60958_0 0x4a38 +#define VOL_mmDIG1_AFMT_60958_0 0x4b38 +#define VOL_mmDIG2_AFMT_60958_0 0x4c38 +#define VOL_mmDIG3_AFMT_60958_0 0x4d38 +#define VOL_mmDIG4_AFMT_60958_0 0x4e38 +#define VOL_mmDIG5_AFMT_60958_0 0x4f38 +#define VOL_mmDIG6_AFMT_60958_0 0x5438 +#define VOL_mmAFMT_60958_1 0x4a39 +#define VOL_mmDIG0_AFMT_60958_1 0x4a39 +#define VOL_mmDIG1_AFMT_60958_1 0x4b39 +#define VOL_mmDIG2_AFMT_60958_1 0x4c39 +#define VOL_mmDIG3_AFMT_60958_1 0x4d39 +#define VOL_mmDIG4_AFMT_60958_1 0x4e39 +#define VOL_mmDIG5_AFMT_60958_1 0x4f39 +#define VOL_mmDIG6_AFMT_60958_1 0x5439 +#define VOL_mmAFMT_AUDIO_CRC_CONTROL 0x4a3a +#define VOL_mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a +#define VOL_mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a +#define VOL_mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a +#define VOL_mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a +#define VOL_mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a +#define VOL_mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a +#define VOL_mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a +#define VOL_mmAFMT_RAMP_CONTROL0 0x4a3b +#define VOL_mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b +#define VOL_mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b +#define VOL_mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b +#define VOL_mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b +#define VOL_mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b +#define VOL_mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b +#define VOL_mmDIG6_AFMT_RAMP_CONTROL0 0x543b +#define VOL_mmAFMT_RAMP_CONTROL1 0x4a3c +#define VOL_mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c +#define VOL_mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c +#define VOL_mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c +#define VOL_mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c +#define VOL_mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c +#define VOL_mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c +#define VOL_mmDIG6_AFMT_RAMP_CONTROL1 0x543c +#define VOL_mmAFMT_RAMP_CONTROL2 0x4a3d +#define VOL_mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d +#define VOL_mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d +#define VOL_mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d +#define VOL_mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d +#define VOL_mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d +#define VOL_mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d +#define VOL_mmDIG6_AFMT_RAMP_CONTROL2 0x543d +#define VOL_mmAFMT_RAMP_CONTROL3 0x4a3e +#define VOL_mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e +#define VOL_mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e +#define VOL_mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e +#define VOL_mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e +#define VOL_mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e +#define VOL_mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e +#define VOL_mmDIG6_AFMT_RAMP_CONTROL3 0x543e +#define VOL_mmAFMT_60958_2 0x4a3f +#define VOL_mmDIG0_AFMT_60958_2 0x4a3f +#define VOL_mmDIG1_AFMT_60958_2 0x4b3f +#define VOL_mmDIG2_AFMT_60958_2 0x4c3f +#define VOL_mmDIG3_AFMT_60958_2 0x4d3f +#define VOL_mmDIG4_AFMT_60958_2 0x4e3f +#define VOL_mmDIG5_AFMT_60958_2 0x4f3f +#define VOL_mmDIG6_AFMT_60958_2 0x543f +#define VOL_mmAFMT_AUDIO_CRC_RESULT 0x4a40 +#define VOL_mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 +#define VOL_mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 +#define VOL_mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 +#define VOL_mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 +#define VOL_mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 +#define VOL_mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 +#define VOL_mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 +#define VOL_mmAFMT_STATUS 0x4a41 +#define VOL_mmDIG0_AFMT_STATUS 0x4a41 +#define VOL_mmDIG1_AFMT_STATUS 0x4b41 +#define VOL_mmDIG2_AFMT_STATUS 0x4c41 +#define VOL_mmDIG3_AFMT_STATUS 0x4d41 +#define VOL_mmDIG4_AFMT_STATUS 0x4e41 +#define VOL_mmDIG5_AFMT_STATUS 0x4f41 +#define VOL_mmDIG6_AFMT_STATUS 0x5441 +#define VOL_mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define VOL_mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define VOL_mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 +#define VOL_mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 +#define VOL_mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 +#define VOL_mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 +#define VOL_mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 +#define VOL_mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 +#define VOL_mmAFMT_VBI_PACKET_CONTROL 0x4a43 +#define VOL_mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 +#define VOL_mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 +#define VOL_mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 +#define VOL_mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 +#define VOL_mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 +#define VOL_mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 +#define VOL_mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 +#define VOL_mmAFMT_INFOFRAME_CONTROL0 0x4a44 +#define VOL_mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 +#define VOL_mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 +#define VOL_mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 +#define VOL_mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 +#define VOL_mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 +#define VOL_mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 +#define VOL_mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 +#define VOL_mmAFMT_AUDIO_SRC_CONTROL 0x4a45 +#define VOL_mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 +#define VOL_mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 +#define VOL_mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 +#define VOL_mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 +#define VOL_mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 +#define VOL_mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 +#define VOL_mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 +#define VOL_mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define VOL_mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define VOL_mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 +#define VOL_mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 +#define VOL_mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 +#define VOL_mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 +#define VOL_mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 +#define VOL_mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 +#define VOL_mmDIG_BE_CNTL 0x4a47 +#define VOL_mmDIG0_DIG_BE_CNTL 0x4a47 +#define VOL_mmDIG1_DIG_BE_CNTL 0x4b47 +#define VOL_mmDIG2_DIG_BE_CNTL 0x4c47 +#define VOL_mmDIG3_DIG_BE_CNTL 0x4d47 +#define VOL_mmDIG4_DIG_BE_CNTL 0x4e47 +#define VOL_mmDIG5_DIG_BE_CNTL 0x4f47 +#define VOL_mmDIG6_DIG_BE_CNTL 0x5447 +#define VOL_mmDIG_BE_EN_CNTL 0x4a48 +#define VOL_mmDIG0_DIG_BE_EN_CNTL 0x4a48 +#define VOL_mmDIG1_DIG_BE_EN_CNTL 0x4b48 +#define VOL_mmDIG2_DIG_BE_EN_CNTL 0x4c48 +#define VOL_mmDIG3_DIG_BE_EN_CNTL 0x4d48 +#define VOL_mmDIG4_DIG_BE_EN_CNTL 0x4e48 +#define VOL_mmDIG5_DIG_BE_EN_CNTL 0x4f48 +#define VOL_mmDIG6_DIG_BE_EN_CNTL 0x5448 +#define VOL_mmTMDS_CNTL 0x4a6b +#define VOL_mmDIG0_TMDS_CNTL 0x4a6b +#define VOL_mmDIG1_TMDS_CNTL 0x4b6b +#define VOL_mmDIG2_TMDS_CNTL 0x4c6b +#define VOL_mmDIG3_TMDS_CNTL 0x4d6b +#define VOL_mmDIG4_TMDS_CNTL 0x4e6b +#define VOL_mmDIG5_TMDS_CNTL 0x4f6b +#define VOL_mmDIG6_TMDS_CNTL 0x546b +#define VOL_mmTMDS_CONTROL_CHAR 0x4a6c +#define VOL_mmDIG0_TMDS_CONTROL_CHAR 0x4a6c +#define VOL_mmDIG1_TMDS_CONTROL_CHAR 0x4b6c +#define VOL_mmDIG2_TMDS_CONTROL_CHAR 0x4c6c +#define VOL_mmDIG3_TMDS_CONTROL_CHAR 0x4d6c +#define VOL_mmDIG4_TMDS_CONTROL_CHAR 0x4e6c +#define VOL_mmDIG5_TMDS_CONTROL_CHAR 0x4f6c +#define VOL_mmDIG6_TMDS_CONTROL_CHAR 0x546c +#define VOL_mmTMDS_CONTROL0_FEEDBACK 0x4a6d +#define VOL_mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d +#define VOL_mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d +#define VOL_mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d +#define VOL_mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d +#define VOL_mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d +#define VOL_mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d +#define VOL_mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d +#define VOL_mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define VOL_mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define VOL_mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e +#define VOL_mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e +#define VOL_mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e +#define VOL_mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e +#define VOL_mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e +#define VOL_mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e +#define VOL_mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define VOL_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define VOL_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f +#define VOL_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f +#define VOL_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f +#define VOL_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f +#define VOL_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f +#define VOL_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f +#define VOL_mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define VOL_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define VOL_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 +#define VOL_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 +#define VOL_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 +#define VOL_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 +#define VOL_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 +#define VOL_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 +#define VOL_mmTMDS_DEBUG 0x4a71 +#define VOL_mmDIG0_TMDS_DEBUG 0x4a71 +#define VOL_mmDIG1_TMDS_DEBUG 0x4b71 +#define VOL_mmDIG2_TMDS_DEBUG 0x4c71 +#define VOL_mmDIG3_TMDS_DEBUG 0x4d71 +#define VOL_mmDIG4_TMDS_DEBUG 0x4e71 +#define VOL_mmDIG5_TMDS_DEBUG 0x4f71 +#define VOL_mmDIG6_TMDS_DEBUG 0x5471 +#define VOL_mmTMDS_CTL_BITS 0x4a72 +#define VOL_mmDIG0_TMDS_CTL_BITS 0x4a72 +#define VOL_mmDIG1_TMDS_CTL_BITS 0x4b72 +#define VOL_mmDIG2_TMDS_CTL_BITS 0x4c72 +#define VOL_mmDIG3_TMDS_CTL_BITS 0x4d72 +#define VOL_mmDIG4_TMDS_CTL_BITS 0x4e72 +#define VOL_mmDIG5_TMDS_CTL_BITS 0x4f72 +#define VOL_mmDIG6_TMDS_CTL_BITS 0x5472 +#define VOL_mmTMDS_DCBALANCER_CONTROL 0x4a73 +#define VOL_mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 +#define VOL_mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 +#define VOL_mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 +#define VOL_mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 +#define VOL_mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 +#define VOL_mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 +#define VOL_mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 +#define VOL_mmTMDS_CTL0_1_GEN_CNTL 0x4a75 +#define VOL_mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 +#define VOL_mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 +#define VOL_mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 +#define VOL_mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 +#define VOL_mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 +#define VOL_mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 +#define VOL_mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 +#define VOL_mmTMDS_CTL2_3_GEN_CNTL 0x4a76 +#define VOL_mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 +#define VOL_mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 +#define VOL_mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 +#define VOL_mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 +#define VOL_mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 +#define VOL_mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 +#define VOL_mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 +#define VOL_ixTMDS_DEBUG1 0x1 +#define VOL_ixTMDS_DEBUG2 0x2 +#define VOL_ixTMDS_DEBUG3 0x3 +#define VOL_ixTMDS_DEBUG7 0x4 +#define VOL_ixTMDS_DEBUG8 0x5 +#define VOL_ixTMDS_DEBUG9 0x6 +#define VOL_ixTMDS_DEBUG10 0x7 +#define VOL_ixTMDS_DEBUG11 0x8 +#define VOL_ixTMDS_DEBUG12 0x9 +#define VOL_ixTMDS_DEBUG13 0xa +#define VOL_mmLVDS_DATA_CNTL 0x4a78 +#define VOL_mmDIG0_LVDS_DATA_CNTL 0x4a78 +#define VOL_mmDIG1_LVDS_DATA_CNTL 0x4b78 +#define VOL_mmDIG2_LVDS_DATA_CNTL 0x4c78 +#define VOL_mmDIG3_LVDS_DATA_CNTL 0x4d78 +#define VOL_mmDIG4_LVDS_DATA_CNTL 0x4e78 +#define VOL_mmDIG5_LVDS_DATA_CNTL 0x4f78 +#define VOL_mmDIG6_LVDS_DATA_CNTL 0x5478 +#define VOL_mmDIG_LANE_ENABLE 0x4a79 +#define VOL_mmDIG0_DIG_LANE_ENABLE 0x4a79 +#define VOL_mmDIG1_DIG_LANE_ENABLE 0x4b79 +#define VOL_mmDIG2_DIG_LANE_ENABLE 0x4c79 +#define VOL_mmDIG3_DIG_LANE_ENABLE 0x4d79 +#define VOL_mmDIG4_DIG_LANE_ENABLE 0x4e79 +#define VOL_mmDIG5_DIG_LANE_ENABLE 0x4f79 +#define VOL_mmDIG6_DIG_LANE_ENABLE 0x5479 +#define VOL_mmDIG_TEST_DEBUG_INDEX 0x4a7a +#define VOL_mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a +#define VOL_mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a +#define VOL_mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a +#define VOL_mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a +#define VOL_mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a +#define VOL_mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a +#define VOL_mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a +#define VOL_mmDIG_TEST_DEBUG_DATA 0x4a7b +#define VOL_mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b +#define VOL_mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b +#define VOL_mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b +#define VOL_mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b +#define VOL_mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b +#define VOL_mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b +#define VOL_mmDIG6_DIG_TEST_DEBUG_DATA 0x547b +#define VOL_mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define VOL_mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define VOL_mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c +#define VOL_mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c +#define VOL_mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c +#define VOL_mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c +#define VOL_mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c +#define VOL_mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c +#define VOL_mmDIG_FE_TEST_DEBUG_DATA 0x4a7d +#define VOL_mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d +#define VOL_mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d +#define VOL_mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d +#define VOL_mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d +#define VOL_mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d +#define VOL_mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d +#define VOL_mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d +#define VOL_mmDMCU_CTRL 0x1600 +#define VOL_mmDMCU_STATUS 0x1601 +#define VOL_mmDMCU_PC_START_ADDR 0x1602 +#define VOL_mmDMCU_FW_START_ADDR 0x1603 +#define VOL_mmDMCU_FW_END_ADDR 0x1604 +#define VOL_mmDMCU_FW_ISR_START_ADDR 0x1605 +#define VOL_mmDMCU_FW_CS_HI 0x1606 +#define VOL_mmDMCU_FW_CS_LO 0x1607 +#define VOL_mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define VOL_mmDMCU_ERAM_WR_CTRL 0x1609 +#define VOL_mmDMCU_ERAM_WR_DATA 0x160a +#define VOL_mmDMCU_ERAM_RD_CTRL 0x160b +#define VOL_mmDMCU_ERAM_RD_DATA 0x160c +#define VOL_mmDMCU_IRAM_WR_CTRL 0x160d +#define VOL_mmDMCU_IRAM_WR_DATA 0x160e +#define VOL_mmDMCU_IRAM_RD_CTRL 0x160f +#define VOL_mmDMCU_IRAM_RD_DATA 0x1610 +#define VOL_mmDMCU_EVENT_TRIGGER 0x1611 +#define VOL_mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define VOL_mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 +#define VOL_mmDMCU_INTERRUPT_STATUS 0x1614 +#define VOL_mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define VOL_mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define VOL_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define VOL_mmDC_DMCU_SCRATCH 0x1618 +#define VOL_mmDMCU_INT_CNT 0x1619 +#define VOL_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a +#define VOL_mmDMCU_UC_CLK_GATING_CNTL 0x161b +#define VOL_mmMASTER_COMM_DATA_REG1 0x161c +#define VOL_mmMASTER_COMM_DATA_REG2 0x161d +#define VOL_mmMASTER_COMM_DATA_REG3 0x161e +#define VOL_mmMASTER_COMM_CMD_REG 0x161f +#define VOL_mmMASTER_COMM_CNTL_REG 0x1620 +#define VOL_mmSLAVE_COMM_DATA_REG1 0x1621 +#define VOL_mmSLAVE_COMM_DATA_REG2 0x1622 +#define VOL_mmSLAVE_COMM_DATA_REG3 0x1623 +#define VOL_mmSLAVE_COMM_CMD_REG 0x1624 +#define VOL_mmSLAVE_COMM_CNTL_REG 0x1625 +#define VOL_mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define VOL_mmDMCU_TEST_DEBUG_DATA 0x1627 +#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 +#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 +#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 +#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 +#define VOL_mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x167c +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x167d +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x167e +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x167f +#define VOL_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5 0x1633 +#define VOL_mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 +#define VOL_mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 +#define VOL_mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 +#define VOL_mmDP_LINK_CNTL 0x4aa0 +#define VOL_mmDP0_DP_LINK_CNTL 0x4aa0 +#define VOL_mmDP1_DP_LINK_CNTL 0x4ba0 +#define VOL_mmDP2_DP_LINK_CNTL 0x4ca0 +#define VOL_mmDP3_DP_LINK_CNTL 0x4da0 +#define VOL_mmDP4_DP_LINK_CNTL 0x4ea0 +#define VOL_mmDP5_DP_LINK_CNTL 0x4fa0 +#define VOL_mmDP6_DP_LINK_CNTL 0x54a0 +#define VOL_mmDP_PIXEL_FORMAT 0x4aa1 +#define VOL_mmDP0_DP_PIXEL_FORMAT 0x4aa1 +#define VOL_mmDP1_DP_PIXEL_FORMAT 0x4ba1 +#define VOL_mmDP2_DP_PIXEL_FORMAT 0x4ca1 +#define VOL_mmDP3_DP_PIXEL_FORMAT 0x4da1 +#define VOL_mmDP4_DP_PIXEL_FORMAT 0x4ea1 +#define VOL_mmDP5_DP_PIXEL_FORMAT 0x4fa1 +#define VOL_mmDP6_DP_PIXEL_FORMAT 0x54a1 +#define VOL_mmDP_MSA_COLORIMETRY 0x4aa2 +#define VOL_mmDP0_DP_MSA_COLORIMETRY 0x4aa2 +#define VOL_mmDP1_DP_MSA_COLORIMETRY 0x4ba2 +#define VOL_mmDP2_DP_MSA_COLORIMETRY 0x4ca2 +#define VOL_mmDP3_DP_MSA_COLORIMETRY 0x4da2 +#define VOL_mmDP4_DP_MSA_COLORIMETRY 0x4ea2 +#define VOL_mmDP5_DP_MSA_COLORIMETRY 0x4fa2 +#define VOL_mmDP6_DP_MSA_COLORIMETRY 0x54a2 +#define VOL_mmDP_CONFIG 0x4aa3 +#define VOL_mmDP0_DP_CONFIG 0x4aa3 +#define VOL_mmDP1_DP_CONFIG 0x4ba3 +#define VOL_mmDP2_DP_CONFIG 0x4ca3 +#define VOL_mmDP3_DP_CONFIG 0x4da3 +#define VOL_mmDP4_DP_CONFIG 0x4ea3 +#define VOL_mmDP5_DP_CONFIG 0x4fa3 +#define VOL_mmDP6_DP_CONFIG 0x54a3 +#define VOL_mmDP_VID_STREAM_CNTL 0x4aa4 +#define VOL_mmDP0_DP_VID_STREAM_CNTL 0x4aa4 +#define VOL_mmDP1_DP_VID_STREAM_CNTL 0x4ba4 +#define VOL_mmDP2_DP_VID_STREAM_CNTL 0x4ca4 +#define VOL_mmDP3_DP_VID_STREAM_CNTL 0x4da4 +#define VOL_mmDP4_DP_VID_STREAM_CNTL 0x4ea4 +#define VOL_mmDP5_DP_VID_STREAM_CNTL 0x4fa4 +#define VOL_mmDP6_DP_VID_STREAM_CNTL 0x54a4 +#define VOL_mmDP_STEER_FIFO 0x4aa5 +#define VOL_mmDP0_DP_STEER_FIFO 0x4aa5 +#define VOL_mmDP1_DP_STEER_FIFO 0x4ba5 +#define VOL_mmDP2_DP_STEER_FIFO 0x4ca5 +#define VOL_mmDP3_DP_STEER_FIFO 0x4da5 +#define VOL_mmDP4_DP_STEER_FIFO 0x4ea5 +#define VOL_mmDP5_DP_STEER_FIFO 0x4fa5 +#define VOL_mmDP6_DP_STEER_FIFO 0x54a5 +#define VOL_mmDP_MSA_MISC 0x4aa6 +#define VOL_mmDP0_DP_MSA_MISC 0x4aa6 +#define VOL_mmDP1_DP_MSA_MISC 0x4ba6 +#define VOL_mmDP2_DP_MSA_MISC 0x4ca6 +#define VOL_mmDP3_DP_MSA_MISC 0x4da6 +#define VOL_mmDP4_DP_MSA_MISC 0x4ea6 +#define VOL_mmDP5_DP_MSA_MISC 0x4fa6 +#define VOL_mmDP6_DP_MSA_MISC 0x54a6 +#define VOL_mmDP_VID_TIMING 0x4aa8 +#define VOL_mmDP0_DP_VID_TIMING 0x4aa8 +#define VOL_mmDP1_DP_VID_TIMING 0x4ba8 +#define VOL_mmDP2_DP_VID_TIMING 0x4ca8 +#define VOL_mmDP3_DP_VID_TIMING 0x4da8 +#define VOL_mmDP4_DP_VID_TIMING 0x4ea8 +#define VOL_mmDP5_DP_VID_TIMING 0x4fa8 +#define VOL_mmDP6_DP_VID_TIMING 0x54a8 +#define VOL_mmDP_VID_N 0x4aa9 +#define VOL_mmDP0_DP_VID_N 0x4aa9 +#define VOL_mmDP1_DP_VID_N 0x4ba9 +#define VOL_mmDP2_DP_VID_N 0x4ca9 +#define VOL_mmDP3_DP_VID_N 0x4da9 +#define VOL_mmDP4_DP_VID_N 0x4ea9 +#define VOL_mmDP5_DP_VID_N 0x4fa9 +#define VOL_mmDP6_DP_VID_N 0x54a9 +#define VOL_mmDP_VID_M 0x4aaa +#define VOL_mmDP0_DP_VID_M 0x4aaa +#define VOL_mmDP1_DP_VID_M 0x4baa +#define VOL_mmDP2_DP_VID_M 0x4caa +#define VOL_mmDP3_DP_VID_M 0x4daa +#define VOL_mmDP4_DP_VID_M 0x4eaa +#define VOL_mmDP5_DP_VID_M 0x4faa +#define VOL_mmDP6_DP_VID_M 0x54aa +#define VOL_mmDP_LINK_FRAMING_CNTL 0x4aab +#define VOL_mmDP0_DP_LINK_FRAMING_CNTL 0x4aab +#define VOL_mmDP1_DP_LINK_FRAMING_CNTL 0x4bab +#define VOL_mmDP2_DP_LINK_FRAMING_CNTL 0x4cab +#define VOL_mmDP3_DP_LINK_FRAMING_CNTL 0x4dab +#define VOL_mmDP4_DP_LINK_FRAMING_CNTL 0x4eab +#define VOL_mmDP5_DP_LINK_FRAMING_CNTL 0x4fab +#define VOL_mmDP6_DP_LINK_FRAMING_CNTL 0x54ab +#define VOL_mmDP_HBR2_EYE_PATTERN 0x4aac +#define VOL_mmDP0_DP_HBR2_EYE_PATTERN 0x4aac +#define VOL_mmDP1_DP_HBR2_EYE_PATTERN 0x4bac +#define VOL_mmDP2_DP_HBR2_EYE_PATTERN 0x4cac +#define VOL_mmDP3_DP_HBR2_EYE_PATTERN 0x4dac +#define VOL_mmDP4_DP_HBR2_EYE_PATTERN 0x4eac +#define VOL_mmDP5_DP_HBR2_EYE_PATTERN 0x4fac +#define VOL_mmDP6_DP_HBR2_EYE_PATTERN 0x54ac +#define VOL_mmDP_VID_MSA_VBID 0x4aad +#define VOL_mmDP0_DP_VID_MSA_VBID 0x4aad +#define VOL_mmDP1_DP_VID_MSA_VBID 0x4bad +#define VOL_mmDP2_DP_VID_MSA_VBID 0x4cad +#define VOL_mmDP3_DP_VID_MSA_VBID 0x4dad +#define VOL_mmDP4_DP_VID_MSA_VBID 0x4ead +#define VOL_mmDP5_DP_VID_MSA_VBID 0x4fad +#define VOL_mmDP6_DP_VID_MSA_VBID 0x54ad +#define VOL_mmDP_VID_INTERRUPT_CNTL 0x4aae +#define VOL_mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae +#define VOL_mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae +#define VOL_mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae +#define VOL_mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae +#define VOL_mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae +#define VOL_mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae +#define VOL_mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae +#define VOL_mmDP_DPHY_CNTL 0x4aaf +#define VOL_mmDP0_DP_DPHY_CNTL 0x4aaf +#define VOL_mmDP1_DP_DPHY_CNTL 0x4baf +#define VOL_mmDP2_DP_DPHY_CNTL 0x4caf +#define VOL_mmDP3_DP_DPHY_CNTL 0x4daf +#define VOL_mmDP4_DP_DPHY_CNTL 0x4eaf +#define VOL_mmDP5_DP_DPHY_CNTL 0x4faf +#define VOL_mmDP6_DP_DPHY_CNTL 0x54af +#define VOL_mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define VOL_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define VOL_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 +#define VOL_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 +#define VOL_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 +#define VOL_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 +#define VOL_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 +#define VOL_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 +#define VOL_mmDP_DPHY_SYM0 0x4ab1 +#define VOL_mmDP0_DP_DPHY_SYM0 0x4ab1 +#define VOL_mmDP1_DP_DPHY_SYM0 0x4bb1 +#define VOL_mmDP2_DP_DPHY_SYM0 0x4cb1 +#define VOL_mmDP3_DP_DPHY_SYM0 0x4db1 +#define VOL_mmDP4_DP_DPHY_SYM0 0x4eb1 +#define VOL_mmDP5_DP_DPHY_SYM0 0x4fb1 +#define VOL_mmDP6_DP_DPHY_SYM0 0x54b1 +#define VOL_mmDP_DPHY_SYM1 0x4ab2 +#define VOL_mmDP0_DP_DPHY_SYM1 0x4ab2 +#define VOL_mmDP1_DP_DPHY_SYM1 0x4bb2 +#define VOL_mmDP2_DP_DPHY_SYM1 0x4cb2 +#define VOL_mmDP3_DP_DPHY_SYM1 0x4db2 +#define VOL_mmDP4_DP_DPHY_SYM1 0x4eb2 +#define VOL_mmDP5_DP_DPHY_SYM1 0x4fb2 +#define VOL_mmDP6_DP_DPHY_SYM1 0x54b2 +#define VOL_mmDP_DPHY_SYM2 0x4ab3 +#define VOL_mmDP0_DP_DPHY_SYM2 0x4ab3 +#define VOL_mmDP1_DP_DPHY_SYM2 0x4bb3 +#define VOL_mmDP2_DP_DPHY_SYM2 0x4cb3 +#define VOL_mmDP3_DP_DPHY_SYM2 0x4db3 +#define VOL_mmDP4_DP_DPHY_SYM2 0x4eb3 +#define VOL_mmDP5_DP_DPHY_SYM2 0x4fb3 +#define VOL_mmDP6_DP_DPHY_SYM2 0x54b3 +#define VOL_mmDP_DPHY_8B10B_CNTL 0x4ab4 +#define VOL_mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 +#define VOL_mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 +#define VOL_mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 +#define VOL_mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 +#define VOL_mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 +#define VOL_mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 +#define VOL_mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 +#define VOL_mmDP_DPHY_PRBS_CNTL 0x4ab5 +#define VOL_mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 +#define VOL_mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 +#define VOL_mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 +#define VOL_mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 +#define VOL_mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 +#define VOL_mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 +#define VOL_mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 +#define VOL_mmDP_DPHY_CRC_EN 0x4ab7 +#define VOL_mmDP0_DP_DPHY_CRC_EN 0x4ab7 +#define VOL_mmDP1_DP_DPHY_CRC_EN 0x4bb7 +#define VOL_mmDP2_DP_DPHY_CRC_EN 0x4cb7 +#define VOL_mmDP3_DP_DPHY_CRC_EN 0x4db7 +#define VOL_mmDP4_DP_DPHY_CRC_EN 0x4eb7 +#define VOL_mmDP5_DP_DPHY_CRC_EN 0x4fb7 +#define VOL_mmDP6_DP_DPHY_CRC_EN 0x54b7 +#define VOL_mmDP_DPHY_CRC_CNTL 0x4ab8 +#define VOL_mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 +#define VOL_mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 +#define VOL_mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 +#define VOL_mmDP3_DP_DPHY_CRC_CNTL 0x4db8 +#define VOL_mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 +#define VOL_mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 +#define VOL_mmDP6_DP_DPHY_CRC_CNTL 0x54b8 +#define VOL_mmDP_DPHY_CRC_RESULT 0x4ab9 +#define VOL_mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 +#define VOL_mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 +#define VOL_mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 +#define VOL_mmDP3_DP_DPHY_CRC_RESULT 0x4db9 +#define VOL_mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 +#define VOL_mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 +#define VOL_mmDP6_DP_DPHY_CRC_RESULT 0x54b9 +#define VOL_mmDP_DPHY_CRC_MST_CNTL 0x4aba +#define VOL_mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba +#define VOL_mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba +#define VOL_mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba +#define VOL_mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba +#define VOL_mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba +#define VOL_mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba +#define VOL_mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba +#define VOL_mmDP_DPHY_CRC_MST_STATUS 0x4abb +#define VOL_mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb +#define VOL_mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb +#define VOL_mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb +#define VOL_mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb +#define VOL_mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb +#define VOL_mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb +#define VOL_mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb +#define VOL_mmDP_DPHY_FAST_TRAINING 0x4abc +#define VOL_mmDP0_DP_DPHY_FAST_TRAINING 0x4abc +#define VOL_mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc +#define VOL_mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc +#define VOL_mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc +#define VOL_mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc +#define VOL_mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc +#define VOL_mmDP6_DP_DPHY_FAST_TRAINING 0x54bc +#define VOL_mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define VOL_mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define VOL_mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd +#define VOL_mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd +#define VOL_mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd +#define VOL_mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd +#define VOL_mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd +#define VOL_mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd +#define VOL_mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define VOL_mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define VOL_mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe +#define VOL_mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe +#define VOL_mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe +#define VOL_mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe +#define VOL_mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe +#define VOL_mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be +#define VOL_mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define VOL_mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define VOL_mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf +#define VOL_mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf +#define VOL_mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf +#define VOL_mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf +#define VOL_mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf +#define VOL_mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf +#define VOL_mmDP_SEC_CNTL 0x4ac3 +#define VOL_mmDP0_DP_SEC_CNTL 0x4ac3 +#define VOL_mmDP1_DP_SEC_CNTL 0x4bc3 +#define VOL_mmDP2_DP_SEC_CNTL 0x4cc3 +#define VOL_mmDP3_DP_SEC_CNTL 0x4dc3 +#define VOL_mmDP4_DP_SEC_CNTL 0x4ec3 +#define VOL_mmDP5_DP_SEC_CNTL 0x4fc3 +#define VOL_mmDP6_DP_SEC_CNTL 0x54c3 +#define VOL_mmDP_SEC_CNTL1 0x4ac4 +#define VOL_mmDP0_DP_SEC_CNTL1 0x4ac4 +#define VOL_mmDP1_DP_SEC_CNTL1 0x4bc4 +#define VOL_mmDP2_DP_SEC_CNTL1 0x4cc4 +#define VOL_mmDP3_DP_SEC_CNTL1 0x4dc4 +#define VOL_mmDP4_DP_SEC_CNTL1 0x4ec4 +#define VOL_mmDP5_DP_SEC_CNTL1 0x4fc4 +#define VOL_mmDP6_DP_SEC_CNTL1 0x54c4 +#define VOL_mmDP_SEC_FRAMING1 0x4ac5 +#define VOL_mmDP0_DP_SEC_FRAMING1 0x4ac5 +#define VOL_mmDP1_DP_SEC_FRAMING1 0x4bc5 +#define VOL_mmDP2_DP_SEC_FRAMING1 0x4cc5 +#define VOL_mmDP3_DP_SEC_FRAMING1 0x4dc5 +#define VOL_mmDP4_DP_SEC_FRAMING1 0x4ec5 +#define VOL_mmDP5_DP_SEC_FRAMING1 0x4fc5 +#define VOL_mmDP6_DP_SEC_FRAMING1 0x54c5 +#define VOL_mmDP_SEC_FRAMING2 0x4ac6 +#define VOL_mmDP0_DP_SEC_FRAMING2 0x4ac6 +#define VOL_mmDP1_DP_SEC_FRAMING2 0x4bc6 +#define VOL_mmDP2_DP_SEC_FRAMING2 0x4cc6 +#define VOL_mmDP3_DP_SEC_FRAMING2 0x4dc6 +#define VOL_mmDP4_DP_SEC_FRAMING2 0x4ec6 +#define VOL_mmDP5_DP_SEC_FRAMING2 0x4fc6 +#define VOL_mmDP6_DP_SEC_FRAMING2 0x54c6 +#define VOL_mmDP_SEC_FRAMING3 0x4ac7 +#define VOL_mmDP0_DP_SEC_FRAMING3 0x4ac7 +#define VOL_mmDP1_DP_SEC_FRAMING3 0x4bc7 +#define VOL_mmDP2_DP_SEC_FRAMING3 0x4cc7 +#define VOL_mmDP3_DP_SEC_FRAMING3 0x4dc7 +#define VOL_mmDP4_DP_SEC_FRAMING3 0x4ec7 +#define VOL_mmDP5_DP_SEC_FRAMING3 0x4fc7 +#define VOL_mmDP6_DP_SEC_FRAMING3 0x54c7 +#define VOL_mmDP_SEC_FRAMING4 0x4ac8 +#define VOL_mmDP0_DP_SEC_FRAMING4 0x4ac8 +#define VOL_mmDP1_DP_SEC_FRAMING4 0x4bc8 +#define VOL_mmDP2_DP_SEC_FRAMING4 0x4cc8 +#define VOL_mmDP3_DP_SEC_FRAMING4 0x4dc8 +#define VOL_mmDP4_DP_SEC_FRAMING4 0x4ec8 +#define VOL_mmDP5_DP_SEC_FRAMING4 0x4fc8 +#define VOL_mmDP6_DP_SEC_FRAMING4 0x54c8 +#define VOL_mmDP_SEC_AUD_N 0x4ac9 +#define VOL_mmDP0_DP_SEC_AUD_N 0x4ac9 +#define VOL_mmDP1_DP_SEC_AUD_N 0x4bc9 +#define VOL_mmDP2_DP_SEC_AUD_N 0x4cc9 +#define VOL_mmDP3_DP_SEC_AUD_N 0x4dc9 +#define VOL_mmDP4_DP_SEC_AUD_N 0x4ec9 +#define VOL_mmDP5_DP_SEC_AUD_N 0x4fc9 +#define VOL_mmDP6_DP_SEC_AUD_N 0x54c9 +#define VOL_mmDP_SEC_AUD_N_READBACK 0x4aca +#define VOL_mmDP0_DP_SEC_AUD_N_READBACK 0x4aca +#define VOL_mmDP1_DP_SEC_AUD_N_READBACK 0x4bca +#define VOL_mmDP2_DP_SEC_AUD_N_READBACK 0x4cca +#define VOL_mmDP3_DP_SEC_AUD_N_READBACK 0x4dca +#define VOL_mmDP4_DP_SEC_AUD_N_READBACK 0x4eca +#define VOL_mmDP5_DP_SEC_AUD_N_READBACK 0x4fca +#define VOL_mmDP6_DP_SEC_AUD_N_READBACK 0x54ca +#define VOL_mmDP_SEC_AUD_M 0x4acb +#define VOL_mmDP0_DP_SEC_AUD_M 0x4acb +#define VOL_mmDP1_DP_SEC_AUD_M 0x4bcb +#define VOL_mmDP2_DP_SEC_AUD_M 0x4ccb +#define VOL_mmDP3_DP_SEC_AUD_M 0x4dcb +#define VOL_mmDP4_DP_SEC_AUD_M 0x4ecb +#define VOL_mmDP5_DP_SEC_AUD_M 0x4fcb +#define VOL_mmDP6_DP_SEC_AUD_M 0x54cb +#define VOL_mmDP_SEC_AUD_M_READBACK 0x4acc +#define VOL_mmDP0_DP_SEC_AUD_M_READBACK 0x4acc +#define VOL_mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc +#define VOL_mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc +#define VOL_mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc +#define VOL_mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc +#define VOL_mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc +#define VOL_mmDP6_DP_SEC_AUD_M_READBACK 0x54cc +#define VOL_mmDP_SEC_TIMESTAMP 0x4acd +#define VOL_mmDP0_DP_SEC_TIMESTAMP 0x4acd +#define VOL_mmDP1_DP_SEC_TIMESTAMP 0x4bcd +#define VOL_mmDP2_DP_SEC_TIMESTAMP 0x4ccd +#define VOL_mmDP3_DP_SEC_TIMESTAMP 0x4dcd +#define VOL_mmDP4_DP_SEC_TIMESTAMP 0x4ecd +#define VOL_mmDP5_DP_SEC_TIMESTAMP 0x4fcd +#define VOL_mmDP6_DP_SEC_TIMESTAMP 0x54cd +#define VOL_mmDP_SEC_PACKET_CNTL 0x4ace +#define VOL_mmDP0_DP_SEC_PACKET_CNTL 0x4ace +#define VOL_mmDP1_DP_SEC_PACKET_CNTL 0x4bce +#define VOL_mmDP2_DP_SEC_PACKET_CNTL 0x4cce +#define VOL_mmDP3_DP_SEC_PACKET_CNTL 0x4dce +#define VOL_mmDP4_DP_SEC_PACKET_CNTL 0x4ece +#define VOL_mmDP5_DP_SEC_PACKET_CNTL 0x4fce +#define VOL_mmDP6_DP_SEC_PACKET_CNTL 0x54ce +#define VOL_mmDP_MSE_RATE_CNTL 0x4acf +#define VOL_mmDP0_DP_MSE_RATE_CNTL 0x4acf +#define VOL_mmDP1_DP_MSE_RATE_CNTL 0x4bcf +#define VOL_mmDP2_DP_MSE_RATE_CNTL 0x4ccf +#define VOL_mmDP3_DP_MSE_RATE_CNTL 0x4dcf +#define VOL_mmDP4_DP_MSE_RATE_CNTL 0x4ecf +#define VOL_mmDP5_DP_MSE_RATE_CNTL 0x4fcf +#define VOL_mmDP6_DP_MSE_RATE_CNTL 0x54cf +#define VOL_mmDP_MSE_RATE_UPDATE 0x4ad1 +#define VOL_mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 +#define VOL_mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 +#define VOL_mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 +#define VOL_mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 +#define VOL_mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 +#define VOL_mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 +#define VOL_mmDP6_DP_MSE_RATE_UPDATE 0x54d1 +#define VOL_mmDP_MSE_SAT0 0x4ad2 +#define VOL_mmDP0_DP_MSE_SAT0 0x4ad2 +#define VOL_mmDP1_DP_MSE_SAT0 0x4bd2 +#define VOL_mmDP2_DP_MSE_SAT0 0x4cd2 +#define VOL_mmDP3_DP_MSE_SAT0 0x4dd2 +#define VOL_mmDP4_DP_MSE_SAT0 0x4ed2 +#define VOL_mmDP5_DP_MSE_SAT0 0x4fd2 +#define VOL_mmDP6_DP_MSE_SAT0 0x54d2 +#define VOL_mmDP_MSE_SAT1 0x4ad3 +#define VOL_mmDP0_DP_MSE_SAT1 0x4ad3 +#define VOL_mmDP1_DP_MSE_SAT1 0x4bd3 +#define VOL_mmDP2_DP_MSE_SAT1 0x4cd3 +#define VOL_mmDP3_DP_MSE_SAT1 0x4dd3 +#define VOL_mmDP4_DP_MSE_SAT1 0x4ed3 +#define VOL_mmDP5_DP_MSE_SAT1 0x4fd3 +#define VOL_mmDP6_DP_MSE_SAT1 0x54d3 +#define VOL_mmDP_MSE_SAT2 0x4ad4 +#define VOL_mmDP0_DP_MSE_SAT2 0x4ad4 +#define VOL_mmDP1_DP_MSE_SAT2 0x4bd4 +#define VOL_mmDP2_DP_MSE_SAT2 0x4cd4 +#define VOL_mmDP3_DP_MSE_SAT2 0x4dd4 +#define VOL_mmDP4_DP_MSE_SAT2 0x4ed4 +#define VOL_mmDP5_DP_MSE_SAT2 0x4fd4 +#define VOL_mmDP6_DP_MSE_SAT2 0x54d4 +#define VOL_mmDP_MSE_SAT_UPDATE 0x4ad5 +#define VOL_mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 +#define VOL_mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 +#define VOL_mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 +#define VOL_mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 +#define VOL_mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 +#define VOL_mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 +#define VOL_mmDP6_DP_MSE_SAT_UPDATE 0x54d5 +#define VOL_mmDP_MSE_LINK_TIMING 0x4ad6 +#define VOL_mmDP0_DP_MSE_LINK_TIMING 0x4ad6 +#define VOL_mmDP1_DP_MSE_LINK_TIMING 0x4bd6 +#define VOL_mmDP2_DP_MSE_LINK_TIMING 0x4cd6 +#define VOL_mmDP3_DP_MSE_LINK_TIMING 0x4dd6 +#define VOL_mmDP4_DP_MSE_LINK_TIMING 0x4ed6 +#define VOL_mmDP5_DP_MSE_LINK_TIMING 0x4fd6 +#define VOL_mmDP6_DP_MSE_LINK_TIMING 0x54d6 +#define VOL_mmDP_MSE_MISC_CNTL 0x4ad7 +#define VOL_mmDP0_DP_MSE_MISC_CNTL 0x4ad7 +#define VOL_mmDP1_DP_MSE_MISC_CNTL 0x4bd7 +#define VOL_mmDP2_DP_MSE_MISC_CNTL 0x4cd7 +#define VOL_mmDP3_DP_MSE_MISC_CNTL 0x4dd7 +#define VOL_mmDP4_DP_MSE_MISC_CNTL 0x4ed7 +#define VOL_mmDP5_DP_MSE_MISC_CNTL 0x4fd7 +#define VOL_mmDP6_DP_MSE_MISC_CNTL 0x54d7 +#define VOL_mmDP_TEST_DEBUG_INDEX 0x4ad8 +#define VOL_mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 +#define VOL_mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 +#define VOL_mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 +#define VOL_mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 +#define VOL_mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 +#define VOL_mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 +#define VOL_mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 +#define VOL_mmDP_TEST_DEBUG_DATA 0x4ad9 +#define VOL_mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 +#define VOL_mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 +#define VOL_mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 +#define VOL_mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 +#define VOL_mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 +#define VOL_mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 +#define VOL_mmDP6_DP_TEST_DEBUG_DATA 0x54d9 +#define VOL_mmDP_FE_TEST_DEBUG_INDEX 0x4ada +#define VOL_mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada +#define VOL_mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda +#define VOL_mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda +#define VOL_mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda +#define VOL_mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda +#define VOL_mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda +#define VOL_mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da +#define VOL_mmDP_FE_TEST_DEBUG_DATA 0x4adb +#define VOL_mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb +#define VOL_mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb +#define VOL_mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb +#define VOL_mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb +#define VOL_mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb +#define VOL_mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb +#define VOL_mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db +#define VOL_mmAUX_CONTROL 0x5c00 +#define VOL_mmDP_AUX0_AUX_CONTROL 0x5c00 +#define VOL_mmDP_AUX1_AUX_CONTROL 0x5c1c +#define VOL_mmDP_AUX2_AUX_CONTROL 0x5c38 +#define VOL_mmDP_AUX3_AUX_CONTROL 0x5c54 +#define VOL_mmDP_AUX4_AUX_CONTROL 0x5c70 +#define VOL_mmDP_AUX5_AUX_CONTROL 0x5c8c +#define VOL_mmAUX_SW_CONTROL 0x5c01 +#define VOL_mmDP_AUX0_AUX_SW_CONTROL 0x5c01 +#define VOL_mmDP_AUX1_AUX_SW_CONTROL 0x5c1d +#define VOL_mmDP_AUX2_AUX_SW_CONTROL 0x5c39 +#define VOL_mmDP_AUX3_AUX_SW_CONTROL 0x5c55 +#define VOL_mmDP_AUX4_AUX_SW_CONTROL 0x5c71 +#define VOL_mmDP_AUX5_AUX_SW_CONTROL 0x5c8d +#define VOL_mmAUX_ARB_CONTROL 0x5c02 +#define VOL_mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 +#define VOL_mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e +#define VOL_mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a +#define VOL_mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 +#define VOL_mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 +#define VOL_mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e +#define VOL_mmAUX_INTERRUPT_CONTROL 0x5c03 +#define VOL_mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 +#define VOL_mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f +#define VOL_mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b +#define VOL_mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 +#define VOL_mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 +#define VOL_mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f +#define VOL_mmAUX_SW_STATUS 0x5c04 +#define VOL_mmDP_AUX0_AUX_SW_STATUS 0x5c04 +#define VOL_mmDP_AUX1_AUX_SW_STATUS 0x5c20 +#define VOL_mmDP_AUX2_AUX_SW_STATUS 0x5c3c +#define VOL_mmDP_AUX3_AUX_SW_STATUS 0x5c58 +#define VOL_mmDP_AUX4_AUX_SW_STATUS 0x5c74 +#define VOL_mmDP_AUX5_AUX_SW_STATUS 0x5c90 +#define VOL_mmAUX_LS_STATUS 0x5c05 +#define VOL_mmDP_AUX0_AUX_LS_STATUS 0x5c05 +#define VOL_mmDP_AUX1_AUX_LS_STATUS 0x5c21 +#define VOL_mmDP_AUX2_AUX_LS_STATUS 0x5c3d +#define VOL_mmDP_AUX3_AUX_LS_STATUS 0x5c59 +#define VOL_mmDP_AUX4_AUX_LS_STATUS 0x5c75 +#define VOL_mmDP_AUX5_AUX_LS_STATUS 0x5c91 +#define VOL_mmAUX_SW_DATA 0x5c06 +#define VOL_mmDP_AUX0_AUX_SW_DATA 0x5c06 +#define VOL_mmDP_AUX1_AUX_SW_DATA 0x5c22 +#define VOL_mmDP_AUX2_AUX_SW_DATA 0x5c3e +#define VOL_mmDP_AUX3_AUX_SW_DATA 0x5c5a +#define VOL_mmDP_AUX4_AUX_SW_DATA 0x5c76 +#define VOL_mmDP_AUX5_AUX_SW_DATA 0x5c92 +#define VOL_mmAUX_LS_DATA 0x5c07 +#define VOL_mmDP_AUX0_AUX_LS_DATA 0x5c07 +#define VOL_mmDP_AUX1_AUX_LS_DATA 0x5c23 +#define VOL_mmDP_AUX2_AUX_LS_DATA 0x5c3f +#define VOL_mmDP_AUX3_AUX_LS_DATA 0x5c5b +#define VOL_mmDP_AUX4_AUX_LS_DATA 0x5c77 +#define VOL_mmDP_AUX5_AUX_LS_DATA 0x5c93 +#define VOL_mmAUX_DPHY_TX_REF_CONTROL 0x5c08 +#define VOL_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 +#define VOL_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 +#define VOL_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 +#define VOL_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c +#define VOL_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 +#define VOL_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 +#define VOL_mmAUX_DPHY_TX_CONTROL 0x5c09 +#define VOL_mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 +#define VOL_mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 +#define VOL_mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 +#define VOL_mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d +#define VOL_mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 +#define VOL_mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 +#define VOL_mmAUX_DPHY_RX_CONTROL0 0x5c0a +#define VOL_mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a +#define VOL_mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 +#define VOL_mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 +#define VOL_mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e +#define VOL_mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a +#define VOL_mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 +#define VOL_mmAUX_DPHY_RX_CONTROL1 0x5c0b +#define VOL_mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b +#define VOL_mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 +#define VOL_mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 +#define VOL_mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f +#define VOL_mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b +#define VOL_mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 +#define VOL_mmAUX_DPHY_TX_STATUS 0x5c0c +#define VOL_mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c +#define VOL_mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 +#define VOL_mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 +#define VOL_mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 +#define VOL_mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c +#define VOL_mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 +#define VOL_mmAUX_DPHY_RX_STATUS 0x5c0d +#define VOL_mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d +#define VOL_mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 +#define VOL_mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 +#define VOL_mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 +#define VOL_mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d +#define VOL_mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 +#define VOL_mmAUX_GTC_SYNC_CONTROL 0x5c0e +#define VOL_mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e +#define VOL_mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a +#define VOL_mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46 +#define VOL_mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62 +#define VOL_mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e +#define VOL_mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a +#define VOL_mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define VOL_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define VOL_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b +#define VOL_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 +#define VOL_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 +#define VOL_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f +#define VOL_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b +#define VOL_mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define VOL_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define VOL_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c +#define VOL_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 +#define VOL_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 +#define VOL_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 +#define VOL_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c +#define VOL_mmAUX_GTC_SYNC_STATUS 0x5c11 +#define VOL_mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 +#define VOL_mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d +#define VOL_mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 +#define VOL_mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 +#define VOL_mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 +#define VOL_mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d +#define VOL_mmAUX_GTC_SYNC_DATA 0x5c12 +#define VOL_mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12 +#define VOL_mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e +#define VOL_mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a +#define VOL_mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66 +#define VOL_mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82 +#define VOL_mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e +#define VOL_mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 +#define VOL_mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 +#define VOL_mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f +#define VOL_mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b +#define VOL_mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67 +#define VOL_mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83 +#define VOL_mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f +#define VOL_mmAUX_TEST_DEBUG_INDEX 0x5c14 +#define VOL_mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 +#define VOL_mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 +#define VOL_mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c +#define VOL_mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 +#define VOL_mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 +#define VOL_mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 +#define VOL_mmAUX_TEST_DEBUG_DATA 0x5c15 +#define VOL_mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 +#define VOL_mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 +#define VOL_mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d +#define VOL_mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 +#define VOL_mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 +#define VOL_mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 +#define VOL_ixDP_AUX_DEBUG_A 0x10 +#define VOL_ixDP_AUX_DEBUG_B 0x11 +#define VOL_ixDP_AUX_DEBUG_C 0x12 +#define VOL_ixDP_AUX_DEBUG_D 0x13 +#define VOL_ixDP_AUX_DEBUG_E 0x14 +#define VOL_ixDP_AUX_DEBUG_F 0x15 +#define VOL_ixDP_AUX_DEBUG_G 0x16 +#define VOL_ixDP_AUX_DEBUG_H 0x17 +#define VOL_ixDP_AUX_DEBUG_I 0x18 +#define VOL_ixDP_AUX_DEBUG_J 0x19 +#define VOL_ixDP_AUX_DEBUG_K 0x1a +#define VOL_ixDP_AUX_DEBUG_L 0x1b +#define VOL_ixDP_AUX_DEBUG_M 0x1c +#define VOL_ixDP_AUX_DEBUG_N 0x1d +#define VOL_ixDP_AUX_DEBUG_O 0x1e +#define VOL_ixDP_AUX_DEBUG_P 0x1f +#define VOL_ixDP_AUX_DEBUG_Q 0x20 +#define VOL_mmDVO_ENABLE 0x16a0 +#define VOL_mmDVO_SOURCE_SELECT 0x16a1 +#define VOL_mmDVO_OUTPUT 0x16a2 +#define VOL_mmDVO_CONTROL 0x16a3 +#define VOL_mmDVO_CRC_EN 0x16a4 +#define VOL_mmDVO_CRC2_SIG_MASK 0x16a5 +#define VOL_mmDVO_CRC2_SIG_RESULT 0x16a6 +#define VOL_mmDVO_FIFO_ERROR_STATUS 0x16a7 +#define VOL_mmDVO_TEST_DEBUG_INDEX 0x16a8 +#define VOL_mmDVO_TEST_DEBUG_DATA 0x16a9 +#define VOL_mmFBC_CNTL 0x280 +#define VOL_mmFBC_IDLE_MASK 0x281 +#define VOL_mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 +#define VOL_mmFBC_START_STOP_DELAY 0x283 +#define VOL_mmFBC_COMP_CNTL 0x284 +#define VOL_mmFBC_COMP_MODE 0x285 +#define VOL_mmFBC_DEBUG0 0x286 +#define VOL_mmFBC_DEBUG1 0x287 +#define VOL_mmFBC_DEBUG2 0x288 +#define VOL_mmFBC_IND_LUT0 0x289 +#define VOL_mmFBC_IND_LUT1 0x28a +#define VOL_mmFBC_IND_LUT2 0x28b +#define VOL_mmFBC_IND_LUT3 0x28c +#define VOL_mmFBC_IND_LUT4 0x28d +#define VOL_mmFBC_IND_LUT5 0x28e +#define VOL_mmFBC_IND_LUT6 0x28f +#define VOL_mmFBC_IND_LUT7 0x290 +#define VOL_mmFBC_IND_LUT8 0x291 +#define VOL_mmFBC_IND_LUT9 0x292 +#define VOL_mmFBC_IND_LUT10 0x293 +#define VOL_mmFBC_IND_LUT11 0x294 +#define VOL_mmFBC_IND_LUT12 0x295 +#define VOL_mmFBC_IND_LUT13 0x296 +#define VOL_mmFBC_IND_LUT14 0x297 +#define VOL_mmFBC_IND_LUT15 0x298 +#define VOL_mmFBC_CSM_REGION_OFFSET_01 0x299 +#define VOL_mmFBC_CSM_REGION_OFFSET_23 0x29a +#define VOL_mmFBC_CLIENT_REGION_MASK 0x29b +#define VOL_mmFBC_DEBUG_COMP 0x29c +#define VOL_mmFBC_DEBUG_CSR 0x29d +#define VOL_mmFBC_DEBUG_CSR_RDATA 0x29e +#define VOL_mmFBC_DEBUG_CSR_WDATA 0x29f +#define VOL_mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 +#define VOL_mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 +#define VOL_mmFBC_MISC 0x2a2 +#define VOL_mmFBC_STATUS 0x2a3 +#define VOL_mmFBC_TEST_DEBUG_INDEX 0x2a4 +#define VOL_mmFBC_TEST_DEBUG_DATA 0x2a5 +#define VOL_mmFMT_CLAMP_COMPONENT_R 0x1be8 +#define VOL_mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 +#define VOL_mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 +#define VOL_mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 +#define VOL_mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 +#define VOL_mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 +#define VOL_mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 +#define VOL_mmFMT_CLAMP_COMPONENT_G 0x1be9 +#define VOL_mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 +#define VOL_mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 +#define VOL_mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 +#define VOL_mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 +#define VOL_mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 +#define VOL_mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 +#define VOL_mmFMT_CLAMP_COMPONENT_B 0x1bea +#define VOL_mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea +#define VOL_mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea +#define VOL_mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea +#define VOL_mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea +#define VOL_mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea +#define VOL_mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea +#define VOL_mmFMT_DYNAMIC_EXP_CNTL 0x1bed +#define VOL_mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed +#define VOL_mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded +#define VOL_mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed +#define VOL_mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed +#define VOL_mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed +#define VOL_mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed +#define VOL_mmFMT_CONTROL 0x1bee +#define VOL_mmFMT0_FMT_CONTROL 0x1bee +#define VOL_mmFMT1_FMT_CONTROL 0x1dee +#define VOL_mmFMT2_FMT_CONTROL 0x1fee +#define VOL_mmFMT3_FMT_CONTROL 0x41ee +#define VOL_mmFMT4_FMT_CONTROL 0x43ee +#define VOL_mmFMT5_FMT_CONTROL 0x45ee +#define VOL_mmFMT_FORCE_OUTPUT_CNTL 0x1bef +#define VOL_mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef +#define VOL_mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1def +#define VOL_mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x1fef +#define VOL_mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x41ef +#define VOL_mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x43ef +#define VOL_mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x45ef +#define VOL_mmFMT_FORCE_DATA_0_1 0x1bf0 +#define VOL_mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0 +#define VOL_mmFMT1_FMT_FORCE_DATA_0_1 0x1df0 +#define VOL_mmFMT2_FMT_FORCE_DATA_0_1 0x1ff0 +#define VOL_mmFMT3_FMT_FORCE_DATA_0_1 0x41f0 +#define VOL_mmFMT4_FMT_FORCE_DATA_0_1 0x43f0 +#define VOL_mmFMT5_FMT_FORCE_DATA_0_1 0x45f0 +#define VOL_mmFMT_FORCE_DATA_2_3 0x1bf1 +#define VOL_mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1 +#define VOL_mmFMT1_FMT_FORCE_DATA_2_3 0x1df1 +#define VOL_mmFMT2_FMT_FORCE_DATA_2_3 0x1ff1 +#define VOL_mmFMT3_FMT_FORCE_DATA_2_3 0x41f1 +#define VOL_mmFMT4_FMT_FORCE_DATA_2_3 0x43f1 +#define VOL_mmFMT5_FMT_FORCE_DATA_2_3 0x45f1 +#define VOL_mmFMT_BIT_DEPTH_CONTROL 0x1bf2 +#define VOL_mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 +#define VOL_mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 +#define VOL_mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 +#define VOL_mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 +#define VOL_mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 +#define VOL_mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 +#define VOL_mmFMT_DITHER_RAND_R_SEED 0x1bf3 +#define VOL_mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 +#define VOL_mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 +#define VOL_mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 +#define VOL_mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 +#define VOL_mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 +#define VOL_mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 +#define VOL_mmFMT_DITHER_RAND_G_SEED 0x1bf4 +#define VOL_mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 +#define VOL_mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 +#define VOL_mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 +#define VOL_mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 +#define VOL_mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 +#define VOL_mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 +#define VOL_mmFMT_DITHER_RAND_B_SEED 0x1bf5 +#define VOL_mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 +#define VOL_mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 +#define VOL_mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 +#define VOL_mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 +#define VOL_mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 +#define VOL_mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 +#define VOL_mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define VOL_mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define VOL_mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 +#define VOL_mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 +#define VOL_mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 +#define VOL_mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 +#define VOL_mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 +#define VOL_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define VOL_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define VOL_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 +#define VOL_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 +#define VOL_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 +#define VOL_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 +#define VOL_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 +#define VOL_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define VOL_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define VOL_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 +#define VOL_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 +#define VOL_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 +#define VOL_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 +#define VOL_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 +#define VOL_mmFMT_CLAMP_CNTL 0x1bf9 +#define VOL_mmFMT0_FMT_CLAMP_CNTL 0x1bf9 +#define VOL_mmFMT1_FMT_CLAMP_CNTL 0x1df9 +#define VOL_mmFMT2_FMT_CLAMP_CNTL 0x1ff9 +#define VOL_mmFMT3_FMT_CLAMP_CNTL 0x41f9 +#define VOL_mmFMT4_FMT_CLAMP_CNTL 0x43f9 +#define VOL_mmFMT5_FMT_CLAMP_CNTL 0x45f9 +#define VOL_mmFMT_CRC_CNTL 0x1bfa +#define VOL_mmFMT0_FMT_CRC_CNTL 0x1bfa +#define VOL_mmFMT1_FMT_CRC_CNTL 0x1dfa +#define VOL_mmFMT2_FMT_CRC_CNTL 0x1ffa +#define VOL_mmFMT3_FMT_CRC_CNTL 0x41fa +#define VOL_mmFMT4_FMT_CRC_CNTL 0x43fa +#define VOL_mmFMT5_FMT_CRC_CNTL 0x45fa +#define VOL_mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define VOL_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define VOL_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb +#define VOL_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb +#define VOL_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb +#define VOL_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb +#define VOL_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb +#define VOL_mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define VOL_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define VOL_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc +#define VOL_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc +#define VOL_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc +#define VOL_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc +#define VOL_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc +#define VOL_mmFMT_CRC_SIG_RED_GREEN 0x1bfd +#define VOL_mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd +#define VOL_mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd +#define VOL_mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd +#define VOL_mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd +#define VOL_mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd +#define VOL_mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd +#define VOL_mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define VOL_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define VOL_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe +#define VOL_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe +#define VOL_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe +#define VOL_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe +#define VOL_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe +#define VOL_mmFMT_DEBUG_CNTL 0x1bff +#define VOL_mmFMT0_FMT_DEBUG_CNTL 0x1bff +#define VOL_mmFMT1_FMT_DEBUG_CNTL 0x1dff +#define VOL_mmFMT2_FMT_DEBUG_CNTL 0x1fff +#define VOL_mmFMT3_FMT_DEBUG_CNTL 0x41ff +#define VOL_mmFMT4_FMT_DEBUG_CNTL 0x43ff +#define VOL_mmFMT5_FMT_DEBUG_CNTL 0x45ff +#define VOL_mmFMT_TEST_DEBUG_INDEX 0x1beb +#define VOL_mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb +#define VOL_mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb +#define VOL_mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb +#define VOL_mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb +#define VOL_mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb +#define VOL_mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb +#define VOL_mmFMT_TEST_DEBUG_DATA 0x1bec +#define VOL_mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec +#define VOL_mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec +#define VOL_mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec +#define VOL_mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec +#define VOL_mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec +#define VOL_mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec +#define VOL_ixFMT_DEBUG0 0x1 +#define VOL_ixFMT_DEBUG1 0x2 +#define VOL_ixFMT_DEBUG2 0x3 +#define VOL_ixFMT_DEBUG_ID 0x0 +#define VOL_mmLB_DATA_FORMAT 0x1ac0 +#define VOL_mmLB0_LB_DATA_FORMAT 0x1ac0 +#define VOL_mmLB1_LB_DATA_FORMAT 0x1cc0 +#define VOL_mmLB2_LB_DATA_FORMAT 0x1ec0 +#define VOL_mmLB3_LB_DATA_FORMAT 0x40c0 +#define VOL_mmLB4_LB_DATA_FORMAT 0x42c0 +#define VOL_mmLB5_LB_DATA_FORMAT 0x44c0 +#define VOL_mmLB_MEMORY_CTRL 0x1ac1 +#define VOL_mmLB0_LB_MEMORY_CTRL 0x1ac1 +#define VOL_mmLB1_LB_MEMORY_CTRL 0x1cc1 +#define VOL_mmLB2_LB_MEMORY_CTRL 0x1ec1 +#define VOL_mmLB3_LB_MEMORY_CTRL 0x40c1 +#define VOL_mmLB4_LB_MEMORY_CTRL 0x42c1 +#define VOL_mmLB5_LB_MEMORY_CTRL 0x44c1 +#define VOL_mmLB_MEMORY_SIZE_STATUS 0x1ac2 +#define VOL_mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 +#define VOL_mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 +#define VOL_mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 +#define VOL_mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 +#define VOL_mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 +#define VOL_mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 +#define VOL_mmLB_DESKTOP_HEIGHT 0x1ac3 +#define VOL_mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 +#define VOL_mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 +#define VOL_mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 +#define VOL_mmLB3_LB_DESKTOP_HEIGHT 0x40c3 +#define VOL_mmLB4_LB_DESKTOP_HEIGHT 0x42c3 +#define VOL_mmLB5_LB_DESKTOP_HEIGHT 0x44c3 +#define VOL_mmLB_VLINE_START_END 0x1ac4 +#define VOL_mmLB0_LB_VLINE_START_END 0x1ac4 +#define VOL_mmLB1_LB_VLINE_START_END 0x1cc4 +#define VOL_mmLB2_LB_VLINE_START_END 0x1ec4 +#define VOL_mmLB3_LB_VLINE_START_END 0x40c4 +#define VOL_mmLB4_LB_VLINE_START_END 0x42c4 +#define VOL_mmLB5_LB_VLINE_START_END 0x44c4 +#define VOL_mmLB_VLINE2_START_END 0x1ac5 +#define VOL_mmLB0_LB_VLINE2_START_END 0x1ac5 +#define VOL_mmLB1_LB_VLINE2_START_END 0x1cc5 +#define VOL_mmLB2_LB_VLINE2_START_END 0x1ec5 +#define VOL_mmLB3_LB_VLINE2_START_END 0x40c5 +#define VOL_mmLB4_LB_VLINE2_START_END 0x42c5 +#define VOL_mmLB5_LB_VLINE2_START_END 0x44c5 +#define VOL_mmLB_V_COUNTER 0x1ac6 +#define VOL_mmLB0_LB_V_COUNTER 0x1ac6 +#define VOL_mmLB1_LB_V_COUNTER 0x1cc6 +#define VOL_mmLB2_LB_V_COUNTER 0x1ec6 +#define VOL_mmLB3_LB_V_COUNTER 0x40c6 +#define VOL_mmLB4_LB_V_COUNTER 0x42c6 +#define VOL_mmLB5_LB_V_COUNTER 0x44c6 +#define VOL_mmLB_SNAPSHOT_V_COUNTER 0x1ac7 +#define VOL_mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 +#define VOL_mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 +#define VOL_mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 +#define VOL_mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 +#define VOL_mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 +#define VOL_mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 +#define VOL_mmLB_INTERRUPT_MASK 0x1ac8 +#define VOL_mmLB0_LB_INTERRUPT_MASK 0x1ac8 +#define VOL_mmLB1_LB_INTERRUPT_MASK 0x1cc8 +#define VOL_mmLB2_LB_INTERRUPT_MASK 0x1ec8 +#define VOL_mmLB3_LB_INTERRUPT_MASK 0x40c8 +#define VOL_mmLB4_LB_INTERRUPT_MASK 0x42c8 +#define VOL_mmLB5_LB_INTERRUPT_MASK 0x44c8 +#define VOL_mmLB_VLINE_STATUS 0x1ac9 +#define VOL_mmLB0_LB_VLINE_STATUS 0x1ac9 +#define VOL_mmLB1_LB_VLINE_STATUS 0x1cc9 +#define VOL_mmLB2_LB_VLINE_STATUS 0x1ec9 +#define VOL_mmLB3_LB_VLINE_STATUS 0x40c9 +#define VOL_mmLB4_LB_VLINE_STATUS 0x42c9 +#define VOL_mmLB5_LB_VLINE_STATUS 0x44c9 +#define VOL_mmLB_VLINE2_STATUS 0x1aca +#define VOL_mmLB0_LB_VLINE2_STATUS 0x1aca +#define VOL_mmLB1_LB_VLINE2_STATUS 0x1cca +#define VOL_mmLB2_LB_VLINE2_STATUS 0x1eca +#define VOL_mmLB3_LB_VLINE2_STATUS 0x40ca +#define VOL_mmLB4_LB_VLINE2_STATUS 0x42ca +#define VOL_mmLB5_LB_VLINE2_STATUS 0x44ca +#define VOL_mmLB_VBLANK_STATUS 0x1acb +#define VOL_mmLB0_LB_VBLANK_STATUS 0x1acb +#define VOL_mmLB1_LB_VBLANK_STATUS 0x1ccb +#define VOL_mmLB2_LB_VBLANK_STATUS 0x1ecb +#define VOL_mmLB3_LB_VBLANK_STATUS 0x40cb +#define VOL_mmLB4_LB_VBLANK_STATUS 0x42cb +#define VOL_mmLB5_LB_VBLANK_STATUS 0x44cb +#define VOL_mmLB_SYNC_RESET_SEL 0x1acc +#define VOL_mmLB0_LB_SYNC_RESET_SEL 0x1acc +#define VOL_mmLB1_LB_SYNC_RESET_SEL 0x1ccc +#define VOL_mmLB2_LB_SYNC_RESET_SEL 0x1ecc +#define VOL_mmLB3_LB_SYNC_RESET_SEL 0x40cc +#define VOL_mmLB4_LB_SYNC_RESET_SEL 0x42cc +#define VOL_mmLB5_LB_SYNC_RESET_SEL 0x44cc +#define VOL_mmLB_BLACK_KEYER_R_CR 0x1acd +#define VOL_mmLB0_LB_BLACK_KEYER_R_CR 0x1acd +#define VOL_mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd +#define VOL_mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd +#define VOL_mmLB3_LB_BLACK_KEYER_R_CR 0x40cd +#define VOL_mmLB4_LB_BLACK_KEYER_R_CR 0x42cd +#define VOL_mmLB5_LB_BLACK_KEYER_R_CR 0x44cd +#define VOL_mmLB_BLACK_KEYER_G_Y 0x1ace +#define VOL_mmLB0_LB_BLACK_KEYER_G_Y 0x1ace +#define VOL_mmLB1_LB_BLACK_KEYER_G_Y 0x1cce +#define VOL_mmLB2_LB_BLACK_KEYER_G_Y 0x1ece +#define VOL_mmLB3_LB_BLACK_KEYER_G_Y 0x40ce +#define VOL_mmLB4_LB_BLACK_KEYER_G_Y 0x42ce +#define VOL_mmLB5_LB_BLACK_KEYER_G_Y 0x44ce +#define VOL_mmLB_BLACK_KEYER_B_CB 0x1acf +#define VOL_mmLB0_LB_BLACK_KEYER_B_CB 0x1acf +#define VOL_mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf +#define VOL_mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf +#define VOL_mmLB3_LB_BLACK_KEYER_B_CB 0x40cf +#define VOL_mmLB4_LB_BLACK_KEYER_B_CB 0x42cf +#define VOL_mmLB5_LB_BLACK_KEYER_B_CB 0x44cf +#define VOL_mmLB_KEYER_COLOR_CTRL 0x1ad0 +#define VOL_mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 +#define VOL_mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 +#define VOL_mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 +#define VOL_mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 +#define VOL_mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 +#define VOL_mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 +#define VOL_mmLB_KEYER_COLOR_R_CR 0x1ad1 +#define VOL_mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 +#define VOL_mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 +#define VOL_mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 +#define VOL_mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 +#define VOL_mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 +#define VOL_mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 +#define VOL_mmLB_KEYER_COLOR_G_Y 0x1ad2 +#define VOL_mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 +#define VOL_mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 +#define VOL_mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 +#define VOL_mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 +#define VOL_mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 +#define VOL_mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 +#define VOL_mmLB_KEYER_COLOR_B_CB 0x1ad3 +#define VOL_mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 +#define VOL_mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 +#define VOL_mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 +#define VOL_mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 +#define VOL_mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 +#define VOL_mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 +#define VOL_mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define VOL_mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define VOL_mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 +#define VOL_mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 +#define VOL_mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 +#define VOL_mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 +#define VOL_mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 +#define VOL_mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define VOL_mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define VOL_mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 +#define VOL_mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 +#define VOL_mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 +#define VOL_mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 +#define VOL_mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 +#define VOL_mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define VOL_mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define VOL_mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 +#define VOL_mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 +#define VOL_mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 +#define VOL_mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 +#define VOL_mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 +#define VOL_mmLB_BUFFER_LEVEL_STATUS 0x1ad7 +#define VOL_mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 +#define VOL_mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 +#define VOL_mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 +#define VOL_mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 +#define VOL_mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 +#define VOL_mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 +#define VOL_mmLB_BUFFER_URGENCY_CTRL 0x1ad8 +#define VOL_mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 +#define VOL_mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 +#define VOL_mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 +#define VOL_mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 +#define VOL_mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 +#define VOL_mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 +#define VOL_mmLB_BUFFER_URGENCY_STATUS 0x1ad9 +#define VOL_mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 +#define VOL_mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 +#define VOL_mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 +#define VOL_mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 +#define VOL_mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 +#define VOL_mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 +#define VOL_mmLB_BUFFER_STATUS 0x1ada +#define VOL_mmLB0_LB_BUFFER_STATUS 0x1ada +#define VOL_mmLB1_LB_BUFFER_STATUS 0x1cda +#define VOL_mmLB2_LB_BUFFER_STATUS 0x1eda +#define VOL_mmLB3_LB_BUFFER_STATUS 0x40da +#define VOL_mmLB4_LB_BUFFER_STATUS 0x42da +#define VOL_mmLB5_LB_BUFFER_STATUS 0x44da +#define VOL_mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define VOL_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define VOL_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc +#define VOL_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc +#define VOL_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc +#define VOL_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc +#define VOL_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc +#define VOL_mmMVP_AFR_FLIP_MODE 0x1ae0 +#define VOL_mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 +#define VOL_mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 +#define VOL_mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 +#define VOL_mmLB3_MVP_AFR_FLIP_MODE 0x40e0 +#define VOL_mmLB4_MVP_AFR_FLIP_MODE 0x42e0 +#define VOL_mmLB5_MVP_AFR_FLIP_MODE 0x44e0 +#define VOL_mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define VOL_mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define VOL_mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 +#define VOL_mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 +#define VOL_mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 +#define VOL_mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 +#define VOL_mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 +#define VOL_mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define VOL_mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define VOL_mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 +#define VOL_mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 +#define VOL_mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 +#define VOL_mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 +#define VOL_mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 +#define VOL_mmDC_MVP_LB_CONTROL 0x1ae3 +#define VOL_mmLB0_DC_MVP_LB_CONTROL 0x1ae3 +#define VOL_mmLB1_DC_MVP_LB_CONTROL 0x1ce3 +#define VOL_mmLB2_DC_MVP_LB_CONTROL 0x1ee3 +#define VOL_mmLB3_DC_MVP_LB_CONTROL 0x40e3 +#define VOL_mmLB4_DC_MVP_LB_CONTROL 0x42e3 +#define VOL_mmLB5_DC_MVP_LB_CONTROL 0x44e3 +#define VOL_mmLB_DEBUG 0x1ae4 +#define VOL_mmLB0_LB_DEBUG 0x1ae4 +#define VOL_mmLB1_LB_DEBUG 0x1ce4 +#define VOL_mmLB2_LB_DEBUG 0x1ee4 +#define VOL_mmLB3_LB_DEBUG 0x40e4 +#define VOL_mmLB4_LB_DEBUG 0x42e4 +#define VOL_mmLB5_LB_DEBUG 0x44e4 +#define VOL_mmLB_DEBUG2 0x1ae5 +#define VOL_mmLB0_LB_DEBUG2 0x1ae5 +#define VOL_mmLB1_LB_DEBUG2 0x1ce5 +#define VOL_mmLB2_LB_DEBUG2 0x1ee5 +#define VOL_mmLB3_LB_DEBUG2 0x40e5 +#define VOL_mmLB4_LB_DEBUG2 0x42e5 +#define VOL_mmLB5_LB_DEBUG2 0x44e5 +#define VOL_mmLB_DEBUG3 0x1ae6 +#define VOL_mmLB0_LB_DEBUG3 0x1ae6 +#define VOL_mmLB1_LB_DEBUG3 0x1ce6 +#define VOL_mmLB2_LB_DEBUG3 0x1ee6 +#define VOL_mmLB3_LB_DEBUG3 0x40e6 +#define VOL_mmLB4_LB_DEBUG3 0x42e6 +#define VOL_mmLB5_LB_DEBUG3 0x44e6 +#define VOL_mmLB_TEST_DEBUG_INDEX 0x1afe +#define VOL_mmLB0_LB_TEST_DEBUG_INDEX 0x1afe +#define VOL_mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe +#define VOL_mmLB2_LB_TEST_DEBUG_INDEX 0x1efe +#define VOL_mmLB3_LB_TEST_DEBUG_INDEX 0x40fe +#define VOL_mmLB4_LB_TEST_DEBUG_INDEX 0x42fe +#define VOL_mmLB5_LB_TEST_DEBUG_INDEX 0x44fe +#define VOL_mmLB_TEST_DEBUG_DATA 0x1aff +#define VOL_mmLB0_LB_TEST_DEBUG_DATA 0x1aff +#define VOL_mmLB1_LB_TEST_DEBUG_DATA 0x1cff +#define VOL_mmLB2_LB_TEST_DEBUG_DATA 0x1eff +#define VOL_mmLB3_LB_TEST_DEBUG_DATA 0x40ff +#define VOL_mmLB4_LB_TEST_DEBUG_DATA 0x42ff +#define VOL_mmLB5_LB_TEST_DEBUG_DATA 0x44ff +#define VOL_mmLBV_DATA_FORMAT 0x463c +#define VOL_mmLBV_MEMORY_CTRL 0x463d +#define VOL_mmLBV_MEMORY_SIZE_STATUS 0x463e +#define VOL_mmLBV_DESKTOP_HEIGHT 0x463f +#define VOL_mmLBV_VLINE_START_END 0x4640 +#define VOL_mmLBV_VLINE2_START_END 0x4641 +#define VOL_mmLBV_V_COUNTER 0x4642 +#define VOL_mmLBV_SNAPSHOT_V_COUNTER 0x4643 +#define VOL_mmLBV_V_COUNTER_CHROMA 0x4644 +#define VOL_mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 +#define VOL_mmLBV_INTERRUPT_MASK 0x4646 +#define VOL_mmLBV_VLINE_STATUS 0x4647 +#define VOL_mmLBV_VLINE2_STATUS 0x4648 +#define VOL_mmLBV_VBLANK_STATUS 0x4649 +#define VOL_mmLBV_SYNC_RESET_SEL 0x464a +#define VOL_mmLBV_BLACK_KEYER_R_CR 0x464b +#define VOL_mmLBV_BLACK_KEYER_G_Y 0x464c +#define VOL_mmLBV_BLACK_KEYER_B_CB 0x464d +#define VOL_mmLBV_KEYER_COLOR_CTRL 0x464e +#define VOL_mmLBV_KEYER_COLOR_R_CR 0x464f +#define VOL_mmLBV_KEYER_COLOR_G_Y 0x4650 +#define VOL_mmLBV_KEYER_COLOR_B_CB 0x4651 +#define VOL_mmLBV_KEYER_COLOR_REP_R_CR 0x4652 +#define VOL_mmLBV_KEYER_COLOR_REP_G_Y 0x4653 +#define VOL_mmLBV_KEYER_COLOR_REP_B_CB 0x4654 +#define VOL_mmLBV_BUFFER_LEVEL_STATUS 0x4655 +#define VOL_mmLBV_BUFFER_URGENCY_CTRL 0x4656 +#define VOL_mmLBV_BUFFER_URGENCY_STATUS 0x4657 +#define VOL_mmLBV_BUFFER_STATUS 0x4658 +#define VOL_mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 +#define VOL_mmLBV_DEBUG 0x465a +#define VOL_mmLBV_DEBUG2 0x465b +#define VOL_mmLBV_DEBUG3 0x465c +#define VOL_mmLBV_TEST_DEBUG_INDEX 0x4666 +#define VOL_mmLBV_TEST_DEBUG_DATA 0x4667 +#define VOL_mmMVP_CONTROL1 0x2ac +#define VOL_mmMVP_CONTROL2 0x2ad +#define VOL_mmMVP_FIFO_CONTROL 0x2ae +#define VOL_mmMVP_FIFO_STATUS 0x2af +#define VOL_mmMVP_SLAVE_STATUS 0x2b0 +#define VOL_mmMVP_INBAND_CNTL_CAP 0x2b1 +#define VOL_mmMVP_BLACK_KEYER 0x2b2 +#define VOL_mmMVP_CRC_CNTL 0x2b3 +#define VOL_mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 +#define VOL_mmMVP_CRC_RESULT_RED 0x2b5 +#define VOL_mmMVP_CONTROL3 0x2b6 +#define VOL_mmMVP_RECEIVE_CNT_CNTL1 0x2b7 +#define VOL_mmMVP_RECEIVE_CNT_CNTL2 0x2b8 +#define VOL_mmMVP_DEBUG 0x2bb +#define VOL_mmMVP_TEST_DEBUG_INDEX 0x2b9 +#define VOL_mmMVP_TEST_DEBUG_DATA 0x2ba +#define VOL_ixMVP_DEBUG_12 0xc +#define VOL_ixMVP_DEBUG_13 0xd +#define VOL_ixMVP_DEBUG_14 0xe +#define VOL_ixMVP_DEBUG_15 0xf +#define VOL_ixMVP_DEBUG_16 0x10 +#define VOL_ixMVP_DEBUG_17 0x11 +#define VOL_mmSCL_COEF_RAM_SELECT 0x1b40 +#define VOL_mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 +#define VOL_mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 +#define VOL_mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 +#define VOL_mmSCL3_SCL_COEF_RAM_SELECT 0x4140 +#define VOL_mmSCL4_SCL_COEF_RAM_SELECT 0x4340 +#define VOL_mmSCL5_SCL_COEF_RAM_SELECT 0x4540 +#define VOL_mmSCL_COEF_RAM_TAP_DATA 0x1b41 +#define VOL_mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 +#define VOL_mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 +#define VOL_mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 +#define VOL_mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 +#define VOL_mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 +#define VOL_mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 +#define VOL_mmSCL_MODE 0x1b42 +#define VOL_mmSCL0_SCL_MODE 0x1b42 +#define VOL_mmSCL1_SCL_MODE 0x1d42 +#define VOL_mmSCL2_SCL_MODE 0x1f42 +#define VOL_mmSCL3_SCL_MODE 0x4142 +#define VOL_mmSCL4_SCL_MODE 0x4342 +#define VOL_mmSCL5_SCL_MODE 0x4542 +#define VOL_mmSCL_TAP_CONTROL 0x1b43 +#define VOL_mmSCL0_SCL_TAP_CONTROL 0x1b43 +#define VOL_mmSCL1_SCL_TAP_CONTROL 0x1d43 +#define VOL_mmSCL2_SCL_TAP_CONTROL 0x1f43 +#define VOL_mmSCL3_SCL_TAP_CONTROL 0x4143 +#define VOL_mmSCL4_SCL_TAP_CONTROL 0x4343 +#define VOL_mmSCL5_SCL_TAP_CONTROL 0x4543 +#define VOL_mmSCL_CONTROL 0x1b44 +#define VOL_mmSCL0_SCL_CONTROL 0x1b44 +#define VOL_mmSCL1_SCL_CONTROL 0x1d44 +#define VOL_mmSCL2_SCL_CONTROL 0x1f44 +#define VOL_mmSCL3_SCL_CONTROL 0x4144 +#define VOL_mmSCL4_SCL_CONTROL 0x4344 +#define VOL_mmSCL5_SCL_CONTROL 0x4544 +#define VOL_mmSCL_BYPASS_CONTROL 0x1b45 +#define VOL_mmSCL0_SCL_BYPASS_CONTROL 0x1b45 +#define VOL_mmSCL1_SCL_BYPASS_CONTROL 0x1d45 +#define VOL_mmSCL2_SCL_BYPASS_CONTROL 0x1f45 +#define VOL_mmSCL3_SCL_BYPASS_CONTROL 0x4145 +#define VOL_mmSCL4_SCL_BYPASS_CONTROL 0x4345 +#define VOL_mmSCL5_SCL_BYPASS_CONTROL 0x4545 +#define VOL_mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define VOL_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define VOL_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 +#define VOL_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 +#define VOL_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define VOL_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 +#define VOL_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 +#define VOL_mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define VOL_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define VOL_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 +#define VOL_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 +#define VOL_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define VOL_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 +#define VOL_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 +#define VOL_mmSCL_HORZ_FILTER_CONTROL 0x1b48 +#define VOL_mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 +#define VOL_mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 +#define VOL_mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 +#define VOL_mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 +#define VOL_mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 +#define VOL_mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 +#define VOL_mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define VOL_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define VOL_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 +#define VOL_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 +#define VOL_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 +#define VOL_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 +#define VOL_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 +#define VOL_mmSCL_HORZ_FILTER_INIT 0x1b4a +#define VOL_mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a +#define VOL_mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a +#define VOL_mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a +#define VOL_mmSCL3_SCL_HORZ_FILTER_INIT 0x414a +#define VOL_mmSCL4_SCL_HORZ_FILTER_INIT 0x434a +#define VOL_mmSCL5_SCL_HORZ_FILTER_INIT 0x454a +#define VOL_mmSCL_VERT_FILTER_CONTROL 0x1b4b +#define VOL_mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b +#define VOL_mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b +#define VOL_mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b +#define VOL_mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b +#define VOL_mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b +#define VOL_mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b +#define VOL_mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define VOL_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define VOL_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c +#define VOL_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c +#define VOL_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c +#define VOL_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c +#define VOL_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c +#define VOL_mmSCL_VERT_FILTER_INIT 0x1b4d +#define VOL_mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d +#define VOL_mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d +#define VOL_mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d +#define VOL_mmSCL3_SCL_VERT_FILTER_INIT 0x414d +#define VOL_mmSCL4_SCL_VERT_FILTER_INIT 0x434d +#define VOL_mmSCL5_SCL_VERT_FILTER_INIT 0x454d +#define VOL_mmSCL_VERT_FILTER_INIT_BOT 0x1b4e +#define VOL_mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e +#define VOL_mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e +#define VOL_mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e +#define VOL_mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e +#define VOL_mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e +#define VOL_mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e +#define VOL_mmSCL_ROUND_OFFSET 0x1b4f +#define VOL_mmSCL0_SCL_ROUND_OFFSET 0x1b4f +#define VOL_mmSCL1_SCL_ROUND_OFFSET 0x1d4f +#define VOL_mmSCL2_SCL_ROUND_OFFSET 0x1f4f +#define VOL_mmSCL3_SCL_ROUND_OFFSET 0x414f +#define VOL_mmSCL4_SCL_ROUND_OFFSET 0x434f +#define VOL_mmSCL5_SCL_ROUND_OFFSET 0x454f +#define VOL_mmSCL_UPDATE 0x1b51 +#define VOL_mmSCL0_SCL_UPDATE 0x1b51 +#define VOL_mmSCL1_SCL_UPDATE 0x1d51 +#define VOL_mmSCL2_SCL_UPDATE 0x1f51 +#define VOL_mmSCL3_SCL_UPDATE 0x4151 +#define VOL_mmSCL4_SCL_UPDATE 0x4351 +#define VOL_mmSCL5_SCL_UPDATE 0x4551 +#define VOL_mmSCL_F_SHARP_CONTROL 0x1b53 +#define VOL_mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 +#define VOL_mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 +#define VOL_mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 +#define VOL_mmSCL3_SCL_F_SHARP_CONTROL 0x4153 +#define VOL_mmSCL4_SCL_F_SHARP_CONTROL 0x4353 +#define VOL_mmSCL5_SCL_F_SHARP_CONTROL 0x4553 +#define VOL_mmSCL_ALU_CONTROL 0x1b54 +#define VOL_mmSCL0_SCL_ALU_CONTROL 0x1b54 +#define VOL_mmSCL1_SCL_ALU_CONTROL 0x1d54 +#define VOL_mmSCL2_SCL_ALU_CONTROL 0x1f54 +#define VOL_mmSCL3_SCL_ALU_CONTROL 0x4154 +#define VOL_mmSCL4_SCL_ALU_CONTROL 0x4354 +#define VOL_mmSCL5_SCL_ALU_CONTROL 0x4554 +#define VOL_mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define VOL_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define VOL_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 +#define VOL_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 +#define VOL_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define VOL_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 +#define VOL_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 +#define VOL_mmVIEWPORT_START_SECONDARY 0x1b5b +#define VOL_mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b +#define VOL_mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b +#define VOL_mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b +#define VOL_mmSCL3_VIEWPORT_START_SECONDARY 0x415b +#define VOL_mmSCL4_VIEWPORT_START_SECONDARY 0x435b +#define VOL_mmSCL5_VIEWPORT_START_SECONDARY 0x455b +#define VOL_mmVIEWPORT_START 0x1b5c +#define VOL_mmSCL0_VIEWPORT_START 0x1b5c +#define VOL_mmSCL1_VIEWPORT_START 0x1d5c +#define VOL_mmSCL2_VIEWPORT_START 0x1f5c +#define VOL_mmSCL3_VIEWPORT_START 0x415c +#define VOL_mmSCL4_VIEWPORT_START 0x435c +#define VOL_mmSCL5_VIEWPORT_START 0x455c +#define VOL_mmVIEWPORT_SIZE 0x1b5d +#define VOL_mmSCL0_VIEWPORT_SIZE 0x1b5d +#define VOL_mmSCL1_VIEWPORT_SIZE 0x1d5d +#define VOL_mmSCL2_VIEWPORT_SIZE 0x1f5d +#define VOL_mmSCL3_VIEWPORT_SIZE 0x415d +#define VOL_mmSCL4_VIEWPORT_SIZE 0x435d +#define VOL_mmSCL5_VIEWPORT_SIZE 0x455d +#define VOL_mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define VOL_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define VOL_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e +#define VOL_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e +#define VOL_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e +#define VOL_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e +#define VOL_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e +#define VOL_mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define VOL_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define VOL_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f +#define VOL_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f +#define VOL_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f +#define VOL_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f +#define VOL_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f +#define VOL_mmSCL_MODE_CHANGE_DET1 0x1b60 +#define VOL_mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 +#define VOL_mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 +#define VOL_mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 +#define VOL_mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 +#define VOL_mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 +#define VOL_mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 +#define VOL_mmSCL_MODE_CHANGE_DET2 0x1b61 +#define VOL_mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 +#define VOL_mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 +#define VOL_mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 +#define VOL_mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 +#define VOL_mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 +#define VOL_mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 +#define VOL_mmSCL_MODE_CHANGE_DET3 0x1b62 +#define VOL_mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 +#define VOL_mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 +#define VOL_mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 +#define VOL_mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 +#define VOL_mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 +#define VOL_mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 +#define VOL_mmSCL_MODE_CHANGE_MASK 0x1b63 +#define VOL_mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 +#define VOL_mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 +#define VOL_mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 +#define VOL_mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 +#define VOL_mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 +#define VOL_mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 +#define VOL_mmSCL_DEBUG2 0x1b69 +#define VOL_mmSCL0_SCL_DEBUG2 0x1b69 +#define VOL_mmSCL1_SCL_DEBUG2 0x1d69 +#define VOL_mmSCL2_SCL_DEBUG2 0x1f69 +#define VOL_mmSCL3_SCL_DEBUG2 0x4169 +#define VOL_mmSCL4_SCL_DEBUG2 0x4369 +#define VOL_mmSCL5_SCL_DEBUG2 0x4569 +#define VOL_mmSCL_DEBUG 0x1b6a +#define VOL_mmSCL0_SCL_DEBUG 0x1b6a +#define VOL_mmSCL1_SCL_DEBUG 0x1d6a +#define VOL_mmSCL2_SCL_DEBUG 0x1f6a +#define VOL_mmSCL3_SCL_DEBUG 0x416a +#define VOL_mmSCL4_SCL_DEBUG 0x436a +#define VOL_mmSCL5_SCL_DEBUG 0x456a +#define VOL_mmSCL_TEST_DEBUG_INDEX 0x1b6b +#define VOL_mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b +#define VOL_mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b +#define VOL_mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b +#define VOL_mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b +#define VOL_mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b +#define VOL_mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b +#define VOL_mmSCL_TEST_DEBUG_DATA 0x1b6c +#define VOL_mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c +#define VOL_mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c +#define VOL_mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c +#define VOL_mmSCL3_SCL_TEST_DEBUG_DATA 0x416c +#define VOL_mmSCL4_SCL_TEST_DEBUG_DATA 0x436c +#define VOL_mmSCL5_SCL_TEST_DEBUG_DATA 0x456c +#define VOL_mmSCLV_COEF_RAM_SELECT 0x4670 +#define VOL_mmSCLV_COEF_RAM_TAP_DATA 0x4671 +#define VOL_mmSCLV_MODE 0x4672 +#define VOL_mmSCLV_TAP_CONTROL 0x4673 +#define VOL_mmSCLV_CONTROL 0x4674 +#define VOL_mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 +#define VOL_mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 +#define VOL_mmSCLV_HORZ_FILTER_CONTROL 0x4677 +#define VOL_mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 +#define VOL_mmSCLV_HORZ_FILTER_INIT 0x4679 +#define VOL_mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a +#define VOL_mmSCLV_HORZ_FILTER_INIT_C 0x467b +#define VOL_mmSCLV_VERT_FILTER_CONTROL 0x467c +#define VOL_mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d +#define VOL_mmSCLV_VERT_FILTER_INIT 0x467e +#define VOL_mmSCLV_VERT_FILTER_INIT_BOT 0x467f +#define VOL_mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 +#define VOL_mmSCLV_VERT_FILTER_INIT_C 0x4681 +#define VOL_mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 +#define VOL_mmSCLV_ROUND_OFFSET 0x4683 +#define VOL_mmSCLV_UPDATE 0x4684 +#define VOL_mmSCLV_ALU_CONTROL 0x4685 +#define VOL_mmSCLV_VIEWPORT_START 0x4686 +#define VOL_mmSCLV_VIEWPORT_START_SECONDARY 0x4687 +#define VOL_mmSCLV_VIEWPORT_SIZE 0x4688 +#define VOL_mmSCLV_VIEWPORT_START_C 0x4689 +#define VOL_mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a +#define VOL_mmSCLV_VIEWPORT_SIZE_C 0x468b +#define VOL_mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c +#define VOL_mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d +#define VOL_mmSCLV_MODE_CHANGE_DET1 0x468e +#define VOL_mmSCLV_MODE_CHANGE_DET2 0x468f +#define VOL_mmSCLV_MODE_CHANGE_DET3 0x4690 +#define VOL_mmSCLV_MODE_CHANGE_MASK 0x4691 +#define VOL_mmSCLV_DEBUG2 0x4692 +#define VOL_mmSCLV_DEBUG 0x4693 +#define VOL_mmSCLV_TEST_DEBUG_INDEX 0x4694 +#define VOL_mmSCLV_TEST_DEBUG_DATA 0x4695 +#define VOL_mmCOL_MAN_UPDATE 0x46a4 +#define VOL_mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 +#define VOL_mmINPUT_CSC_C11_C12_A 0x46a6 +#define VOL_mmINPUT_CSC_C13_C14_A 0x46a7 +#define VOL_mmINPUT_CSC_C21_C22_A 0x46a8 +#define VOL_mmINPUT_CSC_C23_C24_A 0x46a9 +#define VOL_mmINPUT_CSC_C31_C32_A 0x46aa +#define VOL_mmINPUT_CSC_C33_C34_A 0x46ab +#define VOL_mmINPUT_CSC_C11_C12_B 0x46ac +#define VOL_mmINPUT_CSC_C13_C14_B 0x46ad +#define VOL_mmINPUT_CSC_C21_C22_B 0x46ae +#define VOL_mmINPUT_CSC_C23_C24_B 0x46af +#define VOL_mmINPUT_CSC_C31_C32_B 0x46b0 +#define VOL_mmINPUT_CSC_C33_C34_B 0x46b1 +#define VOL_mmPRESCALE_CONTROL 0x46b2 +#define VOL_mmPRESCALE_VALUES_R 0x46b3 +#define VOL_mmPRESCALE_VALUES_G 0x46b4 +#define VOL_mmPRESCALE_VALUES_B 0x46b5 +#define VOL_mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 +#define VOL_mmOUTPUT_CSC_C11_C12_A 0x46b7 +#define VOL_mmOUTPUT_CSC_C13_C14_A 0x46b8 +#define VOL_mmOUTPUT_CSC_C21_C22_A 0x46b9 +#define VOL_mmOUTPUT_CSC_C23_C24_A 0x46ba +#define VOL_mmOUTPUT_CSC_C31_C32_A 0x46bb +#define VOL_mmOUTPUT_CSC_C33_C34_A 0x46bc +#define VOL_mmOUTPUT_CSC_C11_C12_B 0x46bd +#define VOL_mmOUTPUT_CSC_C13_C14_B 0x46be +#define VOL_mmOUTPUT_CSC_C21_C22_B 0x46bf +#define VOL_mmOUTPUT_CSC_C23_C24_B 0x46c0 +#define VOL_mmOUTPUT_CSC_C31_C32_B 0x46c1 +#define VOL_mmOUTPUT_CSC_C33_C34_B 0x46c2 +#define VOL_mmDENORM_CLAMP_CONTROL 0x46c3 +#define VOL_mmDENORM_CLAMP_RANGE_R_CR 0x46c4 +#define VOL_mmDENORM_CLAMP_RANGE_G_Y 0x46c5 +#define VOL_mmDENORM_CLAMP_RANGE_B_CB 0x46c6 +#define VOL_mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 +#define VOL_mmGAMMA_CORR_CONTROL 0x46c8 +#define VOL_mmGAMMA_CORR_LUT_INDEX 0x46c9 +#define VOL_mmGAMMA_CORR_LUT_DATA 0x46ca +#define VOL_mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb +#define VOL_mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc +#define VOL_mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd +#define VOL_mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce +#define VOL_mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf +#define VOL_mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 +#define VOL_mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 +#define VOL_mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 +#define VOL_mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 +#define VOL_mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 +#define VOL_mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 +#define VOL_mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 +#define VOL_mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 +#define VOL_mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 +#define VOL_mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 +#define VOL_mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da +#define VOL_mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db +#define VOL_mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc +#define VOL_mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd +#define VOL_mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de +#define VOL_mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df +#define VOL_mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 +#define VOL_mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 +#define VOL_mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 +#define VOL_mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 +#define VOL_mmCOL_MAN_TEST_DEBUG_INDEX 0x46e4 +#define VOL_mmCOL_MAN_TEST_DEBUG_DATA 0x46e5 +#define VOL_mmCOL_MAN_DEBUG_CONTROL 0x46e6 +#define VOL_mmUNP_GRPH_ENABLE 0x4600 +#define VOL_mmUNP_GRPH_CONTROL 0x4601 +#define VOL_mmUNP_GRPH_CONTROL_EXP 0x4603 +#define VOL_mmUNP_GRPH_SWAP_CNTL 0x4605 +#define VOL_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 +#define VOL_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 +#define VOL_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 +#define VOL_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 +#define VOL_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a +#define VOL_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b +#define VOL_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c +#define VOL_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d +#define VOL_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e +#define VOL_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f +#define VOL_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 +#define VOL_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 +#define VOL_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 +#define VOL_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 +#define VOL_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 +#define VOL_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 +#define VOL_mmUNP_GRPH_PITCH_L 0x4616 +#define VOL_mmUNP_GRPH_PITCH_C 0x4617 +#define VOL_mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 +#define VOL_mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 +#define VOL_mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a +#define VOL_mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b +#define VOL_mmUNP_GRPH_X_START_L 0x461c +#define VOL_mmUNP_GRPH_X_START_C 0x461d +#define VOL_mmUNP_GRPH_Y_START_L 0x461e +#define VOL_mmUNP_GRPH_Y_START_C 0x461f +#define VOL_mmUNP_GRPH_X_END_L 0x4620 +#define VOL_mmUNP_GRPH_X_END_C 0x4621 +#define VOL_mmUNP_GRPH_Y_END_L 0x4622 +#define VOL_mmUNP_GRPH_Y_END_C 0x4623 +#define VOL_mmUNP_GRPH_UPDATE 0x4624 +#define VOL_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 +#define VOL_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 +#define VOL_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 +#define VOL_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 +#define VOL_mmUNP_GRPH_DFQ_CONTROL 0x4629 +#define VOL_mmUNP_GRPH_DFQ_STATUS 0x462a +#define VOL_mmUNP_GRPH_INTERRUPT_STATUS 0x462b +#define VOL_mmUNP_GRPH_INTERRUPT_CONTROL 0x462c +#define VOL_mmUNP_GRPH_STEREOSYNC_FLIP 0x462e +#define VOL_mmUNP_GRPH_FLIP_RATE_CNTL 0x462f +#define VOL_mmUNP_CRC_CONTROL 0x4630 +#define VOL_mmUNP_CRC_MASK 0x4631 +#define VOL_mmUNP_CRC_CURRENT 0x4632 +#define VOL_mmUNP_CRC_LAST 0x4633 +#define VOL_mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 +#define VOL_mmUNP_HW_ROTATION 0x4635 +#define VOL_mmUNP_DEBUG 0x4636 +#define VOL_mmUNP_DEBUG2 0x4637 +#define VOL_mmUNP_TEST_DEBUG_INDEX 0x4638 +#define VOL_mmUNP_TEST_DEBUG_DATA 0x4639 +#define VOL_mmGENMO_WT 0xf0 +#define VOL_mmGENMO_RD 0xf3 +#define VOL_mmGENENB 0xf0 +#define VOL_mmGENFC_WT 0xee +#define VOL_mmVGA0_GENFC_WT 0xee +#define VOL_mmVGA1_GENFC_WT 0xf6 +#define VOL_mmGENFC_RD 0xf2 +#define VOL_mmGENS0 0xf0 +#define VOL_mmGENS1 0xee +#define VOL_mmVGA0_GENS1 0xee +#define VOL_mmVGA1_GENS1 0xf6 +#define VOL_mmDAC_DATA 0xf2 +#define VOL_mmDAC_MASK 0xf1 +#define VOL_mmDAC_R_INDEX 0xf1 +#define VOL_mmDAC_W_INDEX 0xf2 +#define VOL_mmSEQ8_IDX 0xf1 +#define VOL_mmSEQ8_DATA 0xf1 +#define VOL_ixSEQ00 0x0 +#define VOL_ixSEQ01 0x1 +#define VOL_ixSEQ02 0x2 +#define VOL_ixSEQ03 0x3 +#define VOL_ixSEQ04 0x4 +#define VOL_mmCRTC8_IDX 0xed +#define VOL_mmVGA0_CRTC8_IDX 0xed +#define VOL_mmVGA1_CRTC8_IDX 0xf5 +#define VOL_mmCRTC8_DATA 0xed +#define VOL_mmVGA0_CRTC8_DATA 0xed +#define VOL_mmVGA1_CRTC8_DATA 0xf5 +#define VOL_ixCRT00 0x0 +#define VOL_ixCRT01 0x1 +#define VOL_ixCRT02 0x2 +#define VOL_ixCRT03 0x3 +#define VOL_ixCRT04 0x4 +#define VOL_ixCRT05 0x5 +#define VOL_ixCRT06 0x6 +#define VOL_ixCRT07 0x7 +#define VOL_ixCRT08 0x8 +#define VOL_ixCRT09 0x9 +#define VOL_ixCRT0A 0xa +#define VOL_ixCRT0B 0xb +#define VOL_ixCRT0C 0xc +#define VOL_ixCRT0D 0xd +#define VOL_ixCRT0E 0xe +#define VOL_ixCRT0F 0xf +#define VOL_ixCRT10 0x10 +#define VOL_ixCRT11 0x11 +#define VOL_ixCRT12 0x12 +#define VOL_ixCRT13 0x13 +#define VOL_ixCRT14 0x14 +#define VOL_ixCRT15 0x15 +#define VOL_ixCRT16 0x16 +#define VOL_ixCRT17 0x17 +#define VOL_ixCRT18 0x18 +#define VOL_ixCRT1E 0x1e +#define VOL_ixCRT1F 0x1f +#define VOL_ixCRT22 0x22 +#define VOL_mmGRPH8_IDX 0xf3 +#define VOL_mmGRPH8_DATA 0xf3 +#define VOL_ixGRA00 0x0 +#define VOL_ixGRA01 0x1 +#define VOL_ixGRA02 0x2 +#define VOL_ixGRA03 0x3 +#define VOL_ixGRA04 0x4 +#define VOL_ixGRA05 0x5 +#define VOL_ixGRA06 0x6 +#define VOL_ixGRA07 0x7 +#define VOL_ixGRA08 0x8 +#define VOL_mmATTRX 0xf0 +#define VOL_mmATTRDW 0xf0 +#define VOL_mmATTRDR 0xf0 +#define VOL_ixATTR00 0x0 +#define VOL_ixATTR01 0x1 +#define VOL_ixATTR02 0x2 +#define VOL_ixATTR03 0x3 +#define VOL_ixATTR04 0x4 +#define VOL_ixATTR05 0x5 +#define VOL_ixATTR06 0x6 +#define VOL_ixATTR07 0x7 +#define VOL_ixATTR08 0x8 +#define VOL_ixATTR09 0x9 +#define VOL_ixATTR0A 0xa +#define VOL_ixATTR0B 0xb +#define VOL_ixATTR0C 0xc +#define VOL_ixATTR0D 0xd +#define VOL_ixATTR0E 0xe +#define VOL_ixATTR0F 0xf +#define VOL_ixATTR10 0x10 +#define VOL_ixATTR11 0x11 +#define VOL_ixATTR12 0x12 +#define VOL_ixATTR13 0x13 +#define VOL_ixATTR14 0x14 +#define VOL_mmVGA_RENDER_CONTROL 0xc0 +#define VOL_mmVGA_SOURCE_SELECT 0xfc +#define VOL_mmVGA_SEQUENCER_RESET_CONTROL 0xc1 +#define VOL_mmVGA_MODE_CONTROL 0xc2 +#define VOL_mmVGA_SURFACE_PITCH_SELECT 0xc3 +#define VOL_mmVGA_MEMORY_BASE_ADDRESS 0xc4 +#define VOL_mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 +#define VOL_mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 +#define VOL_mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 +#define VOL_mmVGA_HDP_CONTROL 0xca +#define VOL_mmVGA_CACHE_CONTROL 0xcb +#define VOL_mmD1VGA_CONTROL 0xcc +#define VOL_mmD2VGA_CONTROL 0xce +#define VOL_mmD3VGA_CONTROL 0xf8 +#define VOL_mmD4VGA_CONTROL 0xf9 +#define VOL_mmD5VGA_CONTROL 0xfa +#define VOL_mmD6VGA_CONTROL 0xfb +#define VOL_mmVGA_HW_DEBUG 0xcf +#define VOL_mmVGA_STATUS 0xd0 +#define VOL_mmVGA_INTERRUPT_CONTROL 0xd1 +#define VOL_mmVGA_STATUS_CLEAR 0xd2 +#define VOL_mmVGA_INTERRUPT_STATUS 0xd3 +#define VOL_mmVGA_MAIN_CONTROL 0xd4 +#define VOL_mmVGA_TEST_CONTROL 0xd5 +#define VOL_mmVGA_DEBUG_READBACK_INDEX 0xd6 +#define VOL_mmVGA_DEBUG_READBACK_DATA 0xd7 +#define VOL_mmVGA_MEM_WRITE_PAGE_ADDR 0x12 +#define VOL_mmVGA_MEM_READ_PAGE_ADDR 0x13 +#define VOL_mmVGA_TEST_DEBUG_INDEX 0xc5 +#define VOL_mmVGA_TEST_DEBUG_DATA 0xc7 +#define VOL_ixVGADCC_DBG_DCCIF_C 0x7e +#define VOL_mmBPHYC_DAC_MACRO_CNTL 0x48b9 +#define VOL_mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba +#define VOL_mmPLL_REF_DIV 0x1700 +#define VOL_mmBPHYC_PLL0_PLL_REF_DIV 0x1700 +#define VOL_mmBPHYC_PLL1_PLL_REF_DIV 0x172a +#define VOL_mmBPHYC_PLL2_PLL_REF_DIV 0x1754 +#define VOL_mmPLL_FB_DIV 0x1701 +#define VOL_mmBPHYC_PLL0_PLL_FB_DIV 0x1701 +#define VOL_mmBPHYC_PLL1_PLL_FB_DIV 0x172b +#define VOL_mmBPHYC_PLL2_PLL_FB_DIV 0x1755 +#define VOL_mmPLL_POST_DIV 0x1702 +#define VOL_mmBPHYC_PLL0_PLL_POST_DIV 0x1702 +#define VOL_mmBPHYC_PLL1_PLL_POST_DIV 0x172c +#define VOL_mmBPHYC_PLL2_PLL_POST_DIV 0x1756 +#define VOL_mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define VOL_mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define VOL_mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d +#define VOL_mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757 +#define VOL_mmPLL_SS_CNTL 0x1704 +#define VOL_mmBPHYC_PLL0_PLL_SS_CNTL 0x1704 +#define VOL_mmBPHYC_PLL1_PLL_SS_CNTL 0x172e +#define VOL_mmBPHYC_PLL2_PLL_SS_CNTL 0x1758 +#define VOL_mmPLL_DS_CNTL 0x1705 +#define VOL_mmBPHYC_PLL0_PLL_DS_CNTL 0x1705 +#define VOL_mmBPHYC_PLL1_PLL_DS_CNTL 0x172f +#define VOL_mmBPHYC_PLL2_PLL_DS_CNTL 0x1759 +#define VOL_mmPLL_IDCLK_CNTL 0x1706 +#define VOL_mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706 +#define VOL_mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730 +#define VOL_mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a +#define VOL_mmPLL_CNTL 0x1707 +#define VOL_mmBPHYC_PLL0_PLL_CNTL 0x1707 +#define VOL_mmBPHYC_PLL1_PLL_CNTL 0x1731 +#define VOL_mmBPHYC_PLL2_PLL_CNTL 0x175b +#define VOL_mmPLL_ANALOG 0x1708 +#define VOL_mmBPHYC_PLL0_PLL_ANALOG 0x1708 +#define VOL_mmBPHYC_PLL1_PLL_ANALOG 0x1732 +#define VOL_mmBPHYC_PLL2_PLL_ANALOG 0x175c +#define VOL_mmPLL_VREG_CNTL 0x1709 +#define VOL_mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709 +#define VOL_mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733 +#define VOL_mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d +#define VOL_mmPLL_UNLOCK_DETECT_CNTL 0x170a +#define VOL_mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a +#define VOL_mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734 +#define VOL_mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e +#define VOL_mmPLL_DEBUG_CNTL 0x170b +#define VOL_mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b +#define VOL_mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735 +#define VOL_mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f +#define VOL_mmPLL_UPDATE_LOCK 0x170c +#define VOL_mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c +#define VOL_mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736 +#define VOL_mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760 +#define VOL_mmPLL_UPDATE_CNTL 0x170d +#define VOL_mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d +#define VOL_mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737 +#define VOL_mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761 +#define VOL_mmPLL_XOR_LOCK 0x1710 +#define VOL_mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710 +#define VOL_mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a +#define VOL_mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764 +#define VOL_mmPLL_ANALOG_CNTL 0x1711 +#define VOL_mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711 +#define VOL_mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b +#define VOL_mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765 +#define VOL_mmVGA25_PPLL_REF_DIV 0x1712 +#define VOL_mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712 +#define VOL_mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c +#define VOL_mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766 +#define VOL_mmVGA28_PPLL_REF_DIV 0x1713 +#define VOL_mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713 +#define VOL_mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d +#define VOL_mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767 +#define VOL_mmVGA41_PPLL_REF_DIV 0x1714 +#define VOL_mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714 +#define VOL_mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e +#define VOL_mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768 +#define VOL_mmVGA25_PPLL_FB_DIV 0x1715 +#define VOL_mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715 +#define VOL_mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f +#define VOL_mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769 +#define VOL_mmVGA28_PPLL_FB_DIV 0x1716 +#define VOL_mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716 +#define VOL_mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740 +#define VOL_mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a +#define VOL_mmVGA41_PPLL_FB_DIV 0x1717 +#define VOL_mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717 +#define VOL_mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741 +#define VOL_mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b +#define VOL_mmVGA25_PPLL_POST_DIV 0x1718 +#define VOL_mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718 +#define VOL_mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742 +#define VOL_mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c +#define VOL_mmVGA28_PPLL_POST_DIV 0x1719 +#define VOL_mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719 +#define VOL_mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743 +#define VOL_mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d +#define VOL_mmVGA41_PPLL_POST_DIV 0x171a +#define VOL_mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a +#define VOL_mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744 +#define VOL_mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e +#define VOL_mmVGA25_PPLL_ANALOG 0x171b +#define VOL_mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b +#define VOL_mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745 +#define VOL_mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f +#define VOL_mmVGA28_PPLL_ANALOG 0x171c +#define VOL_mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c +#define VOL_mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746 +#define VOL_mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770 +#define VOL_mmVGA41_PPLL_ANALOG 0x171d +#define VOL_mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d +#define VOL_mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747 +#define VOL_mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771 +#define VOL_mmDISPPLL_BG_CNTL 0x171e +#define VOL_mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e +#define VOL_mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748 +#define VOL_mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772 +#define VOL_mmPPLL_DIV_UPDATE_DEBUG 0x171f +#define VOL_mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f +#define VOL_mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749 +#define VOL_mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773 +#define VOL_mmPPLL_STATUS_DEBUG 0x1720 +#define VOL_mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720 +#define VOL_mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a +#define VOL_mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774 +#define VOL_mmPPLL_DEBUG_MUX_CNTL 0x1721 +#define VOL_mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721 +#define VOL_mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b +#define VOL_mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775 +#define VOL_mmPPLL_SPARE0 0x1722 +#define VOL_mmBPHYC_PLL0_PPLL_SPARE0 0x1722 +#define VOL_mmBPHYC_PLL1_PPLL_SPARE0 0x174c +#define VOL_mmBPHYC_PLL2_PPLL_SPARE0 0x1776 +#define VOL_mmPPLL_SPARE1 0x1723 +#define VOL_mmBPHYC_PLL0_PPLL_SPARE1 0x1723 +#define VOL_mmBPHYC_PLL1_PPLL_SPARE1 0x174d +#define VOL_mmBPHYC_PLL2_PPLL_SPARE1 0x1777 +#define VOL_mmUNIPHY_TX_CONTROL1 0x48c0 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980 +#define VOL_mmUNIPHY_TX_CONTROL2 0x48c1 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981 +#define VOL_mmUNIPHY_TX_CONTROL3 0x48c2 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982 +#define VOL_mmUNIPHY_TX_CONTROL4 0x48c3 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983 +#define VOL_mmUNIPHY_POWER_CONTROL 0x48c4 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984 +#define VOL_mmUNIPHY_PLL_FBDIV 0x48c5 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985 +#define VOL_mmUNIPHY_PLL_CONTROL1 0x48c6 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986 +#define VOL_mmUNIPHY_PLL_CONTROL2 0x48c7 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987 +#define VOL_mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988 +#define VOL_mmUNIPHY_PLL_SS_CNTL 0x48c9 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989 +#define VOL_mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a +#define VOL_mmUNIPHY_REG_TEST_OUTPUT 0x48cb +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b +#define VOL_mmUNIPHY_ANG_BIST_CNTL 0x48cc +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c +#define VOL_mmUNIPHY_REG_TEST_OUTPUT2 0x48cd +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d +#define VOL_mmUNIPHY_TMDP_REG0 0x48ce +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e +#define VOL_mmUNIPHY_TMDP_REG1 0x48cf +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f +#define VOL_mmUNIPHY_TMDP_REG2 0x48d0 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990 +#define VOL_mmUNIPHY_TMDP_REG3 0x48d1 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991 +#define VOL_mmUNIPHY_TMDP_REG4 0x48d2 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992 +#define VOL_mmUNIPHY_TMDP_REG5 0x48d3 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993 +#define VOL_mmUNIPHY_TMDP_REG6 0x48d4 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994 +#define VOL_mmUNIPHY_TPG_CONTROL 0x48d5 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995 +#define VOL_mmUNIPHY_TPG_SEED 0x48d6 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996 +#define VOL_mmUNIPHY_DEBUG 0x48d7 +#define VOL_mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7 +#define VOL_mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7 +#define VOL_mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917 +#define VOL_mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937 +#define VOL_mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957 +#define VOL_mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977 +#define VOL_mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997 +#define VOL_mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define VOL_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define VOL_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 +#define VOL_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 +#define VOL_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define VOL_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 +#define VOL_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 +#define VOL_mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 +#define VOL_mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define VOL_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define VOL_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 +#define VOL_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 +#define VOL_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define VOL_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 +#define VOL_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 +#define VOL_mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 +#define VOL_mmDPG_WATERMARK_MASK_CONTROL 0x1b32 +#define VOL_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 +#define VOL_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 +#define VOL_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 +#define VOL_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 +#define VOL_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 +#define VOL_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 +#define VOL_mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL 0x4732 +#define VOL_mmDPG_PIPE_URGENCY_CONTROL 0x1b33 +#define VOL_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 +#define VOL_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 +#define VOL_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 +#define VOL_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define VOL_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 +#define VOL_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 +#define VOL_mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL 0x4733 +#define VOL_mmDPG_PIPE_DPM_CONTROL 0x1b34 +#define VOL_mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 +#define VOL_mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 +#define VOL_mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 +#define VOL_mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 +#define VOL_mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 +#define VOL_mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 +#define VOL_mmDMIF_PG6_DPG_PIPE_DPM_CONTROL 0x4734 +#define VOL_mmDPG_PIPE_STUTTER_CONTROL 0x1b35 +#define VOL_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 +#define VOL_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 +#define VOL_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 +#define VOL_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define VOL_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 +#define VOL_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 +#define VOL_mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL 0x4735 +#define VOL_mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define VOL_mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define VOL_mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 +#define VOL_mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 +#define VOL_mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define VOL_mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 +#define VOL_mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 +#define VOL_mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define VOL_mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define VOL_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define VOL_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 +#define VOL_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 +#define VOL_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define VOL_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 +#define VOL_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 +#define VOL_mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define VOL_mmDPG_REPEATER_PROGRAM 0x1b3a +#define VOL_mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a +#define VOL_mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a +#define VOL_mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a +#define VOL_mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a +#define VOL_mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a +#define VOL_mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a +#define VOL_mmDMIF_PG6_DPG_REPEATER_PROGRAM 0x473a +#define VOL_mmDPG_HW_DEBUG_A 0x1b3b +#define VOL_mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b +#define VOL_mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b +#define VOL_mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b +#define VOL_mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b +#define VOL_mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b +#define VOL_mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b +#define VOL_mmDMIF_PG6_DPG_HW_DEBUG_A 0x473b +#define VOL_mmDPG_HW_DEBUG_B 0x1b3c +#define VOL_mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c +#define VOL_mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c +#define VOL_mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c +#define VOL_mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c +#define VOL_mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c +#define VOL_mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c +#define VOL_mmDMIF_PG6_DPG_HW_DEBUG_B 0x473c +#define VOL_mmDPG_HW_DEBUG_11 0x1b3d +#define VOL_mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d +#define VOL_mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d +#define VOL_mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d +#define VOL_mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d +#define VOL_mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d +#define VOL_mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d +#define VOL_mmDMIF_PG6_DPG_HW_DEBUG_11 0x473d +#define VOL_mmDPG_TEST_DEBUG_INDEX 0x1b38 +#define VOL_mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 +#define VOL_mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 +#define VOL_mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 +#define VOL_mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 +#define VOL_mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 +#define VOL_mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 +#define VOL_mmDMIF_PG6_DPG_TEST_DEBUG_INDEX 0x4738 +#define VOL_mmDPG_TEST_DEBUG_DATA 0x1b39 +#define VOL_mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 +#define VOL_mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 +#define VOL_mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 +#define VOL_mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 +#define VOL_mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 +#define VOL_mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 +#define VOL_mmDMIF_PG6_DPG_TEST_DEBUG_DATA 0x4739 +#define VOL_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define VOL_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define VOL_ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 +#define VOL_ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 +#define VOL_ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define VOL_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define VOL_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 +#define VOL_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 +#define VOL_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a +#define VOL_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b +#define VOL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c +#define VOL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d +#define VOL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e +#define VOL_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f +#define VOL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 +#define VOL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 +#define VOL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 +#define VOL_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 +#define VOL_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 +#define VOL_mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 +#define VOL_mmAZALIA_F0_CODEC_DEBUG 0x1836 +#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 +#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 +#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 +#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a +#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b +#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c +#define VOL_mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d +#define VOL_mmGLOBAL_CAPABILITIES 0x0 +#define VOL_mmMINOR_VERSION 0x0 +#define VOL_mmMAJOR_VERSION 0x0 +#define VOL_mmOUTPUT_PAYLOAD_CAPABILITY 0x1 +#define VOL_mmINPUT_PAYLOAD_CAPABILITY 0x1 +#define VOL_mmGLOBAL_CONTROL 0x2 +#define VOL_mmWAKE_ENABLE 0x3 +#define VOL_mmSTATE_CHANGE_STATUS 0x3 +#define VOL_mmGLOBAL_STATUS 0x4 +#define VOL_mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define VOL_mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define VOL_mmINTERRUPT_CONTROL 0x8 +#define VOL_mmINTERRUPT_STATUS 0x9 +#define VOL_mmWALL_CLOCK_COUNTER 0xc +#define VOL_mmSTREAM_SYNCHRONIZATION 0xe +#define VOL_mmCORB_LOWER_BASE_ADDRESS 0x10 +#define VOL_mmCORB_UPPER_BASE_ADDRESS 0x11 +#define VOL_mmCORB_WRITE_POINTER 0x12 +#define VOL_mmCORB_READ_POINTER 0x12 +#define VOL_mmCORB_CONTROL 0x13 +#define VOL_mmCORB_STATUS 0x13 +#define VOL_mmCORB_SIZE 0x13 +#define VOL_mmRIRB_LOWER_BASE_ADDRESS 0x14 +#define VOL_mmRIRB_UPPER_BASE_ADDRESS 0x15 +#define VOL_mmRIRB_WRITE_POINTER 0x16 +#define VOL_mmRESPONSE_INTERRUPT_COUNT 0x16 +#define VOL_mmRIRB_CONTROL 0x17 +#define VOL_mmRIRB_STATUS 0x17 +#define VOL_mmRIRB_SIZE 0x17 +#define VOL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 +#define VOL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define VOL_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define VOL_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 +#define VOL_mmIMMEDIATE_COMMAND_STATUS 0x1a +#define VOL_mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c +#define VOL_mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d +#define VOL_mmWALL_CLOCK_COUNTER_ALIAS 0x80c +#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 +#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 +#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 +#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 +#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 +#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 +#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 +#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 +#define VOL_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 +#define VOL_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define VOL_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define VOL_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define VOL_ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define VOL_ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define VOL_ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define VOL_ixAUDIO_DESCRIPTOR0 0x1 +#define VOL_ixAUDIO_DESCRIPTOR1 0x2 +#define VOL_ixAUDIO_DESCRIPTOR2 0x3 +#define VOL_ixAUDIO_DESCRIPTOR3 0x4 +#define VOL_ixAUDIO_DESCRIPTOR4 0x5 +#define VOL_ixAUDIO_DESCRIPTOR5 0x6 +#define VOL_ixAUDIO_DESCRIPTOR6 0x7 +#define VOL_ixAUDIO_DESCRIPTOR7 0x8 +#define VOL_ixAUDIO_DESCRIPTOR8 0x9 +#define VOL_ixAUDIO_DESCRIPTOR9 0xa +#define VOL_ixAUDIO_DESCRIPTOR10 0xb +#define VOL_ixAUDIO_DESCRIPTOR11 0xc +#define VOL_ixAUDIO_DESCRIPTOR12 0xd +#define VOL_ixAUDIO_DESCRIPTOR13 0xe +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 +#define VOL_ixSINK_DESCRIPTION0 0x5 +#define VOL_ixSINK_DESCRIPTION1 0x6 +#define VOL_ixSINK_DESCRIPTION2 0x7 +#define VOL_ixSINK_DESCRIPTION3 0x8 +#define VOL_ixSINK_DESCRIPTION4 0x9 +#define VOL_ixSINK_DESCRIPTION5 0xa +#define VOL_ixSINK_DESCRIPTION6 0xb +#define VOL_ixSINK_DESCRIPTION7 0xc +#define VOL_ixSINK_DESCRIPTION8 0xd +#define VOL_ixSINK_DESCRIPTION9 0xe +#define VOL_ixSINK_DESCRIPTION10 0xf +#define VOL_ixSINK_DESCRIPTION11 0x10 +#define VOL_ixSINK_DESCRIPTION12 0x11 +#define VOL_ixSINK_DESCRIPTION13 0x12 +#define VOL_ixSINK_DESCRIPTION14 0x13 +#define VOL_ixSINK_DESCRIPTION15 0x14 +#define VOL_ixSINK_DESCRIPTION16 0x15 +#define VOL_ixSINK_DESCRIPTION17 0x16 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define VOL_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define VOL_ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define VOL_ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define VOL_mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 +#define VOL_mmAZALIA_AUDIO_DTO 0x17e5 +#define VOL_mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 +#define VOL_mmAZALIA_SCLK_CONTROL 0x17e7 +#define VOL_mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 +#define VOL_mmAZALIA_DATA_DMA_CONTROL 0x17e9 +#define VOL_mmAZALIA_BDL_DMA_CONTROL 0x17ea +#define VOL_mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb +#define VOL_mmAZALIA_CORB_DMA_CONTROL 0x17ec +#define VOL_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 +#define VOL_mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 +#define VOL_mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 +#define VOL_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 +#define VOL_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 +#define VOL_mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 +#define VOL_mmAZALIA_CONTROLLER_DEBUG 0x17f9 +#define VOL_mmAZALIA_MEM_PWR_CTRL 0x1810 +#define VOL_mmAZALIA_MEM_PWR_STATUS 0x1811 +#define VOL_mmDCI_PG_DEBUG_CONFIG 0x1812 +#define VOL_mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb +#define VOL_mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc +#define VOL_mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd +#define VOL_mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe +#define VOL_mmAZALIA_INPUT_CRC0_RESULT 0x17ff +#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 +#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 +#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 +#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 +#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 +#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 +#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 +#define VOL_ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 +#define VOL_mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 +#define VOL_mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 +#define VOL_mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 +#define VOL_mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 +#define VOL_mmAZALIA_INPUT_CRC1_RESULT 0x1804 +#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 +#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 +#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 +#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 +#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 +#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 +#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 +#define VOL_ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 +#define VOL_mmAZALIA_CRC0_CONTROL0 0x1805 +#define VOL_mmAZALIA_CRC0_CONTROL1 0x1806 +#define VOL_mmAZALIA_CRC0_CONTROL2 0x1807 +#define VOL_mmAZALIA_CRC0_CONTROL3 0x1808 +#define VOL_mmAZALIA_CRC0_RESULT 0x1809 +#define VOL_ixAZALIA_CRC0_CHANNEL0 0x0 +#define VOL_ixAZALIA_CRC0_CHANNEL1 0x1 +#define VOL_ixAZALIA_CRC0_CHANNEL2 0x2 +#define VOL_ixAZALIA_CRC0_CHANNEL3 0x3 +#define VOL_ixAZALIA_CRC0_CHANNEL4 0x4 +#define VOL_ixAZALIA_CRC0_CHANNEL5 0x5 +#define VOL_ixAZALIA_CRC0_CHANNEL6 0x6 +#define VOL_ixAZALIA_CRC0_CHANNEL7 0x7 +#define VOL_mmAZALIA_CRC1_CONTROL0 0x180a +#define VOL_mmAZALIA_CRC1_CONTROL1 0x180b +#define VOL_mmAZALIA_CRC1_CONTROL2 0x180c +#define VOL_mmAZALIA_CRC1_CONTROL3 0x180d +#define VOL_mmAZALIA_CRC1_RESULT 0x180e +#define VOL_ixAZALIA_CRC1_CHANNEL0 0x0 +#define VOL_ixAZALIA_CRC1_CHANNEL1 0x1 +#define VOL_ixAZALIA_CRC1_CHANNEL2 0x2 +#define VOL_ixAZALIA_CRC1_CHANNEL3 0x3 +#define VOL_ixAZALIA_CRC1_CHANNEL4 0x4 +#define VOL_ixAZALIA_CRC1_CHANNEL5 0x5 +#define VOL_ixAZALIA_CRC1_CHANNEL6 0x6 +#define VOL_ixAZALIA_CRC1_CHANNEL7 0x7 +#define VOL_mmAZ_TEST_DEBUG_INDEX 0x181f +#define VOL_mmAZ_TEST_DEBUG_DATA 0x1820 +#define VOL_mmAZALIA_STREAM_INDEX 0x1780 +#define VOL_mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 +#define VOL_mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 +#define VOL_mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 +#define VOL_mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 +#define VOL_mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 +#define VOL_mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a +#define VOL_mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c +#define VOL_mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e +#define VOL_mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 +#define VOL_mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 +#define VOL_mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 +#define VOL_mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 +#define VOL_mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 +#define VOL_mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca +#define VOL_mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc +#define VOL_mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce +#define VOL_mmAZALIA_STREAM_DATA 0x1781 +#define VOL_mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 +#define VOL_mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 +#define VOL_mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 +#define VOL_mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 +#define VOL_mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 +#define VOL_mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b +#define VOL_mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d +#define VOL_mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f +#define VOL_mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 +#define VOL_mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 +#define VOL_mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 +#define VOL_mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 +#define VOL_mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 +#define VOL_mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb +#define VOL_mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd +#define VOL_mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf +#define VOL_ixAZALIA_FIFO_SIZE_CONTROL 0x0 +#define VOL_ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 +#define VOL_ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 +#define VOL_ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 +#define VOL_ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 +#define VOL_ixAZALIA_STREAM_DEBUG 0x5 +#define VOL_mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define VOL_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define VOL_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac +#define VOL_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 +#define VOL_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 +#define VOL_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 +#define VOL_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc +#define VOL_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 +#define VOL_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 +#define VOL_mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define VOL_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define VOL_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad +#define VOL_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 +#define VOL_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 +#define VOL_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 +#define VOL_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd +#define VOL_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 +#define VOL_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd +#define VOL_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe +#define VOL_ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define VOL_ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 +#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a +#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b +#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c +#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d +#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e +#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f +#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 +#define VOL_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 +#define VOL_ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 +#define VOL_ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a +#define VOL_ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b +#define VOL_ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c +#define VOL_ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d +#define VOL_ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e +#define VOL_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define VOL_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define VOL_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 +#define VOL_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc +#define VOL_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 +#define VOL_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 +#define VOL_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 +#define VOL_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec +#define VOL_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 +#define VOL_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define VOL_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define VOL_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 +#define VOL_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd +#define VOL_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 +#define VOL_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 +#define VOL_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 +#define VOL_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed +#define VOL_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 +#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 +#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define VOL_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 +#define VOL_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define VOL_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 +#define VOL_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 +#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define VOL_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define VOL_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define VOL_mmBLND_CONTROL 0x1b6d +#define VOL_mmBLND0_BLND_CONTROL 0x1b6d +#define VOL_mmBLND1_BLND_CONTROL 0x1d6d +#define VOL_mmBLND2_BLND_CONTROL 0x1f6d +#define VOL_mmBLND3_BLND_CONTROL 0x416d +#define VOL_mmBLND4_BLND_CONTROL 0x436d +#define VOL_mmBLND5_BLND_CONTROL 0x456d +#define VOL_mmBLND6_BLND_CONTROL 0x476d +#define VOL_mmSM_CONTROL2 0x1b6e +#define VOL_mmBLND0_SM_CONTROL2 0x1b6e +#define VOL_mmBLND1_SM_CONTROL2 0x1d6e +#define VOL_mmBLND2_SM_CONTROL2 0x1f6e +#define VOL_mmBLND3_SM_CONTROL2 0x416e +#define VOL_mmBLND4_SM_CONTROL2 0x436e +#define VOL_mmBLND5_SM_CONTROL2 0x456e +#define VOL_mmBLND6_SM_CONTROL2 0x476e +#define VOL_mmBLND_CONTROL2 0x1b6f +#define VOL_mmBLND0_BLND_CONTROL2 0x1b6f +#define VOL_mmBLND1_BLND_CONTROL2 0x1d6f +#define VOL_mmBLND2_BLND_CONTROL2 0x1f6f +#define VOL_mmBLND3_BLND_CONTROL2 0x416f +#define VOL_mmBLND4_BLND_CONTROL2 0x436f +#define VOL_mmBLND5_BLND_CONTROL2 0x456f +#define VOL_mmBLND6_BLND_CONTROL2 0x476f +#define VOL_mmBLND_UPDATE 0x1b70 +#define VOL_mmBLND0_BLND_UPDATE 0x1b70 +#define VOL_mmBLND1_BLND_UPDATE 0x1d70 +#define VOL_mmBLND2_BLND_UPDATE 0x1f70 +#define VOL_mmBLND3_BLND_UPDATE 0x4170 +#define VOL_mmBLND4_BLND_UPDATE 0x4370 +#define VOL_mmBLND5_BLND_UPDATE 0x4570 +#define VOL_mmBLND6_BLND_UPDATE 0x4770 +#define VOL_mmBLND_UNDERFLOW_INTERRUPT 0x1b71 +#define VOL_mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 +#define VOL_mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 +#define VOL_mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 +#define VOL_mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 +#define VOL_mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 +#define VOL_mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 +#define VOL_mmBLND6_BLND_UNDERFLOW_INTERRUPT 0x4771 +#define VOL_mmBLND_V_UPDATE_LOCK 0x1b73 +#define VOL_mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 +#define VOL_mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 +#define VOL_mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 +#define VOL_mmBLND3_BLND_V_UPDATE_LOCK 0x4173 +#define VOL_mmBLND4_BLND_V_UPDATE_LOCK 0x4373 +#define VOL_mmBLND5_BLND_V_UPDATE_LOCK 0x4573 +#define VOL_mmBLND6_BLND_V_UPDATE_LOCK 0x4773 +#define VOL_mmBLND_REG_UPDATE_STATUS 0x1b77 +#define VOL_mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 +#define VOL_mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 +#define VOL_mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 +#define VOL_mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 +#define VOL_mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 +#define VOL_mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 +#define VOL_mmBLND6_BLND_REG_UPDATE_STATUS 0x4777 +#define VOL_mmBLND_DEBUG 0x1b74 +#define VOL_mmBLND0_BLND_DEBUG 0x1b74 +#define VOL_mmBLND1_BLND_DEBUG 0x1d74 +#define VOL_mmBLND2_BLND_DEBUG 0x1f74 +#define VOL_mmBLND3_BLND_DEBUG 0x4174 +#define VOL_mmBLND4_BLND_DEBUG 0x4374 +#define VOL_mmBLND5_BLND_DEBUG 0x4574 +#define VOL_mmBLND6_BLND_DEBUG 0x4774 +#define VOL_mmBLND_TEST_DEBUG_INDEX 0x1b75 +#define VOL_mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 +#define VOL_mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 +#define VOL_mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 +#define VOL_mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 +#define VOL_mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 +#define VOL_mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 +#define VOL_mmBLND6_BLND_TEST_DEBUG_INDEX 0x4775 +#define VOL_mmBLND_TEST_DEBUG_DATA 0x1b76 +#define VOL_mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 +#define VOL_mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 +#define VOL_mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 +#define VOL_mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 +#define VOL_mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 +#define VOL_mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 +#define VOL_mmBLND6_BLND_TEST_DEBUG_DATA 0x4776 +#define VOL_mmWB_ENABLE 0x5e18 +#define VOL_mmWB_EC_CONFIG 0x5e19 +#define VOL_mmCNV_MODE 0x5e1a +#define VOL_mmCNV_WINDOW_START 0x5e1b +#define VOL_mmCNV_WINDOW_SIZE 0x5e1c +#define VOL_mmCNV_UPDATE 0x5e1d +#define VOL_mmCNV_SOURCE_SIZE 0x5e1e +#define VOL_mmCNV_CSC_CONTROL 0x5e1f +#define VOL_mmCNV_CSC_C11_C12 0x5e20 +#define VOL_mmCNV_CSC_C13_C14 0x5e21 +#define VOL_mmCNV_CSC_C21_C22 0x5e22 +#define VOL_mmCNV_CSC_C23_C24 0x5e23 +#define VOL_mmCNV_CSC_C31_C32 0x5e24 +#define VOL_mmCNV_CSC_C33_C34 0x5e25 +#define VOL_mmCNV_CSC_ROUND_OFFSET_R 0x5e26 +#define VOL_mmCNV_CSC_ROUND_OFFSET_G 0x5e27 +#define VOL_mmCNV_CSC_ROUND_OFFSET_B 0x5e28 +#define VOL_mmCNV_CSC_CLAMP_R 0x5e29 +#define VOL_mmCNV_CSC_CLAMP_G 0x5e2a +#define VOL_mmCNV_CSC_CLAMP_B 0x5e2b +#define VOL_mmCNV_TEST_CNTL 0x5e2c +#define VOL_mmCNV_TEST_CRC_RED 0x5e2d +#define VOL_mmCNV_TEST_CRC_GREEN 0x5e2e +#define VOL_mmCNV_TEST_CRC_BLUE 0x5e2f +#define VOL_mmWB_DEBUG_CTRL 0x5e30 +#define VOL_mmWB_DBG_MODE 0x5e31 +#define VOL_mmWB_HW_DEBUG 0x5e32 +#define VOL_mmCNV_INPUT_SELECT 0x5e33 +#define VOL_mmWB_SOFT_RESET 0x5e36 +#define VOL_mmCNV_TEST_DEBUG_INDEX 0x5e34 +#define VOL_mmCNV_TEST_DEBUG_DATA 0x5e35 +#define VOL_mmDCFE_CLOCK_CONTROL 0x1b00 +#define VOL_mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 +#define VOL_mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 +#define VOL_mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 +#define VOL_mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 +#define VOL_mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 +#define VOL_mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 +#define VOL_mmDCFE_SOFT_RESET 0x1b01 +#define VOL_mmDCFE0_DCFE_SOFT_RESET 0x1b01 +#define VOL_mmDCFE1_DCFE_SOFT_RESET 0x1d01 +#define VOL_mmDCFE2_DCFE_SOFT_RESET 0x1f01 +#define VOL_mmDCFE3_DCFE_SOFT_RESET 0x4101 +#define VOL_mmDCFE4_DCFE_SOFT_RESET 0x4301 +#define VOL_mmDCFE5_DCFE_SOFT_RESET 0x4501 +#define VOL_mmDCFE_DBG_CONFIG 0x1b02 +#define VOL_mmDCFE0_DCFE_DBG_CONFIG 0x1b02 +#define VOL_mmDCFE1_DCFE_DBG_CONFIG 0x1d02 +#define VOL_mmDCFE2_DCFE_DBG_CONFIG 0x1f02 +#define VOL_mmDCFE3_DCFE_DBG_CONFIG 0x4102 +#define VOL_mmDCFE4_DCFE_DBG_CONFIG 0x4302 +#define VOL_mmDCFE5_DCFE_DBG_CONFIG 0x4502 +#define VOL_mmDCFEV_CLOCK_CONTROL 0x46f4 +#define VOL_mmDCFEV_SOFT_RESET 0x46f5 +#define VOL_mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 +#define VOL_mmDCFEV_DBG_CONFIG 0x46f7 +#define VOL_mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 +#define VOL_mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 +#define VOL_mmDC_HPD_INT_STATUS 0x1898 +#define VOL_mmHPD0_DC_HPD_INT_STATUS 0x1898 +#define VOL_mmHPD1_DC_HPD_INT_STATUS 0x18a0 +#define VOL_mmHPD2_DC_HPD_INT_STATUS 0x18a8 +#define VOL_mmHPD3_DC_HPD_INT_STATUS 0x18b0 +#define VOL_mmHPD4_DC_HPD_INT_STATUS 0x18b8 +#define VOL_mmHPD5_DC_HPD_INT_STATUS 0x18c0 +#define VOL_mmDC_HPD_INT_CONTROL 0x1899 +#define VOL_mmHPD0_DC_HPD_INT_CONTROL 0x1899 +#define VOL_mmHPD1_DC_HPD_INT_CONTROL 0x18a1 +#define VOL_mmHPD2_DC_HPD_INT_CONTROL 0x18a9 +#define VOL_mmHPD3_DC_HPD_INT_CONTROL 0x18b1 +#define VOL_mmHPD4_DC_HPD_INT_CONTROL 0x18b9 +#define VOL_mmHPD5_DC_HPD_INT_CONTROL 0x18c1 +#define VOL_mmDC_HPD_CONTROL 0x189a +#define VOL_mmHPD0_DC_HPD_CONTROL 0x189a +#define VOL_mmHPD1_DC_HPD_CONTROL 0x18a2 +#define VOL_mmHPD2_DC_HPD_CONTROL 0x18aa +#define VOL_mmHPD3_DC_HPD_CONTROL 0x18b2 +#define VOL_mmHPD4_DC_HPD_CONTROL 0x18ba +#define VOL_mmHPD5_DC_HPD_CONTROL 0x18c2 +#define VOL_mmDC_HPD_FAST_TRAIN_CNTL 0x189b +#define VOL_mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b +#define VOL_mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 +#define VOL_mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab +#define VOL_mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 +#define VOL_mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb +#define VOL_mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 +#define VOL_mmDC_HPD_TOGGLE_FILT_CNTL 0x189c +#define VOL_mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c +#define VOL_mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 +#define VOL_mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac +#define VOL_mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 +#define VOL_mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc +#define VOL_mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 +#define VOL_mmDCO_SCRATCH0 0x184e +#define VOL_mmDCO_SCRATCH1 0x184f +#define VOL_mmDCO_SCRATCH2 0x1850 +#define VOL_mmDCO_SCRATCH3 0x1851 +#define VOL_mmDCO_SCRATCH4 0x1852 +#define VOL_mmDCO_SCRATCH5 0x1853 +#define VOL_mmDCO_SCRATCH6 0x1854 +#define VOL_mmDCO_SCRATCH7 0x1855 +#define VOL_mmDCE_VCE_CONTROL 0x1856 +#define VOL_mmDISP_INTERRUPT_STATUS 0x1857 +#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 +#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 +#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a +#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b +#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c +#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d +#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e +#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f +#define VOL_mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 +#define VOL_mmDCO_MEM_PWR_STATUS 0x1861 +#define VOL_mmDCO_MEM_PWR_CTRL 0x1862 +#define VOL_mmDCO_MEM_PWR_CTRL2 0x1863 +#define VOL_mmDCO_CLK_CNTL 0x1864 +#define VOL_mmDCO_CLK_RAMP_CNTL 0x1865 +#define VOL_mmDPDBG_CNTL 0x1866 +#define VOL_mmDPDBG_INTERRUPT 0x1867 +#define VOL_mmDCO_POWER_MANAGEMENT_CNTL 0x1868 +#define VOL_mmDCO_SOFT_RESET 0x1871 +#define VOL_mmDIG_SOFT_RESET 0x1872 +#define VOL_mmDCO_STEREOSYNC_SEL 0x186e +#define VOL_mmDCO_TEST_DEBUG_INDEX 0x186f +#define VOL_mmDCO_TEST_DEBUG_DATA 0x1870 +#define VOL_mmDC_I2C_CONTROL 0x16d4 +#define VOL_mmDC_I2C_ARBITRATION 0x16d5 +#define VOL_mmDC_I2C_INTERRUPT_CONTROL 0x16d6 +#define VOL_mmDC_I2C_SW_STATUS 0x16d7 +#define VOL_mmDC_I2C_DDC1_HW_STATUS 0x16d8 +#define VOL_mmDC_I2C_DDC2_HW_STATUS 0x16d9 +#define VOL_mmDC_I2C_DDC3_HW_STATUS 0x16da +#define VOL_mmDC_I2C_DDC4_HW_STATUS 0x16db +#define VOL_mmDC_I2C_DDC5_HW_STATUS 0x16dc +#define VOL_mmDC_I2C_DDC6_HW_STATUS 0x16dd +#define VOL_mmDC_I2C_DDC1_SPEED 0x16de +#define VOL_mmDC_I2C_DDC1_SETUP 0x16df +#define VOL_mmDC_I2C_DDC2_SPEED 0x16e0 +#define VOL_mmDC_I2C_DDC2_SETUP 0x16e1 +#define VOL_mmDC_I2C_DDC3_SPEED 0x16e2 +#define VOL_mmDC_I2C_DDC3_SETUP 0x16e3 +#define VOL_mmDC_I2C_DDC4_SPEED 0x16e4 +#define VOL_mmDC_I2C_DDC4_SETUP 0x16e5 +#define VOL_mmDC_I2C_DDC5_SPEED 0x16e6 +#define VOL_mmDC_I2C_DDC5_SETUP 0x16e7 +#define VOL_mmDC_I2C_DDC6_SPEED 0x16e8 +#define VOL_mmDC_I2C_DDC6_SETUP 0x16e9 +#define VOL_mmDC_I2C_TRANSACTION0 0x16ea +#define VOL_mmDC_I2C_TRANSACTION1 0x16eb +#define VOL_mmDC_I2C_TRANSACTION2 0x16ec +#define VOL_mmDC_I2C_TRANSACTION3 0x16ed +#define VOL_mmDC_I2C_DATA 0x16ee +#define VOL_mmDC_I2C_DDCVGA_HW_STATUS 0x16ef +#define VOL_mmDC_I2C_DDCVGA_SPEED 0x16f0 +#define VOL_mmDC_I2C_DDCVGA_SETUP 0x16f1 +#define VOL_mmDC_I2C_EDID_DETECT_CTRL 0x16f2 +#define VOL_mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 +#define VOL_mmGENERIC_I2C_CONTROL 0x16f4 +#define VOL_mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 +#define VOL_mmGENERIC_I2C_STATUS 0x16f6 +#define VOL_mmGENERIC_I2C_SPEED 0x16f7 +#define VOL_mmGENERIC_I2C_SETUP 0x16f8 +#define VOL_mmGENERIC_I2C_TRANSACTION 0x16f9 +#define VOL_mmGENERIC_I2C_DATA 0x16fa +#define VOL_mmGENERIC_I2C_PIN_SELECTION 0x16fb +#define VOL_mmGENERIC_I2C_PIN_DEBUG 0x16fc +#define VOL_mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 +#define VOL_mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 +#define VOL_mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 +#define VOL_mmXDMA_INTERRUPT 0x3e3 +#define VOL_mmXDMA_CLOCK_GATING_CNTL 0x3e4 +#define VOL_mmXDMA_MEM_POWER_CNTL 0x3e6 +#define VOL_mmXDMA_IF_BIF_STATUS 0x3e7 +#define VOL_mmXDMA_PERF_MEAS_STATUS 0x3e8 +#define VOL_mmXDMA_IF_STATUS 0x3e9 +#define VOL_mmXDMA_TEST_DEBUG_INDEX 0x3ea +#define VOL_mmXDMA_TEST_DEBUG_DATA 0x3eb +#define VOL_mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 +#define VOL_mmXDMA_PG_CONTROL 0x3f9 +#define VOL_mmXDMA_PG_WDATA 0x3fa +#define VOL_mmXDMA_PG_STATUS 0x3fb +#define VOL_mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc +#define VOL_mmXDMA_AON_TEST_DEBUG_DATA 0x3fd +#define VOL_mmXDMA_MSTR_CNTL 0x3ec +#define VOL_mmXDMA_MSTR_STATUS 0x3ed +#define VOL_mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee +#define VOL_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef +#define VOL_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 +#define VOL_mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 +#define VOL_mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 +#define VOL_mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 +#define VOL_mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 +#define VOL_mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 +#define VOL_mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 +#define VOL_mmXDMA_MSTR_PIPE_CNTL 0x400 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 +#define VOL_mmXDMA_MSTR_READ_COMMAND 0x401 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 +#define VOL_mmXDMA_MSTR_CHANNEL_DIM 0x402 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 +#define VOL_mmXDMA_MSTR_HEIGHT 0x403 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 +#define VOL_mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 +#define VOL_mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 +#define VOL_mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 +#define VOL_mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 +#define VOL_mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 +#define VOL_mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 +#define VOL_mmXDMA_MSTR_CACHE 0x40a +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a +#define VOL_mmXDMA_MSTR_CHANNEL_START 0x40b +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b +#define VOL_mmXDMA_MSTR_PERFMEAS_STATUS 0x40e +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e +#define VOL_mmXDMA_MSTR_PERFMEAS_CNTL 0x40f +#define VOL_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f +#define VOL_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f +#define VOL_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f +#define VOL_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f +#define VOL_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f +#define VOL_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f +#define VOL_mmXDMA_SLV_CNTL 0x460 +#define VOL_mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 +#define VOL_mmXDMA_SLV_SLS_PITCH 0x462 +#define VOL_mmXDMA_SLV_READ_URGENT_CNTL 0x463 +#define VOL_mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 +#define VOL_mmXDMA_SLV_WB_RATE_CNTL 0x465 +#define VOL_mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 +#define VOL_mmXDMA_SLV_READ_LATENCY_AVE 0x467 +#define VOL_mmXDMA_SLV_PCIE_NACK_STATUS 0x468 +#define VOL_mmXDMA_SLV_MEM_NACK_STATUS 0x469 +#define VOL_mmXDMA_SLV_RDRET_BUF_STATUS 0x46a +#define VOL_mmXDMA_SLV_READ_LATENCY_TIMER 0x46b +#define VOL_mmXDMA_SLV_FLIP_PENDING 0x46c +#define VOL_mmXDMA_SLV_CHANNEL_CNTL 0x470 +#define VOL_mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 +#define VOL_mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 +#define VOL_mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 +#define VOL_mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 +#define VOL_mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 +#define VOL_mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 +#define VOL_mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define VOL_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define VOL_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 +#define VOL_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 +#define VOL_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 +#define VOL_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 +#define VOL_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 +#define VOL_mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define VOL_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define VOL_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a +#define VOL_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 +#define VOL_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a +#define VOL_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 +#define VOL_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a + +#endif /* DCE_10_0_D_H */ diff --git a/src/add-ons/accelerants/radeon_hd/connector.cpp b/src/add-ons/accelerants/radeon_hd/connector.cpp index d3d44bdc47..3ab652780e 100644 --- a/src/add-ons/accelerants/radeon_hd/connector.cpp +++ b/src/add-ons/accelerants/radeon_hd/connector.cpp @@ -117,6 +117,60 @@ gpio_set_i2c_bit(void* cookie, int clock, int data) } +uint16 +connector_pick_atom_hpdid(uint32 connectorIndex) +{ + radeon_shared_info &info = *gInfo->shared_info; + + uint16 atomHPDID = 0xff; + uint16 hpdPinIndex = gConnector[connectorIndex]->hpdPinIndex; + if (info.dceMajor >= 4 + && gGPIOInfo[hpdPinIndex]->valid) { + + // See mmDC_GPIO_HPD_A in drm for register value + uint32 targetReg = AVIVO_DC_GPIO_HPD_A; + if (info.dceMajor >= 12) { + ERROR("WARNING: CHECK NEW DCE mmDC_GPIO_HPD_A value!\n"); + targetReg = CAR_mmDC_GPIO_HPD_A; + } else if (info.dceMajor >= 11) + targetReg = CAR_mmDC_GPIO_HPD_A; + else if (info.dceMajor >= 10) + targetReg = VOL_mmDC_GPIO_HPD_A; + else if (info.dceMajor >= 8) + targetReg = SEA_mmDC_GPIO_HPD_A; + else if (info.dceMajor >= 6) + targetReg = SI_DC_GPIO_HPD_A; + else if (info.dceMajor >= 4) + targetReg = EVERGREEN_DC_GPIO_HPD_A; + + // You're drunk AMD, go home. (this makes no sense) + if (gGPIOInfo[hpdPinIndex]->hwReg == targetReg) { + switch(gGPIOInfo[hpdPinIndex]->hwMask) { + case (1 << 0): + atomHPDID = 0; + break; + case (1 << 8): + atomHPDID = 1; + break; + case (1 << 16): + atomHPDID = 2; + break; + case (1 << 24): + atomHPDID = 3; + break; + case (1 << 26): + atomHPDID = 4; + break; + case (1 << 28): + atomHPDID = 5; + break; + } + } + } + return atomHPDID; +} + + bool connector_read_edid(uint32 connectorIndex, edid1_info* edid) { diff --git a/src/add-ons/accelerants/radeon_hd/connector.h b/src/add-ons/accelerants/radeon_hd/connector.h index df69c339c6..1b95e04505 100644 --- a/src/add-ons/accelerants/radeon_hd/connector.h +++ b/src/add-ons/accelerants/radeon_hd/connector.h @@ -69,5 +69,7 @@ status_t connector_probe_legacy(); bool connector_is_dp(uint32 connectorIndex); void debug_connectors(); +uint16 connector_pick_atom_hpdid(uint32 connectorIndex); + #endif /* RADEON_HD_CONNECTOR_H */ diff --git a/src/add-ons/accelerants/radeon_hd/displayport.cpp b/src/add-ons/accelerants/radeon_hd/displayport.cpp index 99bfa93846..b70f92b6a8 100644 --- a/src/add-ons/accelerants/radeon_hd/displayport.cpp +++ b/src/add-ons/accelerants/radeon_hd/displayport.cpp @@ -35,8 +35,6 @@ static ssize_t dp_aux_speak(uint32 connectorIndex, uint8* send, int sendBytes, uint8* recv, int recvBytes, uint8 delay, uint8* ack) { - radeon_shared_info &info = *gInfo->shared_info; - dp_info* dpInfo = &gConnector[connectorIndex]->dpInfo; if (dpInfo->auxPin == 0) { ERROR("%s: cannot speak on invalid GPIO pin!\n", __func__); @@ -59,43 +57,8 @@ dp_aux_speak(uint32 connectorIndex, uint8* send, int sendBytes, args.v2.ucChannelID = dpInfo->auxPin; args.v2.ucDelay = delay / 10; - uint16 hpdPinIndex = gConnector[connectorIndex]->hpdPinIndex; - if (info.dceMajor >= 4 - && gGPIOInfo[hpdPinIndex]->valid) { - - uint32 targetReg = EVERGREEN_DC_GPIO_HPD_A; - if (info.dceMajor >= 6) - targetReg = SI_DC_GPIO_HPD_A; - - // You're drunk AMD, go home. (this makes no sense) - if (gGPIOInfo[hpdPinIndex]->hwReg == targetReg) { - switch(gGPIOInfo[hpdPinIndex]->hwMask) { - case (1 << 0): - args.v2.ucHPD_ID = 0; - break; - case (1 << 8): - args.v2.ucHPD_ID = 1; - break; - case (1 << 16): - args.v2.ucHPD_ID = 2; - break; - case (1 << 24): - args.v2.ucHPD_ID = 3; - break; - case (1 << 26): - args.v2.ucHPD_ID = 4; - break; - case (1 << 28): - args.v2.ucHPD_ID = 5; - break; - default: - args.v2.ucHPD_ID = 0xff; - break; - } - } else { - args.v2.ucHPD_ID = 0xff; - } - } + // Careful! This value differs in different atombios calls :-| + args.v2.ucHPD_ID = connector_pick_atom_hpdid(connectorIndex); unsigned char* base = (unsigned char*)(gAtomContext->scratch + 1); diff --git a/src/add-ons/accelerants/radeon_hd/encoder.cpp b/src/add-ons/accelerants/radeon_hd/encoder.cpp index 91d7046269..72a123ebb5 100644 --- a/src/add-ons/accelerants/radeon_hd/encoder.cpp +++ b/src/add-ons/accelerants/radeon_hd/encoder.cpp @@ -637,6 +637,9 @@ encoder_dig_setup(uint32 connectorIndex, uint32 pixelClock, int command) dualLink = true; } + // Careful! The mapping of ucHPD_ID differs between atombios calls + uint16 hpdID = connector_pick_atom_hpdid(connectorIndex); + switch (tableMinor) { case 1: args.v1.ucAction = command; @@ -784,8 +787,11 @@ encoder_dig_setup(uint32 connectorIndex, uint32 pixelClock, int command) args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; break; } - // TODO: VVV RADEON_HPD_NONE? - args.v4.ucHPD_ID = 0; + + if (hpdID == 0xff) + args.v4.ucHPD_ID = 0; + else + args.v4.ucHPD_ID = hpdID + 1; break; default: ERROR("%s: unknown tableMinor!\n", __func__);