added more definitions from specification

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22136 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Marcus Overhagen 2007-09-01 14:28:47 +00:00
parent 2c5a88945e
commit 1a941c2e04

View File

@ -11,6 +11,41 @@
#define AHCI_DEVICE_MODULE_NAME "busses/scsi/ahci/device_v1"
#define AHCI_SIM_MODULE_NAME "busses/scsi/ahci/sim/v1"
enum {
CAP_S64A = (1 << 31), // Supports 64-bit Addressing
CAP_SNCQ = (1 << 30), // Supports Native Command Queuing
CAP_SSNTF = (1 << 29), // Supports SNotification Register
CAP_SMPS = (1 << 28), // Supports Mechanical Presence Switch
CAP_SSS = (1 << 27), // Supports Staggered Spin-up
CAP_SALP = (1 << 26), // Supports Aggressive Link Power Management
CAP_SAL = (1 << 25), // Supports Activity LED
CAP_SCLO = (1 << 24), // Supports Command List Override
CAP_ISS_MASK = 0xf, // Interface Speed Support
CAP_ISS_SHIFT = 20,
CAP_SNZO = (1 << 19), // Supports Non-Zero DMA Offsets
CAP_SAM = (1 << 18), // Supports AHCI mode only
CAP_SPM = (1 << 17), // Supports Port Multiplier
CAP_FBSS = (1 << 16), // FIS-based Switching Supported
CAP_PMD = (1 << 15), // PIO Multiple DRQ Block
CAP_SSC = (1 << 14), // Slumber State Capable
CAP_PSC = (1 << 13), // Partial State Capable
CAP_NCS_MASK = 0x1f, // Number of Command Slots
CAP_NCS_SHIFT = 8,
CAP_CCCS = (1 << 7), // Command Completion Coalescing Supported
CAP_EMS = (1 << 6), // Enclosure Management Supported
CAP_SXS = (1 << 5), // Supports External SATA
CAP_NP_MASK = 0x1f, // Number of Ports
CAP_NP_SHIFT = 0,
};
enum {
GHC_AE = (1 << 31), // AHCI Enable
GHC_MRSM = (1 << 2), // MSI Revert to Single Message
GHC_IE = (1 << 1), // Interrupt Enable
GHC_HR = (1 << 0), // HBA Reset
};
typedef struct {
uint32 clb; // Command List Base Address
@ -50,6 +85,7 @@ typedef struct {
ahci_port port[32];
} ahci_hba;
extern scsi_sim_interface gAHCISimInterface;
extern device_manager_info *gDeviceManager;
extern pci_device_module_info *gPCI;