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added MAVEN/DAC output selection programming for singlehead cards with a MAVEN: now TVout (kindof) works here :). Still in progress..

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17387 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2006-05-09 11:46:51 +00:00
parent dd665ef198
commit 19f65af1dd
3 changed files with 31 additions and 10 deletions
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5
src/add-ons/accelerants/matrox/SetDisplayMode.c
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@ -357,7 +357,10 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
case G200:
case G400:
case G400MAX:
gx00_general_dac_select(DS_CRTC1DAC_CRTC2MAVEN);
if (!si->ps.secondary_head && si->ps.tvout && (target.flags & TV_BITS))
gx00_general_dac_select(DS_CRTC1MAVEN);
else
gx00_general_dac_select(DS_CRTC1DAC);
break;
case G450:
case G550:

15
src/add-ons/accelerants/matrox/engine/mga_general.c
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@ -792,34 +792,33 @@ status_t gx50_general_output_select()
return B_OK;
}
/*connect CRTC1 to the specified DAC*/
/* connect CRTC(s) to the specified DAC(s) */
status_t gx00_general_dac_select(int dac)
{
if (!si->ps.secondary_head)
return B_ERROR;
/*MISCCTRL, clock src,...*/
switch(dac)
{
/* G400 */
/* G100 - G400 */
case DS_CRTC1DAC:
case DS_CRTC1DAC_CRTC2MAVEN:
/* connect CRTC1 to pixPLL */
DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0xc)|0x1);
/* connect CRTC2 to vidPLL, connect CRTC1 to internal DAC and
* enable CRTC2 external video timing reset signal.
* (Setting for MAVEN 'master mode' TVout signal generation.) */
CR2W(CTL,(CR2R(CTL)&0xffe00779)|0xD0000002);
if (si->ps.secondary_head) CR2W(CTL,(CR2R(CTL)&0xffe00779)|0xD0000002);
/* disable CRTC1 external video timing reset signal */
VGAW_I(CRTCEXT,1,(VGAR_I(CRTCEXT,1)&0x77));
/* select CRTC2 RGB24 MAFC mode: connects CRTC2 to MAVEN DAC */
DXIW(MISCCTRL,(DXIR(MISCCTRL)&0x19)|0x82);
break;
case DS_CRTC1MAVEN:
case DS_CRTC1MAVEN_CRTC2DAC:
/* connect CRTC1 to vidPLL */
DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0xc)|0x2);
/* connect CRTC2 to pixPLL and internal DAC and
* disable CRTC2 external video timing reset signal */
CR2W(CTL,(CR2R(CTL)&0x2fe00779)|0x4|(0x1<<20));
if (si->ps.secondary_head) CR2W(CTL,(CR2R(CTL)&0x2fe00779)|0x4|(0x1<<20));
/* enable CRTC1 external video timing reset signal.
* note: this is nolonger used as G450/G550 cannot do TVout on CRTC1 */
VGAW_I(CRTCEXT,1,(VGAR_I(CRTCEXT,1)|0x88));
@ -828,6 +827,7 @@ status_t gx00_general_dac_select(int dac)
break;
/* G450/G550 */
case DS_CRTC1CON1_CRTC2CON2:
if (si->ps.card_type < G450) return B_ERROR;
/* connect CRTC1 to pixPLL */
DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0xc)|0x1);
/* connect CRTC2 to vidPLL, connect CRTC1 to DAC1, disable CRTC2
@ -848,6 +848,7 @@ status_t gx00_general_dac_select(int dac)
//fixme: toggle PLL's below if possible:
// otherwise toggle PLL's for G400 2nd case?
case DS_CRTC1CON2_CRTC2CON1:
if (si->ps.card_type < G450) return B_ERROR;
/* connect CRTC1 to pixPLL */
DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0xc)|0x1);
/* connect CRTC2 to vidPLL and DAC1, disable CRTC2 external

21
src/add-ons/accelerants/matrox/engine/mga_proto.h
View File

@ -125,5 +125,22 @@ status_t gx00_release_bes(void);
status_t i2c_sec_tv_adapter(void);
/*driver structures and enums*/
enum{BPP8=0,BPP15=1,BPP16=2,BPP24=3,BPP32DIR=4,BPP32=7};
enum{DS_CRTC1DAC_CRTC2MAVEN, DS_CRTC1MAVEN_CRTC2DAC, DS_CRTC1CON1_CRTC2CON2, DS_CRTC1CON2_CRTC2CON1};
enum
{
BPP8 = 0,
BPP15 = 1,
BPP16 = 2,
BPP24 = 3,
BPP32DIR = 4,
BPP32 = 7
};
enum
{
DS_CRTC1DAC,
DS_CRTC1MAVEN,
DS_CRTC1DAC_CRTC2MAVEN,
DS_CRTC1MAVEN_CRTC2DAC,
DS_CRTC1CON1_CRTC2CON2,
DS_CRTC1CON2_CRTC2CON1
};