uart: Remove due to mmu's new (better) UART code
This commit is contained in:
Alexander von Gluck IV
parent
e9ec7a55dd
commit
182643f763
@ -1,58 +0,0 @@
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/*
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* Copyright (c) 2008 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
|
||||
* (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
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||||
*
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||||
* The above copyright notice and this permission notice shall be
|
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* included in all copies or substantial portions of the Software.
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||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __DEV_UART_8250_H
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#define __DEV_UART_8250_H
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#include <SupportDefs.h>
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#include <sys/types.h>
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class Uart8250 {
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public:
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Uart8250(addr_t base);
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~Uart8250();
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void InitEarly();
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void Init();
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void InitPort(uint32 baud);
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void Enable();
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void Disable();
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int PutChar(char c);
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int GetChar(bool wait);
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void FlushTx();
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void FlushRx();
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private:
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void WriteUart(uint32 reg, unsigned char data);
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unsigned char ReadUart(uint32 reg);
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bool fUARTEnabled;
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addr_t fUARTBase;
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};
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#endif
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@ -1,173 +0,0 @@
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/*
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* Copyright 2011-2012 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Alexander von Gluck, kallisti5@unixzen.com
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*/
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#ifndef __DEV_UART_PL011_H
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#define __DEV_UART_PL011_H
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#include <sys/types.h>
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#include <SupportDefs.h>
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#define PL01x_DR 0x00 // Data read or written
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#define PL01x_RSR 0x04 // Receive status, read
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#define PL01x_ECR 0x04 // Error clear, write
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#define PL010_LCRH 0x08 // Line control, high
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#define PL010_LCRM 0x0C // Line control, middle
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#define PL010_LCRL 0x10 // Line control, low
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#define PL010_CR 0x14 // Control
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#define PL01x_FR 0x18 // Flag (r/o)
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#define PL010_IIR 0x1C // Interrupt ID (r)
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#define PL010_ICR 0x1C // Interrupt clear (w)
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#define PL01x_ILPR 0x20 // IrDA low power
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#define PL011_IBRD 0x24 // Interrupt baud rate divisor
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#define PL011_FBRD 0x28 // Fractional baud rate divisor
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#define PL011_LCRH 0x2C // Line control
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#define PL011_CR 0x30 // Control
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#define PL011_IFLS 0x34 // Interrupt fifo level
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#define PL011_IMSC 0x38 // Interrupt mask
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#define PL011_RIS 0x3C // Raw interrupt
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#define PL011_MIS 0x40 // Masked interrupt
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#define PL011_ICR 0x44 // Interrupt clear
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#define PL011_DMACR 0x48 // DMA control register
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#define PL011_DR_OE (1 << 11)
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#define PL011_DR_BE (1 << 10)
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#define PL011_DR_PE (1 << 9)
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#define PL011_DR_FE (1 << 8)
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#define PL01x_RSR_OE 0x08
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#define PL01x_RSR_BE 0x04
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#define PL01x_RSR_PE 0x02
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#define PL01x_RSR_FE 0x01
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#define PL011_FR_RI 0x100
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#define PL011_FR_TXFE 0x080
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#define PL011_FR_RXFF 0x040
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#define PL01x_FR_TXFF 0x020
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#define PL01x_FR_RXFE 0x010
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#define PL01x_FR_BUSY 0x008
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#define PL01x_FR_DCD 0x004
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#define PL01x_FR_DSR 0x002
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#define PL01x_FR_CTS 0x001
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#define PL01x_FR_TMSK (PL01x_FR_TXFF | PL01x_FR_BUSY)
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#define PL011_CR_CTSEN 0x8000 // CTS flow control
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#define PL011_CR_RTSEN 0x4000 // RTS flow control
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#define PL011_CR_OUT2 0x2000 // OUT2
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#define PL011_CR_OUT1 0x1000 // OUT1
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#define PL011_CR_RTS 0x0800 // RTS
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#define PL011_CR_DTR 0x0400 // DTR
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#define PL011_CR_RXE 0x0200 // Receive enable
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#define PL011_CR_TXE 0x0100 // Transmit enable
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#define PL011_CR_LBE 0x0080 // Loopback enable
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#define PL010_CR_RTIE 0x0040
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#define PL010_CR_TIE 0x0020
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#define PL010_CR_RIE 0x0010
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#define PL010_CR_MSIE 0x0008
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#define PL01x_CR_IIRLP 0x0004 // SIR low power mode
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#define PL01x_CR_SIREN 0x0002 // SIR enable
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#define PL01x_CR_UARTEN 0x0001 // UART enable
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#define PL011_LCRH_SPS 0x80
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#define PL01x_LCRH_WLEN_8 0x60
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#define PL01x_LCRH_WLEN_7 0x40
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#define PL01x_LCRH_WLEN_6 0x20
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#define PL01x_LCRH_WLEN_5 0x00
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#define PL01x_LCRH_FEN 0x10
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#define PL01x_LCRH_STP2 0x08
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#define PL01x_LCRH_EPS 0x04
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#define PL01x_LCRH_PEN 0x02
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#define PL01x_LCRH_BRK 0x01
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#define PL010_IIR_RTIS 0x08
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#define PL010_IIR_TIS 0x04
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#define PL010_IIR_RIS 0x02
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#define PL010_IIR_MIS 0x01
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#define PL011_IFLS_RX1_8 (0 << 3)
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#define PL011_IFLS_RX2_8 (1 << 3)
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#define PL011_IFLS_RX4_8 (2 << 3)
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#define PL011_IFLS_RX6_8 (3 << 3)
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#define PL011_IFLS_RX7_8 (4 << 3)
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#define PL011_IFLS_TX1_8 (0 << 0)
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#define PL011_IFLS_TX2_8 (1 << 0)
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#define PL011_IFLS_TX4_8 (2 << 0)
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#define PL011_IFLS_TX6_8 (3 << 0)
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#define PL011_IFLS_TX7_8 (4 << 0)
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#define PL011_IFLS_RX_HALF (5 << 3) // ST vendor only
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#define PL011_IFLS_TX_HALF (5 << 0) // ST vendor only
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#define PL011_OEIM (1 << 10) // overrun error interrupt mask
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#define PL011_BEIM (1 << 9) // break error interrupt mask
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#define PL011_PEIM (1 << 8) // parity error interrupt mask
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#define PL011_FEIM (1 << 7) // framing error interrupt mask
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#define PL011_RTIM (1 << 6) // receive timeout interrupt mask
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#define PL011_TXIM (1 << 5) // transmit interrupt mask
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#define PL011_RXIM (1 << 4) // receive interrupt mask
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#define PL011_DSRMIM (1 << 3) // DSR interrupt mask
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#define PL011_DCDMIM (1 << 2) // DCD interrupt mask
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#define PL011_CTSMIM (1 << 1) // CTS interrupt mask
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#define PL011_RIMIM (1 << 0) // RI interrupt mask
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#define PL011_OEIS (1 << 10) // overrun error interrupt state
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#define PL011_BEIS (1 << 9) // break error interrupt state
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#define PL011_PEIS (1 << 8) // parity error interrupt state
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#define PL011_FEIS (1 << 7) // framing error interrupt state
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#define PL011_RTIS (1 << 6) // receive timeout interrupt state
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#define PL011_TXIS (1 << 5) // transmit interrupt state
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#define PL011_RXIS (1 << 4) // receive interrupt state
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#define PL011_DSRMIS (1 << 3) // DSR interrupt state
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#define PL011_DCDMIS (1 << 2) // DCD interrupt state
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#define PL011_CTSMIS (1 << 1) // CTS interrupt state
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#define PL011_RIMIS (1 << 0) // RI interrupt state
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#define PL011_OEIC (1 << 10) // overrun error interrupt clear
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#define PL011_BEIC (1 << 9) // break error interrupt clear
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#define PL011_PEIC (1 << 8) // parity error interrupt clear
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#define PL011_FEIC (1 << 7) // framing error interrupt clear
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#define PL011_RTIC (1 << 6) // receive timeout interrupt clear
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#define PL011_TXIC (1 << 5) // transmit interrupt clear
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#define PL011_RXIC (1 << 4) // receive interrupt clear
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#define PL011_DSRMIC (1 << 3) // DSR interrupt clear
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#define PL011_DCDMIC (1 << 2) // DCD interrupt clear
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#define PL011_CTSMIC (1 << 1) // CTS interrupt clear
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#define PL011_RIMIC (1 << 0) // RI interrupt clear
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#define PL011_DMAONERR (1 << 2) // disable dma on err
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#define PL011_TXDMAE (1 << 1) // enable transmit dma
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#define PL011_RXDMAE (1 << 0) // enable receive dma
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class UartPL011 {
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public:
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UartPL011(addr_t base);
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~UartPL011();
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void InitEarly();
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void InitPort(uint32 baud);
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void Enable();
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void Disable();
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int PutChar(char c);
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int GetChar(bool wait);
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void FlushTx();
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void FlushRx();
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private:
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void WriteUart(uint32 reg, uint32 data);
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uint32 ReadUart(uint32 reg);
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bool fUARTEnabled;
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addr_t fUARTBase;
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};
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#endif
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@ -1,207 +0,0 @@
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/*
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* Copyright (c) 2008 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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||||
*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <debug.h>
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#include <arch/arm/reg.h>
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#include <arch/arm/uart.h>
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#include <board_config.h>
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//#include <target/debugconfig.h>
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#define UART_SHIFT 2
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Uart8250::Uart8250(addr_t base)
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:
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fUARTEnabled(true),
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fUARTBase(base)
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{
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}
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Uart8250::~Uart8250()
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{
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}
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void
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Uart8250::WriteUart(uint32 reg, unsigned char data)
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{
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*(volatile unsigned char *)(fUARTBase + (reg << UART_SHIFT))
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= data;
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}
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unsigned char
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Uart8250::ReadUart(uint32 reg)
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{
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return *(volatile unsigned char *)(fUARTBase + (reg << UART_SHIFT));
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}
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#define LCR_8N1 0x03
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#define FCR_FIFO_EN 0x01 /* Fifo enable */
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#define FCR_RXSR 0x02 /* Receiver soft reset */
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#define FCR_TXSR 0x04 /* Transmitter soft reset */
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#define MCR_DTR 0x01
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#define MCR_RTS 0x02
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#define MCR_DMA_EN 0x04
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#define MCR_TX_DFR 0x08
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#define LCR_WLS_MSK 0x03 /* character length select mask */
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#define LCR_WLS_5 0x00 /* 5 bit character length */
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#define LCR_WLS_6 0x01 /* 6 bit character length */
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#define LCR_WLS_7 0x02 /* 7 bit character length */
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#define LCR_WLS_8 0x03 /* 8 bit character length */
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#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define LCR_PEN 0x08 /* Parity eneble */
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#define LCR_EPS 0x10 /* Even Parity Select */
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#define LCR_STKP 0x20 /* Stick Parity */
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#define LCR_SBRK 0x40 /* Set Break */
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#define LCR_BKSE 0x80 /* Bank select enable */
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#define LSR_DR 0x01 /* Data ready */
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#define LSR_OE 0x02 /* Overrun */
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#define LSR_PE 0x04 /* Parity error */
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#define LSR_FE 0x08 /* Framing error */
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#define LSR_BI 0x10 /* Break */
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#define LSR_THRE 0x20 /* Xmit holding register empty */
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#define LSR_TEMT 0x40 /* Xmitter empty */
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#define LSR_ERR 0x80 /* Error */
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void
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Uart8250::InitPort(uint32 baud)
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{
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Disable();
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uint16 baudDivisor = BOARD_UART_CLOCK / (16 * baud);
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// Write standard uart settings
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WriteUart(UART_LCR, LCR_8N1);
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// 8N1
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WriteUart(UART_IER, 0);
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// Disable interrupt
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WriteUart(UART_FCR, 0);
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// Disable FIFO
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WriteUart(UART_MCR, MCR_DTR | MCR_RTS);
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// DTR / RTS
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// Gain access to, and program baud divisor
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unsigned char buffer = ReadUart(UART_LCR);
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WriteUart(UART_LCR, buffer | LCR_BKSE);
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WriteUart(UART_DLL, baudDivisor & 0xff);
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WriteUart(UART_DLH, (baudDivisor >> 8) & 0xff);
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WriteUart(UART_LCR, buffer & ~LCR_BKSE);
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// WriteUart(UART_MDR1, 0); // UART 16x mode
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// WriteUart(UART_LCR, 0xBF); // config mode B
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// WriteUart(UART_EFR, (1<<7)|(1<<6)); // hw flow control
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// WriteUart(UART_LCR, LCR_8N1); // operational mode
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Enable();
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}
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void
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Uart8250::InitEarly()
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{
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// Perform special hardware UART configuration
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#if BOARD_CPU_OMAP3
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/* UART1 */
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RMWREG32(CM_FCLKEN1_CORE, 13, 1, 1);
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RMWREG32(CM_ICLKEN1_CORE, 13, 1, 1);
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/* UART2 */
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RMWREG32(CM_FCLKEN1_CORE, 14, 1, 1);
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RMWREG32(CM_ICLKEN1_CORE, 14, 1, 1);
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/* UART3 */
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RMWREG32(CM_FCLKEN_PER, 11, 1, 1);
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RMWREG32(CM_ICLKEN_PER, 11, 1, 1);
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#else
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#warning INTITIALIZE UART!!!!!
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#endif
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}
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void
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Uart8250::Enable()
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{
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fUARTEnabled = true;
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}
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void
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Uart8250::Disable()
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{
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fUARTEnabled = false;
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}
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int
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Uart8250::PutChar(char c)
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{
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while (!(ReadUart(UART_LSR) & (1<<6)));
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// wait for the last char to get out
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WriteUart(UART_THR, c);
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return 0;
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}
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/* returns -1 if no data available */
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int
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Uart8250::GetChar(bool wait)
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{
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if (wait) {
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while (!(ReadUart(UART_LSR) & (1<<0)));
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// wait for data to show up in the rx fifo
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} else {
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if (!(ReadUart(UART_LSR) & (1<<0)))
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return -1;
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}
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return ReadUart(UART_RHR);
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}
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void
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Uart8250::FlushTx()
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{
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while (!(ReadUart(UART_LSR) & (1<<6)));
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// wait for the last char to get out
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}
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void
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Uart8250::FlushRx()
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{
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// empty the rx fifo
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while (ReadUart(UART_LSR) & (1<<0)) {
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volatile char c = ReadUart(UART_RHR);
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(void)c;
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}
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}
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@ -1,183 +0,0 @@
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/*
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* Copyright 2011-2012 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
|
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*
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* Authors:
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* Alexander von Gluck, kallisti5@unixzen.com
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*/
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#include <debug.h>
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#include <arch/arm/reg.h>
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#include <arch/arm/uart.h>
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#include <board_config.h>
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//#include <target/debugconfig.h>
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static void
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barrier()
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{
|
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asm volatile ("" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
UartPL011::UartPL011(addr_t base)
|
||||
:
|
||||
fUARTEnabled(true),
|
||||
fUARTBase(base)
|
||||
{
|
||||
barrier();
|
||||
|
||||
// ** Loopback test
|
||||
uint32 cr = PL01x_CR_UARTEN;
|
||||
// Enable UART
|
||||
cr |= PL011_CR_TXE;
|
||||
// Enable TX
|
||||
cr |= PL011_CR_LBE;
|
||||
// Enable Loopback mode
|
||||
WriteUart(PL011_CR, cr);
|
||||
|
||||
WriteUart(PL011_FBRD, 0);
|
||||
WriteUart(PL011_IBRD, 1);
|
||||
WriteUart(PL011_LCRH, 0); // TODO: ST is different tx, rx lcr
|
||||
|
||||
// Write a 0 to the port and wait for confim..
|
||||
WriteUart(PL01x_DR, 0);
|
||||
|
||||
while (ReadUart(PL01x_FR) & PL01x_FR_BUSY)
|
||||
barrier();
|
||||
|
||||
// ** Disable loopback, enable uart
|
||||
cr = PL01x_CR_UARTEN | PL011_CR_RXE | PL011_CR_TXE;
|
||||
WriteUart(PL011_CR, cr);
|
||||
|
||||
// ** Clear interrupts
|
||||
WriteUart(PL011_ICR, PL011_OEIS | PL011_BEIS
|
||||
| PL011_PEIS | PL011_FEIS);
|
||||
|
||||
// ** Disable interrupts
|
||||
WriteUart(PL011_IMSC, 0);
|
||||
}
|
||||
|
||||
|
||||
UartPL011::~UartPL011()
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
UartPL011::WriteUart(uint32 reg, uint32 data)
|
||||
{
|
||||
*(volatile uint32*)(fUARTBase + reg) = data;
|
||||
}
|
||||
|
||||
|
||||
uint32
|
||||
UartPL011::ReadUart(uint32 reg)
|
||||
{
|
||||
return *(volatile uint32*)(fUARTBase + reg);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
UartPL011::InitPort(uint32 baud)
|
||||
{
|
||||
// Calculate baud divisor
|
||||
uint32 baudDivisor = BOARD_UART_CLOCK / (16 * baud);
|
||||
uint32 remainder = BOARD_UART_CLOCK % (16 * baud);
|
||||
uint32 baudFractional = ((8 * remainder) / baud >> 1)
|
||||
+ ((8 * remainder) / baud & 1);
|
||||
|
||||
// Disable UART
|
||||
Disable();
|
||||
|
||||
// Set baud divisor
|
||||
WriteUart(PL011_IBRD, baudDivisor);
|
||||
WriteUart(PL011_FBRD, baudFractional);
|
||||
|
||||
// Set LCR 8n1, enable fifo
|
||||
WriteUart(PL011_LCRH, PL01x_LCRH_WLEN_8 | PL01x_LCRH_FEN);
|
||||
|
||||
// Enable UART
|
||||
Enable();
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
UartPL011::InitEarly()
|
||||
{
|
||||
// Perform special hardware UART configuration
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
UartPL011::Enable()
|
||||
{
|
||||
uint32 cr = PL01x_CR_UARTEN;
|
||||
// Enable UART
|
||||
cr |= PL011_CR_TXE | PL011_CR_RXE;
|
||||
// Enable TX and RX
|
||||
|
||||
WriteUart(PL011_CR, cr);
|
||||
|
||||
fUARTEnabled = true;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
UartPL011::Disable()
|
||||
{
|
||||
// Disable everything
|
||||
WriteUart(PL011_CR, 0);
|
||||
fUARTEnabled = false;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
UartPL011::PutChar(char c)
|
||||
{
|
||||
if (fUARTEnabled == true) {
|
||||
// Wait until there is room in fifo
|
||||
while ((ReadUart(PL01x_FR) & PL01x_FR_TXFF) != 0)
|
||||
barrier();
|
||||
|
||||
WriteUart(PL01x_DR, c);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
UartPL011::GetChar(bool wait)
|
||||
{
|
||||
if (fUARTEnabled == true) {
|
||||
// Wait until a character is received?
|
||||
if (wait) {
|
||||
while ((ReadUart(PL01x_FR) & PL01x_FR_RXFE) != 0)
|
||||
barrier();
|
||||
}
|
||||
return ReadUart(PL01x_DR);
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
UartPL011::FlushTx()
|
||||
{
|
||||
// Wait until transmit fifo empty
|
||||
while ((ReadUart(PL01x_FR) & PL011_FR_TXFE) == 0)
|
||||
barrier();
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
UartPL011::FlushRx()
|
||||
{
|
||||
// Wait until receive fifo empty
|
||||
while ((ReadUart(PL01x_FR) & PL01x_FR_RXFE) == 0)
|
||||
barrier();
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user