* add digital encoder setup code
* make encoder setup functions return status_t * really need a struct to hold encoder info git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42814 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -477,7 +477,6 @@ detect_connectors()
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encoder_type = VIDEO_ENCODER_TMDS;
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// radeon_atombios_set_dig_info
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}
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// drm_encoder_helper_add
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break;
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case ENCODER_OBJECT_ID_INTERNAL_DAC1:
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encoder_type = VIDEO_ENCODER_DAC;
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@ -486,7 +485,6 @@ detect_connectors()
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
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encoder_type = VIDEO_ENCODER_TVDAC;
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// drm_encoder_helper_add
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break;
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case ENCODER_OBJECT_ID_INTERNAL_DVO1:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
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@ -769,7 +767,7 @@ display_crtc_lock(uint8 crtc_id, int command)
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args.ucCRTC = crtc_id;
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args.ucEnable = command;
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atom_execute_table(gAtomContext, index, (uint32 *)&args);
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atom_execute_table(gAtomContext, index, (uint32*)&args);
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}
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@ -188,7 +188,7 @@ encoder_mode_set(uint8 id, uint32 pixelClock)
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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case ENCODER_OBJECT_ID_INTERNAL_LVDS:
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case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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TRACE("%s: TODO for digital encoder setup\n", __func__);
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encoder_digital_setup(id, pixelClock, ATOM_ENABLE);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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@ -208,7 +208,131 @@ encoder_mode_set(uint8 id, uint32 pixelClock)
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}
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void
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union lvds_encoder_control {
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LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
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LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
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};
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status_t
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encoder_digital_setup(uint8 id, uint32 pixelClock, int command)
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{
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TRACE("%s\n", __func__);
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uint32 connector_index = gDisplay[id]->connector_index;
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union lvds_encoder_control args;
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memset(&args, 0, sizeof(args));
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int index = 0;
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uint16 connector_flags = gConnector[connector_index]->connector_flags;
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switch (gConnector[connector_index]->encoder_object_id) {
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case ENCODER_OBJECT_ID_INTERNAL_LVDS:
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index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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if (connector_flags & ATOM_DEVICE_LCD_SUPPORT)
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index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
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else
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index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
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break;
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}
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uint8 frev;
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uint8 crev;
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if (atom_parse_cmd_header(gAtomContext, index, &frev, &crev) != B_OK)
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return B_ERROR;
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switch (frev) {
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case 1:
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case 2:
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switch (crev) {
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case 1:
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args.v1.ucMisc = 0;
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args.v1.ucAction = command;
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if (0) // TODO : HDMI?
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args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
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args.v1.usPixelClock = B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
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if (connector_flags & (ATOM_DEVICE_LCD_SUPPORT)) {
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// TODO : laptop display support
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//if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
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// args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
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//if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
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// args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
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} else {
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//if (dig->linkb)
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// args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
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if (pixelClock > 165000)
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args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
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/*if (pScrn->rgbBits == 8) */
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args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
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}
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break;
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case 2:
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case 3:
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args.v2.ucMisc = 0;
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args.v2.ucAction = command;
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if (crev == 3) {
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//if (dig->coherent_mode)
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// args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
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}
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if (0) // TODO : HDMI?
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args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
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args.v2.usPixelClock = B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
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args.v2.ucTruncate = 0;
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args.v2.ucSpatial = 0;
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args.v2.ucTemporal = 0;
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args.v2.ucFRC = 0;
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if (connector_flags & ATOM_DEVICE_LCD_SUPPORT) {
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// TODO : laptop display support
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//if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
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// args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
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//if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
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args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
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//if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
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// args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
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//}
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//if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
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// args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
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// if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) {
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// args.v2.ucTemporal
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// |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
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// }
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// if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT)
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// & 0x3) == 2) {
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// args.v2.ucTemporal
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// |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
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// }
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//}
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} else {
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//if (dig->linkb)
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// args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
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if (pixelClock > 165000)
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args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
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}
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break;
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default:
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ERROR("%s: Unknown minor table version: %d.%d\n", __func__,
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frev, crev);
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return B_ERROR;
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}
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break;
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default:
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ERROR("%s: Unknown major table version: %d.%d\n", __func__,
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frev, crev);
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return B_ERROR;
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}
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return atom_execute_table(gAtomContext, index, (uint32*)&args);
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}
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status_t
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encoder_analog_setup(uint8 id, uint32 pixelClock, int command)
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{
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TRACE("%s\n", __func__);
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@ -237,7 +361,7 @@ encoder_analog_setup(uint8 id, uint32 pixelClock, int command)
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args.usPixelClock = B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
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atom_execute_table(gAtomContext, index, (uint32*)&args);
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return atom_execute_table(gAtomContext, index, (uint32*)&args);
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}
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@ -11,7 +11,8 @@
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void encoder_assign_crtc(uint8 crt_id);
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void encoder_mode_set(uint8 id, uint32 pixelClock);
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void encoder_analog_setup(uint8 id, uint32 pixelClock, int command);
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status_t encoder_digital_setup(uint8 id, uint32 pixelClock, int command);
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status_t encoder_analog_setup(uint8 id, uint32 pixelClock, int command);
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void encoder_output_lock(bool lock);
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void encoder_dpms_set(uint8 encoder_id, int mode);
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@ -40,9 +40,9 @@ get_accelerant_hook(uint32 feature, void *data)
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return (void*)radeon_dpms_capabilities;
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case B_DPMS_MODE:
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return (void*)radeon_dpms_mode;
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*/
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case B_SET_DPMS_MODE:
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return (void*)radeon_dpms_set;
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*/
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/* mode configuration */
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case B_ACCELERANT_MODE_COUNT:
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@ -137,17 +137,18 @@ radeon_set_display_mode(display_mode *mode)
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continue;
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uint16 connector_index = gDisplay[id]->connector_index;
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// *** encoder prep
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encoder_output_lock(true);
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encoder_dpms_set(gConnector[connector_index]->encoder_object_id,
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B_DPMS_OFF);
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encoder_assign_crtc(id);
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// *** CRT controler prep
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display_crtc_lock(id, ATOM_ENABLE);
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// *** CRT controler mode set
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// TODO program SS
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// TODO : program SS
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pll_set(0, mode->timing.pixel_clock, id);
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// TODO : check if pll 0 is used and use pll 1 if so
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display_crtc_set_dtd(id, mode);
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@ -158,16 +159,12 @@ radeon_set_display_mode(display_mode *mode)
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// atombios_overscan_setup
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display_crtc_scale(id, mode);
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// *** encoder mode set
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encoder_mode_set(id, mode->timing.pixel_clock);
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encoder_assign_crtc(id);
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// *** CRT controler commit
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display_crtc_lock(id, ATOM_DISABLE);
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// *** encoder commit
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encoder_dpms_set(gConnector[connector_index]->encoder_object_id,
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B_DPMS_ON);
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